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rackman/software/firmware/oracle_d21_edition/gcc/AtmelStart.lss

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AtmelStart.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000634 00000000 00000000 00010000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .relocate 00000000 20000000 20000000 00010634 2**0
CONTENTS
2 .bss 00000028 20000000 20000000 00020000 2**2
ALLOC
3 .stack 00002000 20000028 20000028 00020000 2**0
ALLOC
4 .ARM.attributes 00000028 00000000 00000000 00010634 2**0
CONTENTS, READONLY
5 .comment 0000001e 00000000 00000000 0001065c 2**0
CONTENTS, READONLY
6 .debug_info 00019aab 00000000 00000000 0001067a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
7 .debug_abbrev 000018b5 00000000 00000000 0002a125 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
8 .debug_aranges 00000708 00000000 00000000 0002b9da 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
9 .debug_ranges 000016e0 00000000 00000000 0002c0e2 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
10 .debug_macro 00004179 00000000 00000000 0002d7c2 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
11 .debug_line 0000a90e 00000000 00000000 0003193b 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
12 .debug_str 00083ff5 00000000 00000000 0003c249 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_frame 000013f8 00000000 00000000 000c0240 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_loc 00007541 00000000 00000000 000c1638 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
00000000 <exception_table>:
0: 28 20 00 20 01 01 00 00 fd 00 00 00 fd 00 00 00 ( . ............
...
2c: fd 00 00 00 00 00 00 00 00 00 00 00 fd 00 00 00 ................
3c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................
4c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................
5c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................
6c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................
7c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................
8c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................
9c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................
ac: fd 00 00 00 00 00 00 00 ........
000000b4 <__do_global_dtors_aux>:
b4: b510 push {r4, lr}
b6: 4c06 ldr r4, [pc, #24] ; (d0 <__do_global_dtors_aux+0x1c>)
b8: 7823 ldrb r3, [r4, #0]
ba: 2b00 cmp r3, #0
bc: d107 bne.n ce <__do_global_dtors_aux+0x1a>
be: 4b05 ldr r3, [pc, #20] ; (d4 <__do_global_dtors_aux+0x20>)
c0: 2b00 cmp r3, #0
c2: d002 beq.n ca <__do_global_dtors_aux+0x16>
c4: 4804 ldr r0, [pc, #16] ; (d8 <__do_global_dtors_aux+0x24>)
c6: e000 b.n ca <__do_global_dtors_aux+0x16>
c8: bf00 nop
ca: 2301 movs r3, #1
cc: 7023 strb r3, [r4, #0]
ce: bd10 pop {r4, pc}
d0: 20000000 .word 0x20000000
d4: 00000000 .word 0x00000000
d8: 00000634 .word 0x00000634
000000dc <frame_dummy>:
dc: 4b04 ldr r3, [pc, #16] ; (f0 <frame_dummy+0x14>)
de: b510 push {r4, lr}
e0: 2b00 cmp r3, #0
e2: d003 beq.n ec <frame_dummy+0x10>
e4: 4903 ldr r1, [pc, #12] ; (f4 <frame_dummy+0x18>)
e6: 4804 ldr r0, [pc, #16] ; (f8 <frame_dummy+0x1c>)
e8: e000 b.n ec <frame_dummy+0x10>
ea: bf00 nop
ec: bd10 pop {r4, pc}
ee: 46c0 nop ; (mov r8, r8)
f0: 00000000 .word 0x00000000
f4: 20000004 .word 0x20000004
f8: 00000634 .word 0x00000634
000000fc <Dummy_Handler>:
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
fc: e7fe b.n fc <Dummy_Handler>
...
00000100 <Reset_Handler>:
if (pSrc != pDest) {
100: 4925 ldr r1, [pc, #148] ; (198 <Reset_Handler+0x98>)
102: 4826 ldr r0, [pc, #152] ; (19c <Reset_Handler+0x9c>)
{
104: b570 push {r4, r5, r6, lr}
if (pSrc != pDest) {
106: 4281 cmp r1, r0
108: d00a beq.n 120 <Reset_Handler+0x20>
*pDest++ = *pSrc++;
10a: 4b25 ldr r3, [pc, #148] ; (1a0 <Reset_Handler+0xa0>)
10c: 1ec4 subs r4, r0, #3
10e: 2200 movs r2, #0
110: 42a3 cmp r3, r4
112: d303 bcc.n 11c <Reset_Handler+0x1c>
114: 3303 adds r3, #3
116: 1a1a subs r2, r3, r0
118: 0892 lsrs r2, r2, #2
11a: 0092 lsls r2, r2, #2
11c: 4b21 ldr r3, [pc, #132] ; (1a4 <Reset_Handler+0xa4>)
11e: 4798 blx r3
*pDest++ = 0;
120: 4821 ldr r0, [pc, #132] ; (1a8 <Reset_Handler+0xa8>)
122: 4b22 ldr r3, [pc, #136] ; (1ac <Reset_Handler+0xac>)
124: 1ec1 subs r1, r0, #3
126: 2200 movs r2, #0
128: 4299 cmp r1, r3
12a: d803 bhi.n 134 <Reset_Handler+0x34>
12c: 3303 adds r3, #3
12e: 1a1a subs r2, r3, r0
130: 0892 lsrs r2, r2, #2
132: 0092 lsls r2, r2, #2
134: 2100 movs r1, #0
136: 4b1e ldr r3, [pc, #120] ; (1b0 <Reset_Handler+0xb0>)
138: 4798 blx r3
SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
13a: 22ff movs r2, #255 ; 0xff
13c: 4b1d ldr r3, [pc, #116] ; (1b4 <Reset_Handler+0xb4>)
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
13e: 2103 movs r1, #3
SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
140: 4393 bics r3, r2
142: 4a1d ldr r2, [pc, #116] ; (1b8 <Reset_Handler+0xb8>)
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
144: 250c movs r5, #12
SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
146: 6093 str r3, [r2, #8]
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
148: 2202 movs r2, #2
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
14a: 2408 movs r4, #8
DMAC->QOSCTRL.bit.DQOS = 2;
14c: 2630 movs r6, #48 ; 0x30
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
14e: 4b1b ldr r3, [pc, #108] ; (1bc <Reset_Handler+0xbc>)
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
150: 481b ldr r0, [pc, #108] ; (1c0 <Reset_Handler+0xc0>)
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
152: 625a str r2, [r3, #36] ; 0x24
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
154: 78c3 ldrb r3, [r0, #3]
156: 438b bics r3, r1
158: 4313 orrs r3, r2
15a: 70c3 strb r3, [r0, #3]
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
15c: 78c3 ldrb r3, [r0, #3]
15e: 43ab bics r3, r5
160: 4323 orrs r3, r4
162: 70c3 strb r3, [r0, #3]
DMAC->QOSCTRL.bit.DQOS = 2;
164: 4b17 ldr r3, [pc, #92] ; (1c4 <Reset_Handler+0xc4>)
166: 7b98 ldrb r0, [r3, #14]
168: 43b0 bics r0, r6
16a: 0006 movs r6, r0
16c: 2020 movs r0, #32
16e: 4330 orrs r0, r6
170: 7398 strb r0, [r3, #14]
DMAC->QOSCTRL.bit.FQOS = 2;
172: 7b98 ldrb r0, [r3, #14]
174: 43a8 bics r0, r5
176: 4304 orrs r4, r0
178: 739c strb r4, [r3, #14]
DMAC->QOSCTRL.bit.WRBQOS = 2;
17a: 7b98 ldrb r0, [r3, #14]
17c: 4388 bics r0, r1
17e: 4302 orrs r2, r0
180: 739a strb r2, [r3, #14]
NVMCTRL->CTRLB.bit.MANW = 1;
182: 2380 movs r3, #128 ; 0x80
184: 4a10 ldr r2, [pc, #64] ; (1c8 <Reset_Handler+0xc8>)
186: 6851 ldr r1, [r2, #4]
188: 430b orrs r3, r1
18a: 6053 str r3, [r2, #4]
__libc_init_array();
18c: 4b0f ldr r3, [pc, #60] ; (1cc <Reset_Handler+0xcc>)
18e: 4798 blx r3
main();
190: 4b0f ldr r3, [pc, #60] ; (1d0 <Reset_Handler+0xd0>)
192: 4798 blx r3
while (1)
194: e7fe b.n 194 <Reset_Handler+0x94>
196: 46c0 nop ; (mov r8, r8)
198: 00000634 .word 0x00000634
19c: 20000000 .word 0x20000000
1a0: 20000000 .word 0x20000000
1a4: 000005b9 .word 0x000005b9
1a8: 20000000 .word 0x20000000
1ac: 20000028 .word 0x20000028
1b0: 000005cb .word 0x000005cb
1b4: 00000000 .word 0x00000000
1b8: e000ed00 .word 0xe000ed00
1bc: 410070fc .word 0x410070fc
1c0: 41005000 .word 0x41005000
1c4: 41004800 .word 0x41004800
1c8: 41004000 .word 0x41004000
1cc: 00000571 .word 0x00000571
1d0: 000003b5 .word 0x000003b5
000001d4 <_pm_init>:
}
static inline void hri_pm_set_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->CPUSEL.reg |= PM_CPUSEL_CPUDIV(mask);
1d4: 4b06 ldr r3, [pc, #24] ; (1f0 <_pm_init+0x1c>)
1d6: 7a1a ldrb r2, [r3, #8]
1d8: b2d2 uxtb r2, r2
1da: 721a strb r2, [r3, #8]
}
static inline void hri_pm_set_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->APBASEL.reg |= PM_APBASEL_APBADIV(mask);
1dc: 7a5a ldrb r2, [r3, #9]
1de: b2d2 uxtb r2, r2
1e0: 725a strb r2, [r3, #9]
}
static inline void hri_pm_set_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->APBBSEL.reg |= PM_APBBSEL_APBBDIV(mask);
1e2: 7a9a ldrb r2, [r3, #10]
1e4: b2d2 uxtb r2, r2
1e6: 729a strb r2, [r3, #10]
}
static inline void hri_pm_set_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask)
{
PM_CRITICAL_SECTION_ENTER();
((Pm *)hw)->APBCSEL.reg |= PM_APBCSEL_APBCDIV(mask);
1e8: 7ada ldrb r2, [r3, #11]
1ea: b2d2 uxtb r2, r2
1ec: 72da strb r2, [r3, #11]
{
hri_pm_set_CPUSEL_CPUDIV_bf(PM, CONF_CPU_DIV);
hri_pm_set_APBASEL_APBADIV_bf(PM, CONF_APBA_DIV);
hri_pm_set_APBBSEL_APBBDIV_bf(PM, CONF_APBB_DIV);
hri_pm_set_APBCSEL_APBCDIV_bf(PM, CONF_APBC_DIV);
}
1ee: 4770 bx lr
1f0: 40000400 .word 0x40000400
000001f4 <_init_chip>:
}
static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
{
NVMCTRL_CRITICAL_SECTION_ENTER();
((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask);
1f4: 4b06 ldr r3, [pc, #24] ; (210 <_init_chip+0x1c>)
/**
* \brief Initialize the hardware abstraction layer
*/
void _init_chip(void)
{
1f6: b510 push {r4, lr}
1f8: 685a ldr r2, [r3, #4]
1fa: 605a str r2, [r3, #4]
hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
_pm_init();
1fc: 4b05 ldr r3, [pc, #20] ; (214 <_init_chip+0x20>)
1fe: 4798 blx r3
_sysctrl_init_sources();
200: 4b05 ldr r3, [pc, #20] ; (218 <_init_chip+0x24>)
202: 4798 blx r3
#if _GCLK_INIT_1ST
_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
#endif
_sysctrl_init_referenced_generators();
204: 4b05 ldr r3, [pc, #20] ; (21c <_init_chip+0x28>)
206: 4798 blx r3
_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
208: 20ff movs r0, #255 ; 0xff
20a: 4b05 ldr r3, [pc, #20] ; (220 <_init_chip+0x2c>)
20c: 4798 blx r3
#if CONF_DMAC_ENABLE
_pm_enable_bus_clock(PM_BUS_AHB, DMAC);
_pm_enable_bus_clock(PM_BUS_APBB, DMAC);
_dma_init();
#endif
}
20e: bd10 pop {r4, pc}
210: 41004000 .word 0x41004000
214: 000001d5 .word 0x000001d5
218: 0000022d .word 0x0000022d
21c: 00000275 .word 0x00000275
220: 00000395 .word 0x00000395
00000224 <assert>:
/**
* \brief Assert function
*/
void assert(const bool condition, const char *const file, const int line)
{
if (!(condition)) {
224: 2800 cmp r0, #0
226: d100 bne.n 22a <assert+0x6>
__asm("BKPT #0");
228: be00 bkpt 0x0000
}
(void)file;
(void)line;
}
22a: 4770 bx lr
0000022c <_sysctrl_init_sources>:
}
static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_CALIB_bf(const void *const hw)
{
uint32_t tmp;
tmp = ((Sysctrl *)hw)->OSC8M.reg;
22c: 4b0e ldr r3, [pc, #56] ; (268 <_sysctrl_init_sources+0x3c>)
22e: 6a18 ldr r0, [r3, #32]
}
static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_FRANGE_bf(const void *const hw)
{
uint32_t tmp;
tmp = ((Sysctrl *)hw)->OSC8M.reg;
230: 6a19 ldr r1, [r3, #32]
#if CONF_OSC8M_CONFIG == 1
calib = hri_sysctrl_read_OSC8M_CALIB_bf(hw);
hri_sysctrl_write_OSC8M_reg(hw,
SYSCTRL_OSC8M_FRANGE(hri_sysctrl_read_OSC8M_FRANGE_bf(hw)) |
232: 0f89 lsrs r1, r1, #30
234: 078a lsls r2, r1, #30
#if CONF_OSC8M_OVERWRITE_CALIBRATION == 1
SYSCTRL_OSC8M_CALIB(CONF_OSC8M_CALIB) |
#else
SYSCTRL_OSC8M_CALIB(calib) |
236: 490d ldr r1, [pc, #52] ; (26c <_sysctrl_init_sources+0x40>)
238: 4001 ands r1, r0
SYSCTRL_OSC8M_FRANGE(hri_sysctrl_read_OSC8M_FRANGE_bf(hw)) |
23a: 430a orrs r2, r1
hri_sysctrl_write_OSC8M_reg(hw,
23c: 490c ldr r1, [pc, #48] ; (270 <_sysctrl_init_sources+0x44>)
23e: 430a orrs r2, r1
}
static inline void hri_sysctrl_write_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t data)
{
SYSCTRL_CRITICAL_SECTION_ENTER();
((Sysctrl *)hw)->OSC8M.reg = data;
240: 621a str r2, [r3, #32]
((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
242: 2202 movs r2, #2
244: 6999 ldr r1, [r3, #24]
246: 430a orrs r2, r1
tmp = (tmp & SYSCTRL_OSCULP32K_CALIB_Msk) >> SYSCTRL_OSCULP32K_CALIB_Pos;
248: 211f movs r1, #31
((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
24a: 619a str r2, [r3, #24]
tmp = ((Sysctrl *)hw)->OSCULP32K.reg;
24c: 7f1a ldrb r2, [r3, #28]
tmp = (tmp & SYSCTRL_OSCULP32K_CALIB_Msk) >> SYSCTRL_OSCULP32K_CALIB_Pos;
24e: 400a ands r2, r1
((Sysctrl *)hw)->OSCULP32K.reg = data;
250: 771a strb r2, [r3, #28]
return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY) >> SYSCTRL_PCLKSR_OSC8MRDY_Pos;
252: 391e subs r1, #30
254: 68da ldr r2, [r3, #12]
256: 08d2 lsrs r2, r2, #3
#endif
#endif
#if CONF_OSC8M_CONFIG == 1
#if CONF_OSC8M_ENABLE == 1
while (!hri_sysctrl_get_PCLKSR_OSC8MRDY_bit(hw))
258: 420a tst r2, r1
25a: d0fb beq.n 254 <_sysctrl_init_sources+0x28>
((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_ONDEMAND;
25c: 2280 movs r2, #128 ; 0x80
25e: 6a19 ldr r1, [r3, #32]
260: 430a orrs r2, r1
262: 621a str r2, [r3, #32]
hri_sysctrl_set_OSC8M_ONDEMAND_bit(hw);
#endif
#endif
(void)calib, (void)hw;
}
264: 4770 bx lr
266: 46c0 nop ; (mov r8, r8)
268: 40000800 .word 0x40000800
26c: 0fff0000 .word 0x0fff0000
270: 00000302 .word 0x00000302
00000274 <_sysctrl_init_referenced_generators>:
((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
274: 2102 movs r1, #2
276: 4a02 ldr r2, [pc, #8] ; (280 <_sysctrl_init_referenced_generators+0xc>)
278: 6993 ldr r3, [r2, #24]
27a: 438b bics r3, r1
27c: 6193 str r3, [r2, #24]
/* Disable after all possible configurations needs sync written. */
hri_sysctrl_clear_OSC32K_ENABLE_bit(hw);
#endif
(void)hw;
}
27e: 4770 bx lr
280: 40000800 .word 0x40000800
00000284 <usart_sync_write>:
* \param[in] length The number of bytes to write
*
* \return The number of bytes written.
*/
static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
{
284: b5f8 push {r3, r4, r5, r6, r7, lr}
286: 0006 movs r6, r0
288: 000d movs r5, r1
28a: 0014 movs r4, r2
uint32_t offset = 0;
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
ASSERT(io_descr && buf && length);
28c: 2800 cmp r0, #0
28e: d004 beq.n 29a <usart_sync_write+0x16>
290: 1e08 subs r0, r1, #0
292: d002 beq.n 29a <usart_sync_write+0x16>
294: 0010 movs r0, r2
296: 1e43 subs r3, r0, #1
298: 4198 sbcs r0, r3
29a: 22f1 movs r2, #241 ; 0xf1
29c: 4910 ldr r1, [pc, #64] ; (2e0 <usart_sync_write+0x5c>)
29e: 4b11 ldr r3, [pc, #68] ; (2e4 <usart_sync_write+0x60>)
2a0: 4798 blx r3
while (!_usart_sync_is_ready_to_send(&descr->device))
2a2: 0037 movs r7, r6
2a4: 3708 adds r7, #8
2a6: 0038 movs r0, r7
2a8: 4b0f ldr r3, [pc, #60] ; (2e8 <usart_sync_write+0x64>)
2aa: 4798 blx r3
2ac: 2800 cmp r0, #0
2ae: d0f8 beq.n 2a2 <usart_sync_write+0x1e>
uint32_t offset = 0;
2b0: 2600 movs r6, #0
;
do {
_usart_sync_write_byte(&descr->device, buf[offset]);
2b2: 0038 movs r0, r7
2b4: 5da9 ldrb r1, [r5, r6]
2b6: 4b0d ldr r3, [pc, #52] ; (2ec <usart_sync_write+0x68>)
2b8: 4798 blx r3
while (!_usart_sync_is_ready_to_send(&descr->device))
2ba: 0038 movs r0, r7
2bc: 4b0a ldr r3, [pc, #40] ; (2e8 <usart_sync_write+0x64>)
2be: 4798 blx r3
2c0: 2800 cmp r0, #0
2c2: d0fa beq.n 2ba <usart_sync_write+0x36>
;
} while (++offset < length);
2c4: 3601 adds r6, #1
2c6: 42b4 cmp r4, r6
2c8: d8f3 bhi.n 2b2 <usart_sync_write+0x2e>
2ca: 2501 movs r5, #1
2cc: 2c00 cmp r4, #0
2ce: d000 beq.n 2d2 <usart_sync_write+0x4e>
2d0: 0025 movs r5, r4
while (!_usart_sync_is_transmit_done(&descr->device))
2d2: 0038 movs r0, r7
2d4: 4b06 ldr r3, [pc, #24] ; (2f0 <usart_sync_write+0x6c>)
2d6: 4798 blx r3
2d8: 2800 cmp r0, #0
2da: d0fa beq.n 2d2 <usart_sync_write+0x4e>
;
return (int32_t)offset;
}
2dc: 0028 movs r0, r5
2de: bdf8 pop {r3, r4, r5, r6, r7, pc}
2e0: 000005da .word 0x000005da
2e4: 00000225 .word 0x00000225
2e8: 00000547 .word 0x00000547
2ec: 00000539 .word 0x00000539
2f0: 00000551 .word 0x00000551
000002f4 <usart_sync_read>:
* \param[in] length The size of a buffer
*
* \return The number of bytes read.
*/
static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
{
2f4: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
2f6: 0005 movs r5, r0
2f8: 0014 movs r4, r2
2fa: 9101 str r1, [sp, #4]
uint32_t offset = 0;
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
ASSERT(io_descr && buf && length);
2fc: 2800 cmp r0, #0
2fe: d004 beq.n 30a <usart_sync_read+0x16>
300: 1e08 subs r0, r1, #0
302: d002 beq.n 30a <usart_sync_read+0x16>
304: 0010 movs r0, r2
306: 1e43 subs r3, r0, #1
308: 4198 sbcs r0, r3
30a: 2286 movs r2, #134 ; 0x86
30c: 490c ldr r1, [pc, #48] ; (340 <usart_sync_read+0x4c>)
30e: 4b0d ldr r3, [pc, #52] ; (344 <usart_sync_read+0x50>)
310: 0052 lsls r2, r2, #1
312: 4798 blx r3
uint32_t offset = 0;
314: 2600 movs r6, #0
do {
while (!_usart_sync_is_byte_received(&descr->device))
316: 002f movs r7, r5
318: 3708 adds r7, #8
31a: 0038 movs r0, r7
31c: 4b0a ldr r3, [pc, #40] ; (348 <usart_sync_read+0x54>)
31e: 4798 blx r3
320: 2800 cmp r0, #0
322: d0f8 beq.n 316 <usart_sync_read+0x22>
;
buf[offset] = _usart_sync_read_byte(&descr->device);
324: 4b09 ldr r3, [pc, #36] ; (34c <usart_sync_read+0x58>)
326: 0038 movs r0, r7
328: 4798 blx r3
32a: 9b01 ldr r3, [sp, #4]
32c: 5598 strb r0, [r3, r6]
} while (++offset < length);
32e: 3601 adds r6, #1
330: 42b4 cmp r4, r6
332: d8f0 bhi.n 316 <usart_sync_read+0x22>
334: 2001 movs r0, #1
336: 2c00 cmp r4, #0
338: d000 beq.n 33c <usart_sync_read+0x48>
33a: 0020 movs r0, r4
return (int32_t)offset;
}
33c: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
33e: 46c0 nop ; (mov r8, r8)
340: 000005da .word 0x000005da
344: 00000225 .word 0x00000225
348: 0000055b .word 0x0000055b
34c: 0000053f .word 0x0000053f
00000350 <usart_sync_init>:
{
350: b570 push {r4, r5, r6, lr}
352: 0004 movs r4, r0
354: 000d movs r5, r1
ASSERT(descr && hw);
356: 2800 cmp r0, #0
358: d002 beq.n 360 <usart_sync_init+0x10>
35a: 0008 movs r0, r1
35c: 1e43 subs r3, r0, #1
35e: 4198 sbcs r0, r3
360: 4907 ldr r1, [pc, #28] ; (380 <usart_sync_init+0x30>)
362: 4b08 ldr r3, [pc, #32] ; (384 <usart_sync_init+0x34>)
364: 2234 movs r2, #52 ; 0x34
366: 4798 blx r3
init_status = _usart_sync_init(&descr->device, hw);
368: 0020 movs r0, r4
36a: 0029 movs r1, r5
36c: 4b06 ldr r3, [pc, #24] ; (388 <usart_sync_init+0x38>)
36e: 3008 adds r0, #8
370: 4798 blx r3
if (init_status) {
372: 2800 cmp r0, #0
374: d103 bne.n 37e <usart_sync_init+0x2e>
descr->io.read = usart_sync_read;
376: 4b05 ldr r3, [pc, #20] ; (38c <usart_sync_init+0x3c>)
378: 6063 str r3, [r4, #4]
descr->io.write = usart_sync_write;
37a: 4b05 ldr r3, [pc, #20] ; (390 <usart_sync_init+0x40>)
37c: 6023 str r3, [r4, #0]
}
37e: bd70 pop {r4, r5, r6, pc}
380: 000005da .word 0x000005da
384: 00000225 .word 0x00000225
388: 0000050d .word 0x0000050d
38c: 000002f5 .word 0x000002f5
390: 00000285 .word 0x00000285
00000394 <_gclk_init_generators_by_fref>:
void _gclk_init_generators_by_fref(uint32_t bm)
{
#if CONF_GCLK_GENERATOR_0_CONFIG == 1
if (bm & (1ul << 0)) {
394: 07c3 lsls r3, r0, #31
396: d509 bpl.n 3ac <_gclk_init_generators_by_fref+0x18>
}
static inline void hri_gclk_write_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t data)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENDIV.reg = data;
398: 2380 movs r3, #128 ; 0x80
39a: 4a05 ldr r2, [pc, #20] ; (3b0 <_gclk_init_generators_by_fref+0x1c>)
39c: 005b lsls r3, r3, #1
39e: 6093 str r3, [r2, #8]
((Gclk *)hw)->GENCTRL.reg = data;
3a0: 2383 movs r3, #131 ; 0x83
3a2: 025b lsls r3, r3, #9
3a4: 6053 str r3, [r2, #4]
while (((const Gclk *)hw)->STATUS.bit.SYNCBUSY)
3a6: 7853 ldrb r3, [r2, #1]
3a8: 09db lsrs r3, r3, #7
3aa: d1fc bne.n 3a6 <_gclk_init_generators_by_fref+0x12>
| (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SRC | GCLK_GENCTRL_ID(8));
}
#endif
}
3ac: 4770 bx lr
3ae: 46c0 nop ; (mov r8, r8)
3b0: 40000c00 .word 0x40000c00
000003b4 <main>:
#include <atmel_start.h>
int main(void)
{
3b4: b510 push {r4, lr}
/* Initializes MCU, drivers and middleware */
atmel_start_init();
3b6: 4b01 ldr r3, [pc, #4] ; (3bc <main+0x8>)
3b8: 4798 blx r3
/* Replace with your application code */
while (1) {
3ba: e7fe b.n 3ba <main+0x6>
3bc: 00000565 .word 0x00000565
000003c0 <USART_0_PORT_init>:
static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
bool value)
{
uint8_t tmp;
PORT_CRITICAL_SECTION_ENTER();
tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
3c0: 4b0d ldr r3, [pc, #52] ; (3f8 <USART_0_PORT_init+0x38>)
tmp &= ~PORT_PINCFG_PMUXEN;
3c2: 2201 movs r2, #1
tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
3c4: 0018 movs r0, r3
#include <hpl_pm_base.h>
struct usart_sync_descriptor USART_0;
void USART_0_PORT_init(void)
{
3c6: b530 push {r4, r5, lr}
3c8: 3044 adds r0, #68 ; 0x44
3ca: 7801 ldrb r1, [r0, #0]
tmp &= ~PORT_PMUX_PMUXE_Msk;
3cc: 240f movs r4, #15
tmp &= ~PORT_PINCFG_PMUXEN;
3ce: 4391 bics r1, r2
tmp |= value << PORT_PINCFG_PMUXEN_Pos;
3d0: 4311 orrs r1, r2
((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
3d2: 7001 strb r1, [r0, #0]
tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
3d4: 0019 movs r1, r3
tmp |= PORT_PMUX_PMUXE(data);
3d6: 2003 movs r0, #3
tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
3d8: 3132 adds r1, #50 ; 0x32
3da: 780d ldrb r5, [r1, #0]
tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
3dc: 3345 adds r3, #69 ; 0x45
tmp &= ~PORT_PMUX_PMUXE_Msk;
3de: 43a5 bics r5, r4
tmp |= PORT_PMUX_PMUXE(data);
3e0: 4328 orrs r0, r5
((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
3e2: 7008 strb r0, [r1, #0]
tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
3e4: 7818 ldrb r0, [r3, #0]
tmp &= ~PORT_PINCFG_PMUXEN;
3e6: 4390 bics r0, r2
tmp |= value << PORT_PINCFG_PMUXEN_Pos;
3e8: 4302 orrs r2, r0
((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
3ea: 701a strb r2, [r3, #0]
tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
3ec: 780b ldrb r3, [r1, #0]
tmp &= ~PORT_PMUX_PMUXO_Msk;
3ee: 401c ands r4, r3
tmp |= PORT_PMUX_PMUXO(data);
3f0: 2330 movs r3, #48 ; 0x30
3f2: 4323 orrs r3, r4
((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
3f4: 700b strb r3, [r1, #0]
gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0);
gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1);
}
3f6: bd30 pop {r4, r5, pc}
3f8: 41004400 .word 0x41004400
000003fc <USART_0_CLOCK_init>:
peripheral = (uint32_t)_pm_get_apbb_index(module);
PM->APBBMASK.reg |= 1 << peripheral;
}
break;
case PM_BUS_APBC:
PM->APBCMASK.reg |= 1 << peripheral;
3fc: 2304 movs r3, #4
3fe: 4a04 ldr r2, [pc, #16] ; (410 <USART_0_CLOCK_init+0x14>)
400: 6a11 ldr r1, [r2, #32]
402: 430b orrs r3, r1
404: 6213 str r3, [r2, #32]
((Gclk *)hw)->CLKCTRL.reg = data;
406: 4b03 ldr r3, [pc, #12] ; (414 <USART_0_CLOCK_init+0x18>)
408: 4a03 ldr r2, [pc, #12] ; (418 <USART_0_CLOCK_init+0x1c>)
40a: 805a strh r2, [r3, #2]
void USART_0_CLOCK_init(void)
{
_pm_enable_bus_clock(PM_BUS_APBC, SERCOM0);
_gclk_enable_channel(SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC);
}
40c: 4770 bx lr
40e: 46c0 nop ; (mov r8, r8)
410: 40000400 .word 0x40000400
414: 40000c00 .word 0x40000c00
418: 00004014 .word 0x00004014
0000041c <USART_0_init>:
void USART_0_init(void)
{
41c: b510 push {r4, lr}
USART_0_CLOCK_init();
41e: 4b05 ldr r3, [pc, #20] ; (434 <USART_0_init+0x18>)
420: 4798 blx r3
usart_sync_init(&USART_0, SERCOM0, (void *)NULL);
422: 2200 movs r2, #0
424: 4904 ldr r1, [pc, #16] ; (438 <USART_0_init+0x1c>)
426: 4b05 ldr r3, [pc, #20] ; (43c <USART_0_init+0x20>)
428: 4805 ldr r0, [pc, #20] ; (440 <USART_0_init+0x24>)
42a: 4798 blx r3
USART_0_PORT_init();
42c: 4b05 ldr r3, [pc, #20] ; (444 <USART_0_init+0x28>)
42e: 4798 blx r3
}
430: bd10 pop {r4, pc}
432: 46c0 nop ; (mov r8, r8)
434: 000003fd .word 0x000003fd
438: 42000800 .word 0x42000800
43c: 00000351 .word 0x00000351
440: 2000001c .word 0x2000001c
444: 000003c1 .word 0x000003c1
00000448 <system_init>:
void system_init(void)
{
448: b510 push {r4, lr}
* Currently the following initialization functions are supported:
* - System clock initialization
*/
static inline void init_mcu(void)
{
_init_chip();
44a: 4b02 ldr r3, [pc, #8] ; (454 <system_init+0xc>)
44c: 4798 blx r3
init_mcu();
USART_0_init();
44e: 4b02 ldr r3, [pc, #8] ; (458 <system_init+0x10>)
450: 4798 blx r3
}
452: bd10 pop {r4, pc}
454: 000001f5 .word 0x000001f5
458: 0000041d .word 0x0000041d
0000045c <hri_sercomusart_wait_for_sync>:
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
}
static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
{
while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) {
45c: 69c3 ldr r3, [r0, #28]
45e: 4219 tst r1, r3
460: d1fc bne.n 45c <hri_sercomusart_wait_for_sync>
};
}
462: 4770 bx lr
00000464 <hri_sercomusart_clear_CTRLA_ENABLE_bit>:
}
static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
464: 2202 movs r2, #2
{
466: b510 push {r4, lr}
((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
468: 6803 ldr r3, [r0, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
46a: 2103 movs r1, #3
((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
46c: 4393 bics r3, r2
46e: 6003 str r3, [r0, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
470: 4b01 ldr r3, [pc, #4] ; (478 <hri_sercomusart_clear_CTRLA_ENABLE_bit+0x14>)
472: 4798 blx r3
SERCOM_CRITICAL_SECTION_LEAVE();
}
474: bd10 pop {r4, pc}
476: 46c0 nop ; (mov r8, r8)
478: 0000045d .word 0x0000045d
0000047c <_usart_init>:
{
#ifdef _UNIT_TEST_
return ((uint32_t)hw - (uint32_t)SERCOM0) / sizeof(Sercom);
#endif
return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10;
47c: 4b1b ldr r3, [pc, #108] ; (4ec <_usart_init+0x70>)
* \param[in] hw The pointer to hardware instance
*
* \return The status of initialization
*/
static int32_t _usart_init(void *const hw)
{
47e: b570 push {r4, r5, r6, lr}
return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10;
480: 18c3 adds r3, r0, r3
482: 0a9b lsrs r3, r3, #10
if (_usarts[i].number == sercom_offset) {
484: b2db uxtb r3, r3
{
486: 0004 movs r4, r0
if (_usarts[i].number == sercom_offset) {
488: 2b00 cmp r3, #0
48a: d004 beq.n 496 <_usart_init+0x1a>
ASSERT(false);
48c: 2000 movs r0, #0
48e: 4a18 ldr r2, [pc, #96] ; (4f0 <_usart_init+0x74>)
490: 4918 ldr r1, [pc, #96] ; (4f4 <_usart_init+0x78>)
492: 4b19 ldr r3, [pc, #100] ; (4f8 <_usart_init+0x7c>)
494: 4798 blx r3
return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
496: 69e3 ldr r3, [r4, #28]
498: 4d18 ldr r5, [pc, #96] ; (4fc <_usart_init+0x80>)
uint8_t i = _get_sercom_index(hw);
if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) {
49a: 07db lsls r3, r3, #31
49c: d411 bmi.n 4c2 <_usart_init+0x46>
hri_sercomusart_ctrla_reg_t mask)
{
uint32_t tmp;
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
tmp = ((Sercom *)hw)->USART.CTRLA.reg;
tmp &= mask;
49e: 2602 movs r6, #2
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
4a0: 2103 movs r1, #3
4a2: 0020 movs r0, r4
4a4: 47a8 blx r5
tmp = ((Sercom *)hw)->USART.CTRLA.reg;
4a6: 6823 ldr r3, [r4, #0]
uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk;
if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) {
4a8: 4233 tst r3, r6
4aa: d005 beq.n 4b8 <_usart_init+0x3c>
hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
4ac: 0020 movs r0, r4
4ae: 4b14 ldr r3, [pc, #80] ; (500 <_usart_init+0x84>)
4b0: 4798 blx r3
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
4b2: 0031 movs r1, r6
4b4: 0020 movs r0, r4
4b6: 47a8 blx r5
}
static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLA.reg = data;
4b8: 2305 movs r3, #5
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
4ba: 2103 movs r1, #3
4bc: 0020 movs r0, r4
((Sercom *)hw)->USART.CTRLA.reg = data;
4be: 6023 str r3, [r4, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
4c0: 47a8 blx r5
}
hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode);
}
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
4c2: 0020 movs r0, r4
4c4: 2101 movs r1, #1
4c6: 47a8 blx r5
((Sercom *)hw)->USART.CTRLA.reg = data;
4c8: 4b0e ldr r3, [pc, #56] ; (504 <_usart_init+0x88>)
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
4ca: 0020 movs r0, r4
((Sercom *)hw)->USART.CTRLA.reg = data;
4cc: 6023 str r3, [r4, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
4ce: 2103 movs r1, #3
4d0: 47a8 blx r5
}
static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLB.reg = data;
4d2: 23c0 movs r3, #192 ; 0xc0
4d4: 029b lsls r3, r3, #10
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4d6: 0020 movs r0, r4
((Sercom *)hw)->USART.CTRLB.reg = data;
4d8: 6063 str r3, [r4, #4]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
4da: 2107 movs r1, #7
4dc: 47a8 blx r5
}
static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.RXPL.reg = data;
4de: 2000 movs r0, #0
((Sercom *)hw)->USART.BAUD.reg = data;
4e0: 4b09 ldr r3, [pc, #36] ; (508 <_usart_init+0x8c>)
4e2: 81a3 strh r3, [r4, #12]
((Sercom *)hw)->USART.RXPL.reg = data;
4e4: 73a0 strb r0, [r4, #14]
}
static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.DBGCTRL.reg = data;
4e6: 3430 adds r4, #48 ; 0x30
4e8: 7020 strb r0, [r4, #0]
hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl);
hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl);
return ERR_NONE;
}
4ea: bd70 pop {r4, r5, r6, pc}
4ec: bdfff800 .word 0xbdfff800
4f0: 0000023a .word 0x0000023a
4f4: 000005f6 .word 0x000005f6
4f8: 00000225 .word 0x00000225
4fc: 0000045d .word 0x0000045d
500: 00000465 .word 0x00000465
504: 40100004 .word 0x40100004
508: ffffd8ad .word 0xffffd8ad
0000050c <_usart_sync_init>:
{
50c: b570 push {r4, r5, r6, lr}
50e: 0005 movs r5, r0
ASSERT(device);
510: 1e43 subs r3, r0, #1
512: 4198 sbcs r0, r3
{
514: 000c movs r4, r1
ASSERT(device);
516: 22b4 movs r2, #180 ; 0xb4
518: 4904 ldr r1, [pc, #16] ; (52c <_usart_sync_init+0x20>)
51a: 4b05 ldr r3, [pc, #20] ; (530 <_usart_sync_init+0x24>)
51c: b2c0 uxtb r0, r0
51e: 4798 blx r3
device->hw = hw;
520: 602c str r4, [r5, #0]
return _usart_init(hw);
522: 0020 movs r0, r4
524: 4b03 ldr r3, [pc, #12] ; (534 <_usart_sync_init+0x28>)
526: 4798 blx r3
}
528: bd70 pop {r4, r5, r6, pc}
52a: 46c0 nop ; (mov r8, r8)
52c: 000005f6 .word 0x000005f6
530: 00000225 .word 0x00000225
534: 0000047d .word 0x0000047d
00000538 <_usart_sync_write_byte>:
hri_sercomusart_write_DATA_reg(device->hw, data);
538: 6803 ldr r3, [r0, #0]
((Sercom *)hw)->USART.DATA.reg = data;
53a: 8519 strh r1, [r3, #40] ; 0x28
}
53c: 4770 bx lr
0000053e <_usart_sync_read_byte>:
return hri_sercomusart_read_DATA_reg(device->hw);
53e: 6803 ldr r3, [r0, #0]
return ((Sercom *)hw)->USART.DATA.reg;
540: 8d18 ldrh r0, [r3, #40] ; 0x28
542: b2c0 uxtb r0, r0
}
544: 4770 bx lr
00000546 <_usart_sync_is_ready_to_send>:
return hri_sercomusart_get_interrupt_DRE_bit(device->hw);
546: 6803 ldr r3, [r0, #0]
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
548: 7e18 ldrb r0, [r3, #24]
54a: 2301 movs r3, #1
54c: 4018 ands r0, r3
}
54e: 4770 bx lr
00000550 <_usart_sync_is_transmit_done>:
return hri_sercomusart_get_interrupt_TXC_bit(device->hw);
550: 6803 ldr r3, [r0, #0]
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
552: 7e18 ldrb r0, [r3, #24]
554: 0780 lsls r0, r0, #30
556: 0fc0 lsrs r0, r0, #31
}
558: 4770 bx lr
0000055a <_usart_sync_is_byte_received>:
return hri_sercomusart_get_interrupt_RXC_bit(device->hw);
55a: 6803 ldr r3, [r0, #0]
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
55c: 7e18 ldrb r0, [r3, #24]
55e: 0740 lsls r0, r0, #29
560: 0fc0 lsrs r0, r0, #31
}
562: 4770 bx lr
00000564 <atmel_start_init>:
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
564: b510 push {r4, lr}
system_init();
566: 4b01 ldr r3, [pc, #4] ; (56c <atmel_start_init+0x8>)
568: 4798 blx r3
}
56a: bd10 pop {r4, pc}
56c: 00000449 .word 0x00000449
00000570 <__libc_init_array>:
570: b570 push {r4, r5, r6, lr}
572: 2600 movs r6, #0
574: 4d0c ldr r5, [pc, #48] ; (5a8 <__libc_init_array+0x38>)
576: 4c0d ldr r4, [pc, #52] ; (5ac <__libc_init_array+0x3c>)
578: 1b64 subs r4, r4, r5
57a: 10a4 asrs r4, r4, #2
57c: 42a6 cmp r6, r4
57e: d109 bne.n 594 <__libc_init_array+0x24>
580: 2600 movs r6, #0
582: f000 f847 bl 614 <_init>
586: 4d0a ldr r5, [pc, #40] ; (5b0 <__libc_init_array+0x40>)
588: 4c0a ldr r4, [pc, #40] ; (5b4 <__libc_init_array+0x44>)
58a: 1b64 subs r4, r4, r5
58c: 10a4 asrs r4, r4, #2
58e: 42a6 cmp r6, r4
590: d105 bne.n 59e <__libc_init_array+0x2e>
592: bd70 pop {r4, r5, r6, pc}
594: 00b3 lsls r3, r6, #2
596: 58eb ldr r3, [r5, r3]
598: 4798 blx r3
59a: 3601 adds r6, #1
59c: e7ee b.n 57c <__libc_init_array+0xc>
59e: 00b3 lsls r3, r6, #2
5a0: 58eb ldr r3, [r5, r3]
5a2: 4798 blx r3
5a4: 3601 adds r6, #1
5a6: e7f2 b.n 58e <__libc_init_array+0x1e>
5a8: 00000620 .word 0x00000620
5ac: 00000620 .word 0x00000620
5b0: 00000620 .word 0x00000620
5b4: 00000624 .word 0x00000624
000005b8 <memcpy>:
5b8: 2300 movs r3, #0
5ba: b510 push {r4, lr}
5bc: 429a cmp r2, r3
5be: d100 bne.n 5c2 <memcpy+0xa>
5c0: bd10 pop {r4, pc}
5c2: 5ccc ldrb r4, [r1, r3]
5c4: 54c4 strb r4, [r0, r3]
5c6: 3301 adds r3, #1
5c8: e7f8 b.n 5bc <memcpy+0x4>
000005ca <memset>:
5ca: 0003 movs r3, r0
5cc: 1882 adds r2, r0, r2
5ce: 4293 cmp r3, r2
5d0: d100 bne.n 5d4 <memset+0xa>
5d2: 4770 bx lr
5d4: 7019 strb r1, [r3, #0]
5d6: 3301 adds r3, #1
5d8: e7f9 b.n 5ce <memset+0x4>
5da: 2e2e .short 0x2e2e
5dc: 6c61682f .word 0x6c61682f
5e0: 6372732f .word 0x6372732f
5e4: 6c61682f .word 0x6c61682f
5e8: 6173755f .word 0x6173755f
5ec: 735f7472 .word 0x735f7472
5f0: 2e636e79 .word 0x2e636e79
5f4: 0063 .short 0x0063
5f6: 2e2e .short 0x2e2e
5f8: 6c70682f .word 0x6c70682f
5fc: 7265732f .word 0x7265732f
600: 2f6d6f63 .word 0x2f6d6f63
604: 5f6c7068 .word 0x5f6c7068
608: 63726573 .word 0x63726573
60c: 632e6d6f .word 0x632e6d6f
610: 00000000 .word 0x00000000
00000614 <_init>:
614: b5f8 push {r3, r4, r5, r6, r7, lr}
616: 46c0 nop ; (mov r8, r8)
618: bcf8 pop {r3, r4, r5, r6, r7}
61a: bc08 pop {r3}
61c: 469e mov lr, r3
61e: 4770 bx lr
00000620 <__frame_dummy_init_array_entry>:
620: 00dd 0000 ....
00000624 <_fini>:
624: b5f8 push {r3, r4, r5, r6, r7, lr}
626: 46c0 nop ; (mov r8, r8)
628: bcf8 pop {r3, r4, r5, r6, r7}
62a: bc08 pop {r3}
62c: 469e mov lr, r3
62e: 4770 bx lr
00000630 <__do_global_dtors_aux_fini_array_entry>:
630: 00b5 0000 ....
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