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1016 lines
30 KiB
C
1016 lines
30 KiB
C
/**
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* \file
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*
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* \brief SAM NVMCTRL
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*
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* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAMD21_NVMCTRL_COMPONENT_
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#ifndef _HRI_NVMCTRL_D21_H_INCLUDED_
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#define _HRI_NVMCTRL_D21_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS)
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#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define NVMCTRL_CRITICAL_SECTION_ENTER()
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#define NVMCTRL_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint16_t hri_nvmctrl_ctrla_reg_t;
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typedef uint16_t hri_nvmctrl_lock_reg_t;
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typedef uint16_t hri_nvmctrl_status_reg_t;
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typedef uint32_t hri_nvmctrl_addr_reg_t;
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typedef uint32_t hri_nvmctrl_ctrlb_reg_t;
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typedef uint32_t hri_nvmctrl_param_reg_t;
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typedef uint8_t hri_nvmctrl_intenset_reg_t;
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typedef uint8_t hri_nvmctrl_intflag_reg_t;
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static inline bool hri_nvmctrl_get_INTFLAG_READY_bit(const void *const hw)
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{
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return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos;
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}
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static inline void hri_nvmctrl_clear_INTFLAG_READY_bit(const void *const hw)
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{
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((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY;
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}
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static inline bool hri_nvmctrl_get_INTFLAG_ERROR_bit(const void *const hw)
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{
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return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos;
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}
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static inline void hri_nvmctrl_clear_INTFLAG_ERROR_bit(const void *const hw)
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{
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((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR;
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}
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static inline bool hri_nvmctrl_get_interrupt_READY_bit(const void *const hw)
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{
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return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos;
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}
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static inline void hri_nvmctrl_clear_interrupt_READY_bit(const void *const hw)
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{
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((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY;
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}
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static inline bool hri_nvmctrl_get_interrupt_ERROR_bit(const void *const hw)
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{
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return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos;
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}
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static inline void hri_nvmctrl_clear_interrupt_ERROR_bit(const void *const hw)
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{
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((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR;
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}
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static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw,
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hri_nvmctrl_intflag_reg_t mask)
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{
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uint8_t tmp;
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tmp = ((Nvmctrl *)hw)->INTFLAG.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw)
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{
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return ((Nvmctrl *)hw)->INTFLAG.reg;
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}
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static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask)
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{
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((Nvmctrl *)hw)->INTFLAG.reg = mask;
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}
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static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw)
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{
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((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY;
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}
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static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw)
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{
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return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos;
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}
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static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value)
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{
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if (value == 0x0) {
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((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY;
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} else {
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((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY;
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}
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}
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static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw)
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{
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((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY;
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}
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static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw)
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{
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((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR;
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}
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static inline bool hri_nvmctrl_get_INTEN_ERROR_bit(const void *const hw)
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{
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return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos;
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}
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static inline void hri_nvmctrl_write_INTEN_ERROR_bit(const void *const hw, bool value)
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{
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if (value == 0x0) {
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((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR;
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} else {
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((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR;
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}
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}
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static inline void hri_nvmctrl_clear_INTEN_ERROR_bit(const void *const hw)
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{
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((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR;
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}
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static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
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{
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((Nvmctrl *)hw)->INTENSET.reg = mask;
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}
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static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw,
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hri_nvmctrl_intenset_reg_t mask)
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{
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uint8_t tmp;
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tmp = ((Nvmctrl *)hw)->INTENSET.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw)
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{
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return ((Nvmctrl *)hw)->INTENSET.reg;
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}
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static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data)
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{
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((Nvmctrl *)hw)->INTENSET.reg = data;
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((Nvmctrl *)hw)->INTENCLR.reg = ~data;
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}
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static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask)
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{
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((Nvmctrl *)hw)->INTENCLR.reg = mask;
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}
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static inline void hri_nvmctrl_set_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask);
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
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{
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uint16_t tmp;
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tmp = ((Nvmctrl *)hw)->CTRLA.reg;
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tmp = (tmp & NVMCTRL_CTRLA_CMD(mask)) >> NVMCTRL_CTRLA_CMD_Pos;
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return tmp;
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}
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static inline void hri_nvmctrl_write_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
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{
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uint16_t tmp;
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NVMCTRL_CRITICAL_SECTION_ENTER();
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tmp = ((Nvmctrl *)hw)->CTRLA.reg;
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tmp &= ~NVMCTRL_CTRLA_CMD_Msk;
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tmp |= NVMCTRL_CTRLA_CMD(data);
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((Nvmctrl *)hw)->CTRLA.reg = tmp;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_clear_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask);
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_toggle_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask);
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMD_bf(const void *const hw)
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{
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uint16_t tmp;
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tmp = ((Nvmctrl *)hw)->CTRLA.reg;
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tmp = (tmp & NVMCTRL_CTRLA_CMD_Msk) >> NVMCTRL_CTRLA_CMD_Pos;
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return tmp;
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}
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static inline void hri_nvmctrl_set_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask);
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
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{
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uint16_t tmp;
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tmp = ((Nvmctrl *)hw)->CTRLA.reg;
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tmp = (tmp & NVMCTRL_CTRLA_CMDEX(mask)) >> NVMCTRL_CTRLA_CMDEX_Pos;
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return tmp;
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}
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static inline void hri_nvmctrl_write_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
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{
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uint16_t tmp;
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NVMCTRL_CRITICAL_SECTION_ENTER();
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tmp = ((Nvmctrl *)hw)->CTRLA.reg;
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tmp &= ~NVMCTRL_CTRLA_CMDEX_Msk;
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tmp |= NVMCTRL_CTRLA_CMDEX(data);
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((Nvmctrl *)hw)->CTRLA.reg = tmp;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_clear_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMDEX(mask);
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_toggle_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMDEX(mask);
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMDEX_bf(const void *const hw)
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{
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uint16_t tmp;
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tmp = ((Nvmctrl *)hw)->CTRLA.reg;
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tmp = (tmp & NVMCTRL_CTRLA_CMDEX_Msk) >> NVMCTRL_CTRLA_CMDEX_Pos;
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return tmp;
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}
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static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLA.reg |= mask;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
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{
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uint16_t tmp;
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tmp = ((Nvmctrl *)hw)->CTRLA.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLA.reg = data;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLA.reg &= ~mask;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLA.reg ^= mask;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw)
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{
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return ((Nvmctrl *)hw)->CTRLA.reg;
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}
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static inline void hri_nvmctrl_set_CTRLB_MANW_bit(const void *const hw)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_nvmctrl_get_CTRLB_MANW_bit(const void *const hw)
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{
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uint32_t tmp;
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tmp = ((Nvmctrl *)hw)->CTRLB.reg;
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tmp = (tmp & NVMCTRL_CTRLB_MANW) >> NVMCTRL_CTRLB_MANW_Pos;
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return (bool)tmp;
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}
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static inline void hri_nvmctrl_write_CTRLB_MANW_bit(const void *const hw, bool value)
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{
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uint32_t tmp;
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NVMCTRL_CRITICAL_SECTION_ENTER();
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tmp = ((Nvmctrl *)hw)->CTRLB.reg;
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tmp &= ~NVMCTRL_CTRLB_MANW;
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tmp |= value << NVMCTRL_CTRLB_MANW_Pos;
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((Nvmctrl *)hw)->CTRLB.reg = tmp;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_clear_CTRLB_MANW_bit(const void *const hw)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_toggle_CTRLB_MANW_bit(const void *const hw)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_set_CTRLB_CACHEDIS_bit(const void *const hw)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_nvmctrl_get_CTRLB_CACHEDIS_bit(const void *const hw)
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{
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uint32_t tmp;
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tmp = ((Nvmctrl *)hw)->CTRLB.reg;
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tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS) >> NVMCTRL_CTRLB_CACHEDIS_Pos;
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return (bool)tmp;
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}
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static inline void hri_nvmctrl_write_CTRLB_CACHEDIS_bit(const void *const hw, bool value)
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{
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uint32_t tmp;
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NVMCTRL_CRITICAL_SECTION_ENTER();
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tmp = ((Nvmctrl *)hw)->CTRLB.reg;
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tmp &= ~NVMCTRL_CTRLB_CACHEDIS;
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tmp |= value << NVMCTRL_CTRLB_CACHEDIS_Pos;
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((Nvmctrl *)hw)->CTRLB.reg = tmp;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_clear_CTRLB_CACHEDIS_bit(const void *const hw)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_CACHEDIS;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_toggle_CTRLB_CACHEDIS_bit(const void *const hw)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_CACHEDIS;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask);
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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|
|
static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->CTRLB.reg;
|
|
tmp = (tmp & NVMCTRL_CTRLB_RWS(mask)) >> NVMCTRL_CTRLB_RWS_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_write_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Nvmctrl *)hw)->CTRLB.reg;
|
|
tmp &= ~NVMCTRL_CTRLB_RWS_Msk;
|
|
tmp |= NVMCTRL_CTRLB_RWS(data);
|
|
((Nvmctrl *)hw)->CTRLB.reg = tmp;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_RWS(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_toggle_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_RWS(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_RWS_bf(const void *const hw)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->CTRLB.reg;
|
|
tmp = (tmp & NVMCTRL_CTRLB_RWS_Msk) >> NVMCTRL_CTRLB_RWS_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_set_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_SLEEPPRM(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_SLEEPPRM_bf(const void *const hw,
|
|
hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->CTRLB.reg;
|
|
tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM(mask)) >> NVMCTRL_CTRLB_SLEEPPRM_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_write_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Nvmctrl *)hw)->CTRLB.reg;
|
|
tmp &= ~NVMCTRL_CTRLB_SLEEPPRM_Msk;
|
|
tmp |= NVMCTRL_CTRLB_SLEEPPRM(data);
|
|
((Nvmctrl *)hw)->CTRLB.reg = tmp;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_SLEEPPRM(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_toggle_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_SLEEPPRM(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_SLEEPPRM_bf(const void *const hw)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->CTRLB.reg;
|
|
tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM_Msk) >> NVMCTRL_CTRLB_SLEEPPRM_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_set_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_READMODE(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_READMODE_bf(const void *const hw,
|
|
hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->CTRLB.reg;
|
|
tmp = (tmp & NVMCTRL_CTRLB_READMODE(mask)) >> NVMCTRL_CTRLB_READMODE_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_write_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Nvmctrl *)hw)->CTRLB.reg;
|
|
tmp &= ~NVMCTRL_CTRLB_READMODE_Msk;
|
|
tmp |= NVMCTRL_CTRLB_READMODE(data);
|
|
((Nvmctrl *)hw)->CTRLB.reg = tmp;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_READMODE(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_toggle_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_READMODE(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_READMODE_bf(const void *const hw)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->CTRLB.reg;
|
|
tmp = (tmp & NVMCTRL_CTRLB_READMODE_Msk) >> NVMCTRL_CTRLB_READMODE_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_set_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->CTRLB.reg |= mask;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->CTRLB.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->CTRLB.reg = data;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->CTRLB.reg &= ~mask;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_toggle_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->CTRLB.reg ^= mask;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_reg(const void *const hw)
|
|
{
|
|
return ((Nvmctrl *)hw)->CTRLB.reg;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_set_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_NVMP(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->PARAM.reg;
|
|
tmp = (tmp & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_write_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Nvmctrl *)hw)->PARAM.reg;
|
|
tmp &= ~NVMCTRL_PARAM_NVMP_Msk;
|
|
tmp |= NVMCTRL_PARAM_NVMP(data);
|
|
((Nvmctrl *)hw)->PARAM.reg = tmp;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_NVMP(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_toggle_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_NVMP(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->PARAM.reg;
|
|
tmp = (tmp & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_set_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_PSZ(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->PARAM.reg;
|
|
tmp = (tmp & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_write_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Nvmctrl *)hw)->PARAM.reg;
|
|
tmp &= ~NVMCTRL_PARAM_PSZ_Msk;
|
|
tmp |= NVMCTRL_PARAM_PSZ(data);
|
|
((Nvmctrl *)hw)->PARAM.reg = tmp;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_PSZ(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_toggle_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_PSZ(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->PARAM.reg;
|
|
tmp = (tmp & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_set_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->PARAM.reg |= mask;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->PARAM.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_write_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t data)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->PARAM.reg = data;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->PARAM.reg &= ~mask;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_toggle_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->PARAM.reg ^= mask;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw)
|
|
{
|
|
return ((Nvmctrl *)hw)->PARAM.reg;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->ADDR.reg;
|
|
tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Nvmctrl *)hw)->ADDR.reg;
|
|
tmp &= ~NVMCTRL_ADDR_ADDR_Msk;
|
|
tmp |= NVMCTRL_ADDR_ADDR(data);
|
|
((Nvmctrl *)hw)->ADDR.reg = tmp;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->ADDR.reg;
|
|
tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->ADDR.reg |= mask;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->ADDR.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->ADDR.reg = data;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->ADDR.reg &= ~mask;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->ADDR.reg ^= mask;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw)
|
|
{
|
|
return ((Nvmctrl *)hw)->ADDR.reg;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_set_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->LOCK.reg |= NVMCTRL_LOCK_LOCK(mask);
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
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{
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uint16_t tmp;
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tmp = ((Nvmctrl *)hw)->LOCK.reg;
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tmp = (tmp & NVMCTRL_LOCK_LOCK(mask)) >> NVMCTRL_LOCK_LOCK_Pos;
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return tmp;
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}
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static inline void hri_nvmctrl_write_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t data)
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{
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uint16_t tmp;
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NVMCTRL_CRITICAL_SECTION_ENTER();
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tmp = ((Nvmctrl *)hw)->LOCK.reg;
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tmp &= ~NVMCTRL_LOCK_LOCK_Msk;
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tmp |= NVMCTRL_LOCK_LOCK(data);
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((Nvmctrl *)hw)->LOCK.reg = tmp;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_clear_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->LOCK.reg &= ~NVMCTRL_LOCK_LOCK(mask);
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvmctrl_toggle_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->LOCK.reg ^= NVMCTRL_LOCK_LOCK(mask);
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_LOCK_bf(const void *const hw)
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{
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uint16_t tmp;
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tmp = ((Nvmctrl *)hw)->LOCK.reg;
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tmp = (tmp & NVMCTRL_LOCK_LOCK_Msk) >> NVMCTRL_LOCK_LOCK_Pos;
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return tmp;
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}
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static inline void hri_nvmctrl_set_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
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{
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NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->LOCK.reg |= mask;
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NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
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{
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|
uint16_t tmp;
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tmp = ((Nvmctrl *)hw)->LOCK.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_nvmctrl_write_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t data)
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|
{
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|
NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->LOCK.reg = data;
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|
NVMCTRL_CRITICAL_SECTION_LEAVE();
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}
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|
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static inline void hri_nvmctrl_clear_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
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|
{
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|
NVMCTRL_CRITICAL_SECTION_ENTER();
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((Nvmctrl *)hw)->LOCK.reg &= ~mask;
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|
NVMCTRL_CRITICAL_SECTION_LEAVE();
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|
}
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|
|
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static inline void hri_nvmctrl_toggle_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
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|
((Nvmctrl *)hw)->LOCK.reg ^= mask;
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|
NVMCTRL_CRITICAL_SECTION_LEAVE();
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|
}
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|
|
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static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_reg(const void *const hw)
|
|
{
|
|
return ((Nvmctrl *)hw)->LOCK.reg;
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|
}
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|
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static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw)
|
|
{
|
|
return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos;
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|
}
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|
|
|
static inline void hri_nvmctrl_clear_STATUS_PRM_bit(const void *const hw)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PRM;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw)
|
|
{
|
|
return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_STATUS_LOAD_bit(const void *const hw)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOAD;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_nvmctrl_get_STATUS_PROGE_bit(const void *const hw)
|
|
{
|
|
return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PROGE) >> NVMCTRL_STATUS_PROGE_Pos;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_STATUS_PROGE_bit(const void *const hw)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PROGE;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_nvmctrl_get_STATUS_LOCKE_bit(const void *const hw)
|
|
{
|
|
return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOCKE) >> NVMCTRL_STATUS_LOCKE_Pos;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_STATUS_LOCKE_bit(const void *const hw)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOCKE;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_nvmctrl_get_STATUS_NVME_bit(const void *const hw)
|
|
{
|
|
return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_NVME) >> NVMCTRL_STATUS_NVME_Pos;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_STATUS_NVME_bit(const void *const hw)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_NVME;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_nvmctrl_get_STATUS_SB_bit(const void *const hw)
|
|
{
|
|
return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SB) >> NVMCTRL_STATUS_SB_Pos;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_STATUS_SB_bit(const void *const hw)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_SB;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask)
|
|
{
|
|
uint16_t tmp;
|
|
tmp = ((Nvmctrl *)hw)->STATUS.reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_nvmctrl_clear_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask)
|
|
{
|
|
NVMCTRL_CRITICAL_SECTION_ENTER();
|
|
((Nvmctrl *)hw)->STATUS.reg = mask;
|
|
NVMCTRL_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw)
|
|
{
|
|
return ((Nvmctrl *)hw)->STATUS.reg;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _HRI_NVMCTRL_D21_H_INCLUDED */
|
|
#endif /* _SAMD21_NVMCTRL_COMPONENT_ */
|