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270 lines
7.3 KiB
C
270 lines
7.3 KiB
C
/**
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* \file
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*
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* \brief SAM NVIC
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*
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* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAMD21_NVIC_COMPONENT_
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#ifndef _HRI_NVIC_D21_H_INCLUDED_
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#define _HRI_NVIC_D21_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_NVIC_CRITICAL_SECTIONS)
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#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define NVIC_CRITICAL_SECTION_ENTER()
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#define NVIC_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint32_t hri_nvic_icer_reg_t;
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typedef uint32_t hri_nvic_icpr_reg_t;
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typedef uint32_t hri_nvic_ipr_reg_t;
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typedef uint32_t hri_nvic_iser_reg_t;
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typedef uint32_t hri_nvic_ispr_reg_t;
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static inline void hri_nvic_set_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ISER.reg |= mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Nvic *)hw)->ISER.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_nvic_write_ISER_reg(const void *const hw, hri_nvic_iser_reg_t data)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ISER.reg = data;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvic_clear_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ISER.reg &= ~mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvic_toggle_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ISER.reg ^= mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw)
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{
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return ((Nvic *)hw)->ISER.reg;
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}
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static inline void hri_nvic_set_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ICER.reg |= mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Nvic *)hw)->ICER.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_nvic_write_ICER_reg(const void *const hw, hri_nvic_icer_reg_t data)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ICER.reg = data;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvic_clear_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ICER.reg &= ~mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvic_toggle_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ICER.reg ^= mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw)
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{
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return ((Nvic *)hw)->ICER.reg;
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}
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static inline void hri_nvic_set_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ISPR.reg |= mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Nvic *)hw)->ISPR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_nvic_write_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t data)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ISPR.reg = data;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvic_clear_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ISPR.reg &= ~mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ISPR.reg ^= mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw)
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{
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return ((Nvic *)hw)->ISPR.reg;
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}
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static inline void hri_nvic_set_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ICPR.reg |= mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Nvic *)hw)->ICPR.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_nvic_write_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t data)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ICPR.reg = data;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvic_clear_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ICPR.reg &= ~mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->ICPR.reg ^= mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw)
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{
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return ((Nvic *)hw)->ICPR.reg;
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}
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static inline void hri_nvic_set_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->IPR[index].reg |= mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvic_ipr_reg_t hri_nvic_get_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Nvic *)hw)->IPR[index].reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_nvic_write_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t data)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->IPR[index].reg = data;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvic_clear_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->IPR[index].reg &= ~mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_nvic_toggle_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask)
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{
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NVIC_CRITICAL_SECTION_ENTER();
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((Nvic *)hw)->IPR[index].reg ^= mask;
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NVIC_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_nvic_ipr_reg_t hri_nvic_read_IPR_reg(const void *const hw, uint8_t index)
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{
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return ((Nvic *)hw)->IPR[index].reg;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HRI_NVIC_D21_H_INCLUDED */
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#endif /* _SAMD21_NVIC_COMPONENT_ */
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