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251 lines
12 KiB
C
251 lines
12 KiB
C
3 years ago
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/**
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* \file
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*
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* \brief Generic Clock Controller v210 related functionality.
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*
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* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <hpl_gclk_config.h>
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#include <hpl_init.h>
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#include <utils_assert.h>
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/* Make the macro name compatible to different header versions */
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#if !defined(GCLK_GENCTRL_SRC_FDPLL) && defined(GCLK_GENCTRL_SRC_DPLL96M)
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#define GCLK_GENCTRL_SRC_FDPLL GCLK_GENCTRL_SRC_DPLL96M
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#endif
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/**
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* \brief Initializes generators
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*/
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void _gclk_init_generators(void)
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{
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#if CONF_GCLK_GENERATOR_0_CONFIG == 1
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_0_DIV) | GCLK_GENDIV_ID(0));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
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| (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos)
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| (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos)
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| CONF_GCLK_GEN_0_SRC | GCLK_GENCTRL_ID(0));
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#endif
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#if CONF_GCLK_GENERATOR_1_CONFIG == 1
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_1_DIV) | GCLK_GENDIV_ID(1));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
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| (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos)
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| (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos)
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| CONF_GCLK_GEN_1_SRC | GCLK_GENCTRL_ID(1));
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#endif
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#if CONF_GCLK_GENERATOR_2_CONFIG == 1
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_2_DIV) | GCLK_GENDIV_ID(2));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
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| (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos)
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| (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos)
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| CONF_GCLK_GEN_2_SRC | GCLK_GENCTRL_ID(2));
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#endif
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#if CONF_GCLK_GENERATOR_3_CONFIG == 1
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_3_DIV) | GCLK_GENDIV_ID(3));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
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| (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos)
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| (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos)
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| CONF_GCLK_GEN_3_SRC | GCLK_GENCTRL_ID(3));
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#endif
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#if CONF_GCLK_GENERATOR_4_CONFIG == 1
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_4_DIV) | GCLK_GENDIV_ID(4));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
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| (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos)
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| (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos)
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| CONF_GCLK_GEN_4_SRC | GCLK_GENCTRL_ID(4));
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#endif
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#if CONF_GCLK_GENERATOR_5_CONFIG == 1
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_5_DIV) | GCLK_GENDIV_ID(5));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
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| (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos)
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| (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos)
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| CONF_GCLK_GEN_5_SRC | GCLK_GENCTRL_ID(5));
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#endif
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#if CONF_GCLK_GENERATOR_6_CONFIG == 1
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_6_DIV) | GCLK_GENDIV_ID(6));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
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| (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos)
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| (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos)
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| CONF_GCLK_GEN_6_SRC | GCLK_GENCTRL_ID(6));
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#endif
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#if CONF_GCLK_GENERATOR_7_CONFIG == 1
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_7_DIV) | GCLK_GENDIV_ID(7));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
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| (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos)
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| (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos)
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| CONF_GCLK_GEN_7_SRC | GCLK_GENCTRL_ID(7));
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#endif
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#if CONF_GCLK_GENERATOR_8_CONFIG == 1
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_8_DIV) | GCLK_GENDIV_ID(8));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos)
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| (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos)
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| (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos)
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| CONF_GCLK_GEN_8_SRC | GCLK_GENCTRL_ID(8));
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#endif
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}
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void _gclk_init_generators_by_fref(uint32_t bm)
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{
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#if CONF_GCLK_GENERATOR_0_CONFIG == 1
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if (bm & (1ul << 0)) {
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_0_DIV) | GCLK_GENDIV_ID(0));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
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| (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos)
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| (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos)
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| (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SRC | GCLK_GENCTRL_ID(0));
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}
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#endif
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#if CONF_GCLK_GENERATOR_1_CONFIG == 1
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if (bm & (1ul << 1)) {
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_1_DIV) | GCLK_GENDIV_ID(1));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
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| (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos)
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| (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos)
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| (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SRC | GCLK_GENCTRL_ID(1));
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}
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#endif
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#if CONF_GCLK_GENERATOR_2_CONFIG == 1
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if (bm & (1ul << 2)) {
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_2_DIV) | GCLK_GENDIV_ID(2));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
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| (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos)
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| (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos)
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| (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SRC | GCLK_GENCTRL_ID(2));
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}
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#endif
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#if CONF_GCLK_GENERATOR_3_CONFIG == 1
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if (bm & (1ul << 3)) {
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_3_DIV) | GCLK_GENDIV_ID(3));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
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| (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos)
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| (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos)
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| (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SRC | GCLK_GENCTRL_ID(3));
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}
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#endif
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#if CONF_GCLK_GENERATOR_4_CONFIG == 1
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if (bm & (1ul << 4)) {
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_4_DIV) | GCLK_GENDIV_ID(4));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
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| (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos)
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| (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos)
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| (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SRC | GCLK_GENCTRL_ID(4));
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}
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#endif
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#if CONF_GCLK_GENERATOR_5_CONFIG == 1
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if (bm & (1ul << 5)) {
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_5_DIV) | GCLK_GENDIV_ID(5));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
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| (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos)
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| (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos)
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| (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SRC | GCLK_GENCTRL_ID(5));
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}
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#endif
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#if CONF_GCLK_GENERATOR_6_CONFIG == 1
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if (bm & (1ul << 6)) {
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_6_DIV) | GCLK_GENDIV_ID(6));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
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| (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos)
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| (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos)
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| (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SRC | GCLK_GENCTRL_ID(6));
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}
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#endif
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#if CONF_GCLK_GENERATOR_7_CONFIG == 1
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if (bm & (1ul << 7)) {
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hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_7_DIV) | GCLK_GENDIV_ID(7));
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hri_gclk_write_GENCTRL_reg(
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GCLK,
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(CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
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| (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos)
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| (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos)
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|
|
| (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SRC | GCLK_GENCTRL_ID(7));
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if CONF_GCLK_GENERATOR_8_CONFIG == 1
|
||
|
|
if (bm & (1ul << 8)) {
|
||
|
|
hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_8_DIV) | GCLK_GENDIV_ID(8));
|
||
|
|
hri_gclk_write_GENCTRL_reg(
|
||
|
|
GCLK,
|
||
|
|
(CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos)
|
||
|
|
| (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos)
|
||
|
|
| (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos)
|
||
|
|
| (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SRC | GCLK_GENCTRL_ID(8));
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|