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I2C-Detect/d21/asf3/d21_i2c_detect/Debug/d21_i2c_detect.lss

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init
3 years ago
d21_i2c_detect.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00004a40 00000000 00000000 00010000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .relocate 00000068 20000000 00004a40 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
2 .bss 000001f8 20000068 00004aa8 00020068 2**2
ALLOC
3 .stack 00002000 20000260 00004ca0 00020068 2**0
ALLOC
4 .ARM.attributes 00000028 00000000 00000000 00020068 2**0
CONTENTS, READONLY
5 .comment 00000059 00000000 00000000 00020090 2**0
CONTENTS, READONLY
6 .debug_info 0002ed6b 00000000 00000000 000200e9 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_abbrev 000040b7 00000000 00000000 0004ee54 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_loc 000059fe 00000000 00000000 00052f0b 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_aranges 000005b0 00000000 00000000 00058909 2**0
CONTENTS, READONLY, DEBUGGING
10 .debug_ranges 000005e0 00000000 00000000 00058eb9 2**0
CONTENTS, READONLY, DEBUGGING
11 .debug_macro 0001c3ea 00000000 00000000 00059499 2**0
CONTENTS, READONLY, DEBUGGING
12 .debug_line 0000dad3 00000000 00000000 00075883 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_str 0008f19a 00000000 00000000 00083356 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_frame 000016cc 00000000 00000000 001124f0 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00000000 <exception_table>:
0: 60 22 00 20 c9 1b 00 00 c5 1b 00 00 c5 1b 00 00 `". ............
...
2c: c5 1b 00 00 00 00 00 00 00 00 00 00 c5 1b 00 00 ................
3c: c5 1b 00 00 c5 1b 00 00 c5 1b 00 00 c5 1b 00 00 ................
4c: c5 1b 00 00 c5 1b 00 00 c5 1b 00 00 c5 1b 00 00 ................
5c: c5 1b 00 00 c5 1b 00 00 f9 14 00 00 09 15 00 00 ................
6c: 19 15 00 00 29 15 00 00 39 15 00 00 49 15 00 00 ....)...9...I...
7c: c5 1b 00 00 c5 1b 00 00 c5 1b 00 00 c5 1b 00 00 ................
8c: c5 1b 00 00 c5 1b 00 00 c5 1b 00 00 c5 1b 00 00 ................
9c: c5 1b 00 00 c5 1b 00 00 c5 1b 00 00 c5 1b 00 00 ................
ac: c5 1b 00 00 00 00 00 00 ........
000000b4 <__do_global_dtors_aux>:
b4: b510 push {r4, lr}
b6: 4c06 ldr r4, [pc, #24] ; (d0 <__do_global_dtors_aux+0x1c>)
b8: 7823 ldrb r3, [r4, #0]
ba: 2b00 cmp r3, #0
bc: d107 bne.n ce <__do_global_dtors_aux+0x1a>
be: 4b05 ldr r3, [pc, #20] ; (d4 <__do_global_dtors_aux+0x20>)
c0: 2b00 cmp r3, #0
c2: d002 beq.n ca <__do_global_dtors_aux+0x16>
c4: 4804 ldr r0, [pc, #16] ; (d8 <__do_global_dtors_aux+0x24>)
c6: e000 b.n ca <__do_global_dtors_aux+0x16>
c8: bf00 nop
ca: 2301 movs r3, #1
cc: 7023 strb r3, [r4, #0]
ce: bd10 pop {r4, pc}
d0: 20000068 .word 0x20000068
d4: 00000000 .word 0x00000000
d8: 00004a40 .word 0x00004a40
000000dc <frame_dummy>:
dc: 4b08 ldr r3, [pc, #32] ; (100 <frame_dummy+0x24>)
de: b510 push {r4, lr}
e0: 2b00 cmp r3, #0
e2: d003 beq.n ec <frame_dummy+0x10>
e4: 4907 ldr r1, [pc, #28] ; (104 <frame_dummy+0x28>)
e6: 4808 ldr r0, [pc, #32] ; (108 <frame_dummy+0x2c>)
e8: e000 b.n ec <frame_dummy+0x10>
ea: bf00 nop
ec: 4807 ldr r0, [pc, #28] ; (10c <frame_dummy+0x30>)
ee: 6803 ldr r3, [r0, #0]
f0: 2b00 cmp r3, #0
f2: d100 bne.n f6 <frame_dummy+0x1a>
f4: bd10 pop {r4, pc}
f6: 4b06 ldr r3, [pc, #24] ; (110 <frame_dummy+0x34>)
f8: 2b00 cmp r3, #0
fa: d0fb beq.n f4 <frame_dummy+0x18>
fc: 4798 blx r3
fe: e7f9 b.n f4 <frame_dummy+0x18>
100: 00000000 .word 0x00000000
104: 2000006c .word 0x2000006c
108: 00004a40 .word 0x00004a40
10c: 00004a40 .word 0x00004a40
110: 00000000 .word 0x00000000
00000114 <_i2c_master_wait_for_sync>:
/* Set action to NACK */
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
} else {
/* Save data to buffer. */
_i2c_master_wait_for_sync(module);
packet->data[counter++] = i2c_module->DATA.reg;
114: 6801 ldr r1, [r0, #0]
/* Wait for response. */
tmp_status = _i2c_master_wait_for_bus(module);
116: 2207 movs r2, #7
118: 69cb ldr r3, [r1, #28]
11a: 421a tst r2, r3
11c: d1fc bne.n 118 <_i2c_master_wait_for_sync+0x4>
11e: 4770 bx lr
00000120 <i2c_master_init>:
}
/* Check for error. */
if (tmp_status != STATUS_OK) {
120: b5f0 push {r4, r5, r6, r7, lr}
122: 46d6 mov lr, sl
packet->data[counter++] = i2c_module->DATA.reg;
124: 464f mov r7, r9
while (tmp_data_length--) {
126: 4646 mov r6, r8
128: b5c0 push {r6, r7, lr}
if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
12a: b08a sub sp, #40 ; 0x28
12c: 0006 movs r6, r0
12e: 000f movs r7, r1
if (module->send_nack && (((!sclsm_flag) && (tmp_data_length == 0)) ||
130: 0014 movs r4, r2
132: 6031 str r1, [r6, #0]
134: 0008 movs r0, r1
136: 4ba0 ldr r3, [pc, #640] ; (3b8 <i2c_master_init+0x298>)
138: 4798 blx r3
13a: 4aa0 ldr r2, [pc, #640] ; (3bc <i2c_master_init+0x29c>)
13c: 6a11 ldr r1, [r2, #32]
13e: 1c85 adds r5, r0, #2
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
140: 2301 movs r3, #1
142: 40ab lsls r3, r5
144: 430b orrs r3, r1
146: 6213 str r3, [r2, #32]
148: a909 add r1, sp, #36 ; 0x24
14a: 7b23 ldrb r3, [r4, #12]
14c: 700b strb r3, [r1, #0]
14e: 3014 adds r0, #20
packet->data[counter++] = i2c_module->DATA.reg;
150: b2c5 uxtb r5, r0
tmp_status = _i2c_master_wait_for_bus(module);
152: 0028 movs r0, r5
break;
}
}
if (module->send_stop) {
154: 4b9a ldr r3, [pc, #616] ; (3c0 <i2c_master_init+0x2a0>)
156: 4798 blx r3
158: 0028 movs r0, r5
_i2c_master_wait_for_sync(module);
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
}
/* Save last data to buffer. */
_i2c_master_wait_for_sync(module);
15a: 4b9a ldr r3, [pc, #616] ; (3c4 <i2c_master_init+0x2a4>)
15c: 4798 blx r3
15e: 7b20 ldrb r0, [r4, #12]
packet->data[counter] = i2c_module->DATA.reg;
160: 2100 movs r1, #0
162: 4b99 ldr r3, [pc, #612] ; (3c8 <i2c_master_init+0x2a8>)
164: 4798 blx r3
166: 683b ldr r3, [r7, #0]
168: 201c movs r0, #28
16a: 079b lsls r3, r3, #30
16c: d505 bpl.n 17a <i2c_master_init+0x5a>
_i2c_master_wait_for_sync(module);
16e: b00a add sp, #40 ; 0x28
170: bc1c pop {r2, r3, r4}
172: 4690 mov r8, r2
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
174: 4699 mov r9, r3
176: 46a2 mov sl, r4
178: bdf0 pop {r4, r5, r6, r7, pc}
17a: 683b ldr r3, [r7, #0]
17c: 3817 subs r0, #23
17e: 07db lsls r3, r3, #31
return STATUS_ERR_PACKET_COLLISION;
180: d4f5 bmi.n 16e <i2c_master_init+0x4e>
182: 6830 ldr r0, [r6, #0]
184: 4b8c ldr r3, [pc, #560] ; (3b8 <i2c_master_init+0x298>)
186: 4699 mov r9, r3
188: 4798 blx r3
18a: 0005 movs r5, r0
18c: 498f ldr r1, [pc, #572] ; (3cc <i2c_master_init+0x2ac>)
18e: 4b90 ldr r3, [pc, #576] ; (3d0 <i2c_master_init+0x2b0>)
190: 4798 blx r3
192: 00ad lsls r5, r5, #2
194: 4b8f ldr r3, [pc, #572] ; (3d4 <i2c_master_init+0x2b4>)
196: 50ee str r6, [r5, r3]
198: 2300 movs r3, #0
19a: 7633 strb r3, [r6, #24]
19c: 7673 strb r3, [r6, #25]
19e: 2500 movs r5, #0
module->buffer_length = 0;
1a0: 8373 strh r3, [r6, #26]
module->buffer_remaining = 0;
1a2: 83b3 strh r3, [r6, #28]
module->status = STATUS_OK;
1a4: 2225 movs r2, #37 ; 0x25
1a6: 54b5 strb r5, [r6, r2]
module->buffer = NULL;
1a8: 6233 str r3, [r6, #32]
i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE(0x5);
1aa: 3314 adds r3, #20
1ac: 603b str r3, [r7, #0]
SercomI2cm *const i2c_module = &(module->hw->I2CM);
1ae: 6833 ldr r3, [r6, #0]
1b0: 4698 mov r8, r3
uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw);
1b2: 0018 movs r0, r3
1b4: 47c8 blx r9
1b6: 4681 mov r9, r0
{
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->mux_position = SYSTEM_PINMUX_GPIO;
1b8: 2380 movs r3, #128 ; 0x80
1ba: aa08 add r2, sp, #32
1bc: 7013 strb r3, [r2, #0]
config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
1be: 7055 strb r5, [r2, #1]
config->input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
1c0: 2301 movs r3, #1
1c2: 7093 strb r3, [r2, #2]
config->powersave = false;
1c4: 70d5 strb r5, [r2, #3]
uint32_t pad0 = config->pinmux_pad0;
1c6: 69e0 ldr r0, [r4, #28]
uint32_t pad1 = config->pinmux_pad1;
1c8: 6a27 ldr r7, [r4, #32]
if (pad0 == PINMUX_DEFAULT) {
1ca: 2800 cmp r0, #0
1cc: d100 bne.n 1d0 <i2c_master_init+0xb0>
1ce: e0af b.n 330 <i2c_master_init+0x210>
pin_conf.mux_position = pad0 & 0xFFFF;
1d0: ab08 add r3, sp, #32
1d2: 7018 strb r0, [r3, #0]
pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
1d4: 2302 movs r3, #2
1d6: aa08 add r2, sp, #32
1d8: 7053 strb r3, [r2, #1]
system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
1da: 0c00 lsrs r0, r0, #16
1dc: b2c0 uxtb r0, r0
1de: 0011 movs r1, r2
1e0: 4b7d ldr r3, [pc, #500] ; (3d8 <i2c_master_init+0x2b8>)
1e2: 4798 blx r3
if (pad1 == PINMUX_DEFAULT) {
1e4: 2f00 cmp r7, #0
1e6: d100 bne.n 1ea <i2c_master_init+0xca>
1e8: e0a7 b.n 33a <i2c_master_init+0x21a>
pin_conf.mux_position = pad1 & 0xFFFF;
1ea: ab08 add r3, sp, #32
1ec: 701f strb r7, [r3, #0]
pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
1ee: 2302 movs r3, #2
1f0: aa08 add r2, sp, #32
1f2: 7053 strb r3, [r2, #1]
system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
1f4: 0c3f lsrs r7, r7, #16
1f6: b2f8 uxtb r0, r7
1f8: 0011 movs r1, r2
1fa: 4b77 ldr r3, [pc, #476] ; (3d8 <i2c_master_init+0x2b8>)
1fc: 4798 blx r3
module->unknown_bus_state_timeout = config->unknown_bus_state_timeout;
1fe: 8aa3 ldrh r3, [r4, #20]
200: 80f3 strh r3, [r6, #6]
module->buffer_timeout = config->buffer_timeout;
202: 8ae3 ldrh r3, [r4, #22]
204: 8133 strh r3, [r6, #8]
if (config->run_in_standby || system_is_debugger_present()) {
206: 7e23 ldrb r3, [r4, #24]
tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY;
208: 2280 movs r2, #128 ; 0x80
if (config->run_in_standby || system_is_debugger_present()) {
20a: 2b00 cmp r3, #0
20c: d104 bne.n 218 <i2c_master_init+0xf8>
* \retval false Debugger is not connected to the system
*
*/
static inline bool system_is_debugger_present(void)
{
return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
20e: 4b73 ldr r3, [pc, #460] ; (3dc <i2c_master_init+0x2bc>)
210: 789b ldrb r3, [r3, #2]
212: 079b lsls r3, r3, #30
tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY;
214: 0fdb lsrs r3, r3, #31
216: 01da lsls r2, r3, #7
tmp_ctrla |= config->transfer_speed;
218: 68a1 ldr r1, [r4, #8]
21a: 6923 ldr r3, [r4, #16]
21c: 430b orrs r3, r1
21e: 4313 orrs r3, r2
if (config->scl_low_timeout) {
220: 2224 movs r2, #36 ; 0x24
222: 5ca2 ldrb r2, [r4, r2]
224: 2a00 cmp r2, #0
226: d002 beq.n 22e <i2c_master_init+0x10e>
tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
228: 2280 movs r2, #128 ; 0x80
22a: 05d2 lsls r2, r2, #23
22c: 4313 orrs r3, r2
tmp_ctrla |= config->inactive_timeout;
22e: 6aa2 ldr r2, [r4, #40] ; 0x28
230: 4313 orrs r3, r2
if (config->scl_stretch_only_after_ack_bit || (config->transfer_speed == I2C_MASTER_SPEED_HIGH_SPEED)) {
232: 222c movs r2, #44 ; 0x2c
234: 5ca2 ldrb r2, [r4, r2]
236: 2a00 cmp r2, #0
238: d103 bne.n 242 <i2c_master_init+0x122>
23a: 2280 movs r2, #128 ; 0x80
23c: 0492 lsls r2, r2, #18
23e: 4291 cmp r1, r2
240: d102 bne.n 248 <i2c_master_init+0x128>
tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM;
242: 2280 movs r2, #128 ; 0x80
244: 0512 lsls r2, r2, #20
246: 4313 orrs r3, r2
if (config->slave_scl_low_extend_timeout) {
248: 222d movs r2, #45 ; 0x2d
24a: 5ca2 ldrb r2, [r4, r2]
24c: 2a00 cmp r2, #0
24e: d002 beq.n 256 <i2c_master_init+0x136>
tmp_ctrla |= SERCOM_I2CM_CTRLA_SEXTTOEN;
250: 2280 movs r2, #128 ; 0x80
252: 0412 lsls r2, r2, #16
254: 4313 orrs r3, r2
if (config->master_scl_low_extend_timeout) {
256: 222e movs r2, #46 ; 0x2e
258: 5ca2 ldrb r2, [r4, r2]
25a: 2a00 cmp r2, #0
25c: d002 beq.n 264 <i2c_master_init+0x144>
tmp_ctrla |= SERCOM_I2CM_CTRLA_MEXTTOEN;
25e: 2280 movs r2, #128 ; 0x80
260: 03d2 lsls r2, r2, #15
262: 4313 orrs r3, r2
i2c_module->CTRLA.reg |= tmp_ctrla;
264: 4642 mov r2, r8
266: 6812 ldr r2, [r2, #0]
268: 4313 orrs r3, r2
26a: 4642 mov r2, r8
26c: 6013 str r3, [r2, #0]
i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
26e: 2380 movs r3, #128 ; 0x80
270: 005b lsls r3, r3, #1
272: 6053 str r3, [r2, #4]
uint32_t fgclk = system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index);
274: 4648 mov r0, r9
276: 3014 adds r0, #20
278: b2c0 uxtb r0, r0
27a: 4b59 ldr r3, [pc, #356] ; (3e0 <i2c_master_init+0x2c0>)
27c: 4798 blx r3
27e: 9007 str r0, [sp, #28]
uint32_t fscl = 1000 * config->baud_rate;
280: 23fa movs r3, #250 ; 0xfa
282: 009b lsls r3, r3, #2
284: 6822 ldr r2, [r4, #0]
286: 435a muls r2, r3
288: 4691 mov r9, r2
uint32_t fscl_hs = 1000 * config->baud_rate_high_speed;
28a: 6863 ldr r3, [r4, #4]
28c: 469a mov sl, r3
tmp_baud = (int32_t)(div_ceil(
28e: 4d55 ldr r5, [pc, #340] ; (3e4 <i2c_master_init+0x2c4>)
290: 47a8 blx r5
292: 9000 str r0, [sp, #0]
294: 9101 str r1, [sp, #4]
296: 464b mov r3, r9
298: 0058 lsls r0, r3, #1
29a: 47a8 blx r5
29c: 9002 str r0, [sp, #8]
29e: 9103 str r1, [sp, #12]
2a0: 8e20 ldrh r0, [r4, #48] ; 0x30
2a2: 47a8 blx r5
2a4: 9004 str r0, [sp, #16]
2a6: 9105 str r1, [sp, #20]
2a8: 4f4f ldr r7, [pc, #316] ; (3e8 <i2c_master_init+0x2c8>)
2aa: 4a50 ldr r2, [pc, #320] ; (3ec <i2c_master_init+0x2cc>)
2ac: 4b50 ldr r3, [pc, #320] ; (3f0 <i2c_master_init+0x2d0>)
2ae: 9800 ldr r0, [sp, #0]
2b0: 9901 ldr r1, [sp, #4]
2b2: 47b8 blx r7
2b4: 0002 movs r2, r0
2b6: 000b movs r3, r1
2b8: 9804 ldr r0, [sp, #16]
2ba: 9905 ldr r1, [sp, #20]
2bc: 47b8 blx r7
2be: 4e4d ldr r6, [pc, #308] ; (3f4 <i2c_master_init+0x2d4>)
2c0: 2200 movs r2, #0
2c2: 4b4d ldr r3, [pc, #308] ; (3f8 <i2c_master_init+0x2d8>)
2c4: 47b0 blx r6
2c6: 9004 str r0, [sp, #16]
2c8: 9105 str r1, [sp, #20]
2ca: 4648 mov r0, r9
2cc: 47a8 blx r5
2ce: 0002 movs r2, r0
2d0: 000b movs r3, r1
2d2: 9804 ldr r0, [sp, #16]
2d4: 9905 ldr r1, [sp, #20]
2d6: 47b8 blx r7
2d8: 0002 movs r2, r0
2da: 000b movs r3, r1
2dc: 4d47 ldr r5, [pc, #284] ; (3fc <i2c_master_init+0x2dc>)
2de: 9800 ldr r0, [sp, #0]
2e0: 9901 ldr r1, [sp, #4]
2e2: 47a8 blx r5
2e4: 9a02 ldr r2, [sp, #8]
2e6: 9b03 ldr r3, [sp, #12]
2e8: 47b0 blx r6
2ea: 2200 movs r2, #0
2ec: 4b44 ldr r3, [pc, #272] ; (400 <i2c_master_init+0x2e0>)
2ee: 47a8 blx r5
2f0: 9a02 ldr r2, [sp, #8]
2f2: 9b03 ldr r3, [sp, #12]
2f4: 4d43 ldr r5, [pc, #268] ; (404 <i2c_master_init+0x2e4>)
2f6: 47a8 blx r5
2f8: 4b43 ldr r3, [pc, #268] ; (408 <i2c_master_init+0x2e8>)
2fa: 4798 blx r3
2fc: 0005 movs r5, r0
if (config->transfer_speed == I2C_MASTER_SPEED_HIGH_SPEED) {
2fe: 2380 movs r3, #128 ; 0x80
300: 049b lsls r3, r3, #18
302: 68a2 ldr r2, [r4, #8]
304: 429a cmp r2, r3
306: d01e beq.n 346 <i2c_master_init+0x226>
if (tmp_baud > 255 || tmp_baud < 0 || tmp_baud_hs > 255 || tmp_baud_hs < 0) {
308: 0003 movs r3, r0
30a: 2040 movs r0, #64 ; 0x40
30c: 2dff cmp r5, #255 ; 0xff
30e: d900 bls.n 312 <i2c_master_init+0x1f2>
310: e72d b.n 16e <i2c_master_init+0x4e>
int32_t tmp_baudlow_hs = 0;
312: 2400 movs r4, #0
int32_t tmp_baud_hs = 0;
314: 2000 movs r0, #0
i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) |
316: 25ff movs r5, #255 ; 0xff
318: 401d ands r5, r3
SERCOM_I2CM_BAUD_HSBAUD(tmp_baud_hs) | SERCOM_I2CM_BAUD_HSBAUDLOW(tmp_baudlow_hs);
31a: 0624 lsls r4, r4, #24
31c: 4325 orrs r5, r4
31e: 0400 lsls r0, r0, #16
320: 23ff movs r3, #255 ; 0xff
322: 041b lsls r3, r3, #16
324: 4018 ands r0, r3
326: 4305 orrs r5, r0
i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) |
328: 4643 mov r3, r8
32a: 60dd str r5, [r3, #12]
enum status_code tmp_status_code = STATUS_OK;
32c: 2000 movs r0, #0
32e: e71e b.n 16e <i2c_master_init+0x4e>
pad0 = _sercom_get_default_pad(sercom_hw, 0);
330: 2100 movs r1, #0
332: 4640 mov r0, r8
334: 4b35 ldr r3, [pc, #212] ; (40c <i2c_master_init+0x2ec>)
336: 4798 blx r3
338: e74a b.n 1d0 <i2c_master_init+0xb0>
pad1 = _sercom_get_default_pad(sercom_hw, 1);
33a: 2101 movs r1, #1
33c: 4640 mov r0, r8
33e: 4b33 ldr r3, [pc, #204] ; (40c <i2c_master_init+0x2ec>)
340: 4798 blx r3
342: 0007 movs r7, r0
344: e751 b.n 1ea <i2c_master_init+0xca>
uint32_t fscl_hs = 1000 * config->baud_rate_high_speed;
346: 26fa movs r6, #250 ; 0xfa
348: 00b6 lsls r6, r6, #2
34a: 4653 mov r3, sl
34c: 435e muls r6, r3
tmp_baudlow_hs = (int32_t)((fgclk * 2.0) / (3.0 * fscl_hs) - 1);
34e: 9800 ldr r0, [sp, #0]
350: 9901 ldr r1, [sp, #4]
352: 0002 movs r2, r0
354: 000b movs r3, r1
356: 4c27 ldr r4, [pc, #156] ; (3f4 <i2c_master_init+0x2d4>)
358: 47a0 blx r4
35a: 9000 str r0, [sp, #0]
35c: 9101 str r1, [sp, #4]
35e: 0030 movs r0, r6
360: 4b20 ldr r3, [pc, #128] ; (3e4 <i2c_master_init+0x2c4>)
362: 4798 blx r3
364: 2200 movs r2, #0
366: 4b2a ldr r3, [pc, #168] ; (410 <i2c_master_init+0x2f0>)
368: 47b8 blx r7
36a: 0002 movs r2, r0
36c: 000b movs r3, r1
36e: 9800 ldr r0, [sp, #0]
370: 9901 ldr r1, [sp, #4]
372: 4c24 ldr r4, [pc, #144] ; (404 <i2c_master_init+0x2e4>)
374: 47a0 blx r4
376: 2200 movs r2, #0
378: 4b21 ldr r3, [pc, #132] ; (400 <i2c_master_init+0x2e0>)
37a: 4c20 ldr r4, [pc, #128] ; (3fc <i2c_master_init+0x2dc>)
37c: 47a0 blx r4
37e: 4b22 ldr r3, [pc, #136] ; (408 <i2c_master_init+0x2e8>)
380: 4798 blx r3
382: 1e04 subs r4, r0, #0
if (tmp_baudlow_hs) {
384: d00c beq.n 3a0 <i2c_master_init+0x280>
tmp_baud_hs = (int32_t)(fgclk / fscl_hs) - 2 - tmp_baudlow_hs;
386: 0031 movs r1, r6
388: 9807 ldr r0, [sp, #28]
38a: 4b22 ldr r3, [pc, #136] ; (414 <i2c_master_init+0x2f4>)
38c: 4798 blx r3
38e: 3802 subs r0, #2
390: 1b00 subs r0, r0, r4
if (tmp_baud > 255 || tmp_baud < 0 || tmp_baud_hs > 255 || tmp_baud_hs < 0) {
392: 002b movs r3, r5
394: 2dff cmp r5, #255 ; 0xff
396: d80c bhi.n 3b2 <i2c_master_init+0x292>
398: 28ff cmp r0, #255 ; 0xff
39a: d9bc bls.n 316 <i2c_master_init+0x1f6>
39c: 2040 movs r0, #64 ; 0x40
39e: e6e6 b.n 16e <i2c_master_init+0x4e>
tmp_baud_hs = (int32_t)(div_ceil(fgclk, 2 * fscl_hs)) - 1;
3a0: 0071 lsls r1, r6, #1
3a2: 1e48 subs r0, r1, #1
3a4: 9b07 ldr r3, [sp, #28]
3a6: 469c mov ip, r3
3a8: 4460 add r0, ip
3aa: 4b1a ldr r3, [pc, #104] ; (414 <i2c_master_init+0x2f4>)
3ac: 4798 blx r3
3ae: 3801 subs r0, #1
3b0: e7ef b.n 392 <i2c_master_init+0x272>
if (tmp_baud > 255 || tmp_baud < 0 || tmp_baud_hs > 255 || tmp_baud_hs < 0) {
3b2: 2040 movs r0, #64 ; 0x40
3b4: e6db b.n 16e <i2c_master_init+0x4e>
3b6: 46c0 nop ; (mov r8, r8)
3b8: 00001451 .word 0x00001451
3bc: 40000400 .word 0x40000400
3c0: 00001a6d .word 0x00001a6d
3c4: 000019e1 .word 0x000019e1
3c8: 0000128d .word 0x0000128d
3cc: 000006a1 .word 0x000006a1
3d0: 0000148d .word 0x0000148d
3d4: 20000244 .word 0x20000244
3d8: 00001b65 .word 0x00001b65
3dc: 41002000 .word 0x41002000
3e0: 00001a89 .word 0x00001a89
3e4: 000036cd .word 0x000036cd
3e8: 00002b39 .word 0x00002b39
3ec: e826d695 .word 0xe826d695
3f0: 3e112e0b .word 0x3e112e0b
3f4: 00001eb1 .word 0x00001eb1
3f8: 40240000 .word 0x40240000
3fc: 00003039 .word 0x00003039
400: 3ff00000 .word 0x3ff00000
404: 000024d1 .word 0x000024d1
408: 00003665 .word 0x00003665
40c: 000012d9 .word 0x000012d9
410: 40080000 .word 0x40080000
414: 00001d45 .word 0x00001d45
00000418 <_i2c_master_address_response>:
SercomI2cm *const i2c_module = &(module->hw->I2CM);
418: 6803 ldr r3, [r0, #0]
if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) {
41a: 7e1a ldrb r2, [r3, #24]
41c: 0792 lsls r2, r2, #30
41e: d507 bpl.n 430 <_i2c_master_address_response+0x18>
i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
420: 2202 movs r2, #2
422: 761a strb r2, [r3, #24]
if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
424: 8b5b ldrh r3, [r3, #26]
426: 079b lsls r3, r3, #30
return STATUS_ERR_PACKET_COLLISION;
428: 2041 movs r0, #65 ; 0x41
return STATUS_OK;
42a: 17db asrs r3, r3, #31
42c: 4018 ands r0, r3
}
42e: 4770 bx lr
} else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
430: 8b5a ldrh r2, [r3, #26]
432: 0752 lsls r2, r2, #29
434: d506 bpl.n 444 <_i2c_master_address_response+0x2c>
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
436: 6859 ldr r1, [r3, #4]
438: 22c0 movs r2, #192 ; 0xc0
43a: 0292 lsls r2, r2, #10
43c: 430a orrs r2, r1
43e: 605a str r2, [r3, #4]
return STATUS_ERR_BAD_ADDRESS;
440: 2018 movs r0, #24
442: e7f4 b.n 42e <_i2c_master_address_response+0x16>
return STATUS_OK;
444: 2000 movs r0, #0
446: e7f2 b.n 42e <_i2c_master_address_response+0x16>
00000448 <_i2c_master_wait_for_bus>:
{
448: b530 push {r4, r5, lr}
SercomI2cm *const i2c_module = &(module->hw->I2CM);
44a: 6802 ldr r2, [r0, #0]
uint16_t timeout_counter = 0;
44c: 2300 movs r3, #0
while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) &&
44e: 2401 movs r4, #1
450: 2502 movs r5, #2
452: 7e11 ldrb r1, [r2, #24]
454: 4221 tst r1, r4
456: d10b bne.n 470 <_i2c_master_wait_for_bus+0x28>
!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)) {
458: 7e11 ldrb r1, [r2, #24]
while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) &&
45a: 4229 tst r1, r5
45c: d106 bne.n 46c <_i2c_master_wait_for_bus+0x24>
if (++timeout_counter >= module->buffer_timeout) {
45e: 3301 adds r3, #1
460: b29b uxth r3, r3
462: 8901 ldrh r1, [r0, #8]
464: 4299 cmp r1, r3
466: d8f4 bhi.n 452 <_i2c_master_wait_for_bus+0xa>
return STATUS_ERR_TIMEOUT;
468: 2012 movs r0, #18
46a: e002 b.n 472 <_i2c_master_wait_for_bus+0x2a>
return STATUS_OK;
46c: 2000 movs r0, #0
46e: e000 b.n 472 <_i2c_master_wait_for_bus+0x2a>
470: 2000 movs r0, #0
}
472: bd30 pop {r4, r5, pc}
00000474 <_i2c_master_send_hs_master_code>:
{
474: b510 push {r4, lr}
SercomI2cm *const i2c_module = &(module->hw->I2CM);
476: 6804 ldr r4, [r0, #0]
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
478: 6862 ldr r2, [r4, #4]
47a: 2380 movs r3, #128 ; 0x80
47c: 02db lsls r3, r3, #11
47e: 4313 orrs r3, r2
480: 6063 str r3, [r4, #4]
i2c_module->ADDR.reg = hs_master_code;
482: 6261 str r1, [r4, #36] ; 0x24
tmp_status = _i2c_master_wait_for_bus(module);
484: 4b02 ldr r3, [pc, #8] ; (490 <_i2c_master_send_hs_master_code+0x1c>)
486: 4798 blx r3
i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
488: 2301 movs r3, #1
48a: 7623 strb r3, [r4, #24]
}
48c: bd10 pop {r4, pc}
48e: 46c0 nop ; (mov r8, r8)
490: 00000449 .word 0x00000449
00000494 <_i2c_master_write_packet>:
* acknowledged the address
*/
static enum status_code _i2c_master_write_packet(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet)
{
494: b5f0 push {r4, r5, r6, r7, lr}
496: 46de mov lr, fp
498: 4657 mov r7, sl
49a: 464e mov r6, r9
49c: 4645 mov r5, r8
49e: b5e0 push {r5, r6, r7, lr}
4a0: b083 sub sp, #12
4a2: 0006 movs r6, r0
4a4: 000f movs r7, r1
SercomI2cm *const i2c_module = &(module->hw->I2CM);
4a6: 6805 ldr r5, [r0, #0]
/* Return value. */
enum status_code tmp_status;
uint16_t tmp_data_length = packet->data_length;
4a8: 884c ldrh r4, [r1, #2]
_i2c_master_wait_for_sync(module);
4aa: 4b32 ldr r3, [pc, #200] ; (574 <_i2c_master_write_packet+0xe0>)
4ac: 4798 blx r3
/* Switch to high speed mode */
if (packet->high_speed) {
4ae: 7a7b ldrb r3, [r7, #9]
4b0: 2b00 cmp r3, #0
4b2: d11d bne.n 4f0 <_i2c_master_write_packet+0x5c>
_i2c_master_send_hs_master_code(module, packet->hs_master_code);
}
/* Set action to ACK. */
i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
4b4: 686b ldr r3, [r5, #4]
4b6: 4a30 ldr r2, [pc, #192] ; (578 <_i2c_master_write_packet+0xe4>)
4b8: 4013 ands r3, r2
4ba: 606b str r3, [r5, #4]
/* Set address and direction bit. Will send start command on bus. */
if (packet->ten_bit_address) {
4bc: 7a3b ldrb r3, [r7, #8]
4be: 2b00 cmp r3, #0
4c0: d01b beq.n 4fa <_i2c_master_write_packet+0x66>
i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
4c2: 883b ldrh r3, [r7, #0]
4c4: 005b lsls r3, r3, #1
(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
4c6: 7a7a ldrb r2, [r7, #9]
4c8: 0392 lsls r2, r2, #14
i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
4ca: 4313 orrs r3, r2
(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
4cc: 2280 movs r2, #128 ; 0x80
4ce: 0212 lsls r2, r2, #8
4d0: 4313 orrs r3, r2
i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
4d2: 626b str r3, [r5, #36] ; 0x24
} else {
i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
}
/* Wait for response on bus. */
tmp_status = _i2c_master_wait_for_bus(module);
4d4: 0030 movs r0, r6
4d6: 4b29 ldr r3, [pc, #164] ; (57c <_i2c_master_write_packet+0xe8>)
4d8: 4798 blx r3
4da: 9001 str r0, [sp, #4]
/* Check for address response error unless previous error is
* detected. */
if (tmp_status == STATUS_OK) {
4dc: 2800 cmp r0, #0
4de: d013 beq.n 508 <_i2c_master_write_packet+0x74>
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
}
}
return tmp_status;
}
4e0: 9801 ldr r0, [sp, #4]
4e2: b003 add sp, #12
4e4: bc3c pop {r2, r3, r4, r5}
4e6: 4690 mov r8, r2
4e8: 4699 mov r9, r3
4ea: 46a2 mov sl, r4
4ec: 46ab mov fp, r5
4ee: bdf0 pop {r4, r5, r6, r7, pc}
_i2c_master_send_hs_master_code(module, packet->hs_master_code);
4f0: 7ab9 ldrb r1, [r7, #10]
4f2: 0030 movs r0, r6
4f4: 4b22 ldr r3, [pc, #136] ; (580 <_i2c_master_write_packet+0xec>)
4f6: 4798 blx r3
4f8: e7dc b.n 4b4 <_i2c_master_write_packet+0x20>
i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
4fa: 883b ldrh r3, [r7, #0]
4fc: 005b lsls r3, r3, #1
(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
4fe: 7a7a ldrb r2, [r7, #9]
500: 0392 lsls r2, r2, #14
i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
502: 4313 orrs r3, r2
504: 626b str r3, [r5, #36] ; 0x24
506: e7e5 b.n 4d4 <_i2c_master_write_packet+0x40>
tmp_status = _i2c_master_address_response(module);
508: 0030 movs r0, r6
50a: 4b1e ldr r3, [pc, #120] ; (584 <_i2c_master_write_packet+0xf0>)
50c: 4798 blx r3
50e: 1e03 subs r3, r0, #0
510: 9001 str r0, [sp, #4]
if (tmp_status == STATUS_OK) {
512: d1e5 bne.n 4e0 <_i2c_master_write_packet+0x4c>
514: 46a0 mov r8, r4
516: 2400 movs r4, #0
if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
518: 3320 adds r3, #32
51a: 4699 mov r9, r3
_i2c_master_wait_for_sync(module);
51c: 4b15 ldr r3, [pc, #84] ; (574 <_i2c_master_write_packet+0xe0>)
51e: 469b mov fp, r3
tmp_status = _i2c_master_wait_for_bus(module);
520: 4b16 ldr r3, [pc, #88] ; (57c <_i2c_master_write_packet+0xe8>)
522: 469a mov sl, r3
while (tmp_data_length--) {
524: 4544 cmp r4, r8
526: d015 beq.n 554 <_i2c_master_write_packet+0xc0>
if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
528: 8b6b ldrh r3, [r5, #26]
52a: 464a mov r2, r9
52c: 4213 tst r3, r2
52e: d01d beq.n 56c <_i2c_master_write_packet+0xd8>
_i2c_master_wait_for_sync(module);
530: 0030 movs r0, r6
532: 47d8 blx fp
i2c_module->DATA.reg = packet->data[buffer_counter++];
534: 687b ldr r3, [r7, #4]
536: 5d1a ldrb r2, [r3, r4]
538: 2328 movs r3, #40 ; 0x28
53a: 54ea strb r2, [r5, r3]
tmp_status = _i2c_master_wait_for_bus(module);
53c: 0030 movs r0, r6
53e: 47d0 blx sl
if (tmp_status != STATUS_OK) {
540: 2800 cmp r0, #0
542: d106 bne.n 552 <_i2c_master_write_packet+0xbe>
if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
544: 8b6b ldrh r3, [r5, #26]
546: 3401 adds r4, #1
548: 075b lsls r3, r3, #29
54a: d5eb bpl.n 524 <_i2c_master_write_packet+0x90>
tmp_status = STATUS_ERR_OVERFLOW;
54c: 231e movs r3, #30
54e: 9301 str r3, [sp, #4]
550: e000 b.n 554 <_i2c_master_write_packet+0xc0>
tmp_status = _i2c_master_wait_for_bus(module);
552: 9001 str r0, [sp, #4]
if (module->send_stop) {
554: 7ab3 ldrb r3, [r6, #10]
556: 2b00 cmp r3, #0
558: d0c2 beq.n 4e0 <_i2c_master_write_packet+0x4c>
_i2c_master_wait_for_sync(module);
55a: 0030 movs r0, r6
55c: 4b05 ldr r3, [pc, #20] ; (574 <_i2c_master_write_packet+0xe0>)
55e: 4798 blx r3
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
560: 686a ldr r2, [r5, #4]
562: 23c0 movs r3, #192 ; 0xc0
564: 029b lsls r3, r3, #10
566: 4313 orrs r3, r2
568: 606b str r3, [r5, #4]
56a: e7b9 b.n 4e0 <_i2c_master_write_packet+0x4c>
return STATUS_ERR_PACKET_COLLISION;
56c: 2341 movs r3, #65 ; 0x41
56e: 9301 str r3, [sp, #4]
570: e7b6 b.n 4e0 <_i2c_master_write_packet+0x4c>
572: 46c0 nop ; (mov r8, r8)
574: 00000115 .word 0x00000115
578: fffbffff .word 0xfffbffff
57c: 00000449 .word 0x00000449
580: 00000475 .word 0x00000475
584: 00000419 .word 0x00000419
00000588 <i2c_master_write_packet_wait>:
* last data sent
*/
enum status_code i2c_master_write_packet_wait(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet)
{
588: b510 push {r4, lr}
Assert(module->hw);
Assert(packet);
#if I2C_MASTER_CALLBACK_MODE == true
/* Check if the I2C module is busy with a job */
if (module->buffer_remaining > 0) {
58a: 8b83 ldrh r3, [r0, #28]
58c: b29b uxth r3, r3
return STATUS_BUSY;
58e: 2205 movs r2, #5
if (module->buffer_remaining > 0) {
590: 2b00 cmp r3, #0
592: d001 beq.n 598 <i2c_master_write_packet_wait+0x10>
module->send_stop = true;
module->send_nack = true;
return _i2c_master_write_packet(module, packet);
}
594: 0010 movs r0, r2
596: bd10 pop {r4, pc}
module->send_stop = true;
598: 3301 adds r3, #1
59a: 7283 strb r3, [r0, #10]
module->send_nack = true;
59c: 72c3 strb r3, [r0, #11]
return _i2c_master_write_packet(module, packet);
59e: 4b02 ldr r3, [pc, #8] ; (5a8 <i2c_master_write_packet_wait+0x20>)
5a0: 4798 blx r3
5a2: 0002 movs r2, r0
5a4: e7f6 b.n 594 <i2c_master_write_packet_wait+0xc>
5a6: 46c0 nop ; (mov r8, r8)
5a8: 00000495 .word 0x00000495
000005ac <i2c_master_write_packet_wait_no_stop>:
* more data
*/
enum status_code i2c_master_write_packet_wait_no_stop(
struct i2c_master_module *const module,
struct i2c_master_packet *const packet)
{
5ac: b510 push {r4, lr}
Assert(module->hw);
Assert(packet);
#if I2C_MASTER_CALLBACK_MODE == true
/* Check if the I2C module is busy with a job */
if (module->buffer_remaining > 0) {
5ae: 8b83 ldrh r3, [r0, #28]
5b0: b29b uxth r3, r3
return STATUS_BUSY;
5b2: 2205 movs r2, #5
if (module->buffer_remaining > 0) {
5b4: 2b00 cmp r3, #0
5b6: d001 beq.n 5bc <i2c_master_write_packet_wait_no_stop+0x10>
module->send_stop = false;
module->send_nack = true;
return _i2c_master_write_packet(module, packet);
}
5b8: 0010 movs r0, r2
5ba: bd10 pop {r4, pc}
module->send_stop = false;
5bc: 7283 strb r3, [r0, #10]
module->send_nack = true;
5be: 3301 adds r3, #1
5c0: 72c3 strb r3, [r0, #11]
return _i2c_master_write_packet(module, packet);
5c2: 4b02 ldr r3, [pc, #8] ; (5cc <i2c_master_write_packet_wait_no_stop+0x20>)
5c4: 4798 blx r3
5c6: 0002 movs r2, r0
5c8: e7f6 b.n 5b8 <i2c_master_write_packet_wait_no_stop+0xc>
5ca: 46c0 nop ; (mov r8, r8)
5cc: 00000495 .word 0x00000495
000005d0 <_i2c_master_wait_for_sync>:
{
/* Sanity check */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_hw = &(module->hw->I2CM);
5d0: 6801 ldr r1, [r0, #0]
#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1)
return (i2c_hw->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY);
#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2)
return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
5d2: 2207 movs r2, #7
5d4: 69cb ldr r3, [r1, #28]
const struct i2c_master_module *const module)
{
/* Sanity check */
Assert(module);
while (i2c_master_is_syncing(module)) {
5d6: 421a tst r2, r3
5d8: d1fc bne.n 5d4 <_i2c_master_wait_for_sync+0x4>
/* Wait for I2C module to sync. */
}
}
5da: 4770 bx lr
000005dc <_i2c_master_read>:
*
* \param[in,out] module Pointer to software module structure
*/
static void _i2c_master_read(
struct i2c_master_module *const module)
{
5dc: b570 push {r4, r5, r6, lr}
5de: 0004 movs r4, r0
/* Sanity check arguments. */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
5e0: 6806 ldr r6, [r0, #0]
bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
5e2: 6832 ldr r2, [r6, #0]
/* Find index to save next value in buffer */
uint16_t buffer_index = module->buffer_length;
5e4: 8b45 ldrh r5, [r0, #26]
buffer_index -= module->buffer_remaining;
5e6: 8b83 ldrh r3, [r0, #28]
5e8: 1aed subs r5, r5, r3
5ea: b2ad uxth r5, r5
module->buffer_remaining--;
5ec: 8b83 ldrh r3, [r0, #28]
5ee: 3b01 subs r3, #1
5f0: b29b uxth r3, r3
5f2: 8383 strh r3, [r0, #28]
if (sclsm_flag) {
5f4: 0113 lsls r3, r2, #4
5f6: d51d bpl.n 634 <_i2c_master_read+0x58>
if (module->send_nack && module->buffer_remaining == 1) {
5f8: 7ac3 ldrb r3, [r0, #11]
5fa: 2b00 cmp r3, #0
5fc: d003 beq.n 606 <_i2c_master_read+0x2a>
5fe: 8b83 ldrh r3, [r0, #28]
600: b29b uxth r3, r3
602: 2b01 cmp r3, #1
604: d010 beq.n 628 <_i2c_master_read+0x4c>
/* Set action to NACK. */
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
}
}
if (module->buffer_remaining == 0) {
606: 8ba3 ldrh r3, [r4, #28]
608: b29b uxth r3, r3
60a: 2b00 cmp r3, #0
60c: d102 bne.n 614 <_i2c_master_read+0x38>
if (module->send_stop) {
60e: 7aa3 ldrb r3, [r4, #10]
610: 2b00 cmp r3, #0
612: d11c bne.n 64e <_i2c_master_read+0x72>
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
}
}
/* Read byte from slave and put in buffer */
_i2c_master_wait_for_sync(module);
614: 0020 movs r0, r4
616: 4b12 ldr r3, [pc, #72] ; (660 <_i2c_master_read+0x84>)
618: 4798 blx r3
module->buffer[buffer_index] = i2c_module->DATA.reg;
61a: 6a23 ldr r3, [r4, #32]
61c: 195d adds r5, r3, r5
61e: 2328 movs r3, #40 ; 0x28
620: 5cf3 ldrb r3, [r6, r3]
622: b2db uxtb r3, r3
624: 702b strb r3, [r5, #0]
}
626: bd70 pop {r4, r5, r6, pc}
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
628: 6872 ldr r2, [r6, #4]
62a: 2380 movs r3, #128 ; 0x80
62c: 02db lsls r3, r3, #11
62e: 4313 orrs r3, r2
630: 6073 str r3, [r6, #4]
632: e7e8 b.n 606 <_i2c_master_read+0x2a>
if (module->send_nack && module->buffer_remaining == 0) {
634: 7ac3 ldrb r3, [r0, #11]
636: 2b00 cmp r3, #0
638: d0e5 beq.n 606 <_i2c_master_read+0x2a>
63a: 8b83 ldrh r3, [r0, #28]
63c: b29b uxth r3, r3
63e: 2b00 cmp r3, #0
640: d1e1 bne.n 606 <_i2c_master_read+0x2a>
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
642: 6872 ldr r2, [r6, #4]
644: 2380 movs r3, #128 ; 0x80
646: 02db lsls r3, r3, #11
648: 4313 orrs r3, r2
64a: 6073 str r3, [r6, #4]
64c: e7db b.n 606 <_i2c_master_read+0x2a>
_i2c_master_wait_for_sync(module);
64e: 0020 movs r0, r4
650: 4b03 ldr r3, [pc, #12] ; (660 <_i2c_master_read+0x84>)
652: 4798 blx r3
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
654: 6872 ldr r2, [r6, #4]
656: 23c0 movs r3, #192 ; 0xc0
658: 029b lsls r3, r3, #10
65a: 4313 orrs r3, r2
65c: 6073 str r3, [r6, #4]
65e: e7d9 b.n 614 <_i2c_master_read+0x38>
660: 000005d1 .word 0x000005d1
00000664 <_i2c_master_write>:
* Write next data. Used by interrupt handler to send next data byte to slave.
*
* \param[in,out] module Pointer to software module structure
*/
static void _i2c_master_write(struct i2c_master_module *const module)
{
664: b570 push {r4, r5, r6, lr}
666: 0004 movs r4, r0
/* Sanity check arguments. */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
668: 6805 ldr r5, [r0, #0]
/* Check for ack from slave */
if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
66a: 8b6b ldrh r3, [r5, #26]
66c: 075b lsls r3, r3, #29
66e: d503 bpl.n 678 <_i2c_master_write+0x14>
{
/* Set status */
module->status = STATUS_ERR_OVERFLOW;
670: 221e movs r2, #30
672: 2325 movs r3, #37 ; 0x25
674: 54c2 strb r2, [r0, r3]
module->buffer_remaining--;
/* Write byte from buffer to slave */
_i2c_master_wait_for_sync(module);
i2c_module->DATA.reg = module->buffer[buffer_index];
}
676: bd70 pop {r4, r5, r6, pc}
uint16_t buffer_index = module->buffer_length;
678: 8b46 ldrh r6, [r0, #26]
buffer_index -= module->buffer_remaining;
67a: 8b83 ldrh r3, [r0, #28]
67c: 1af6 subs r6, r6, r3
67e: b2b6 uxth r6, r6
module->buffer_remaining--;
680: 8b83 ldrh r3, [r0, #28]
682: 3b01 subs r3, #1
684: b29b uxth r3, r3
686: 8383 strh r3, [r0, #28]
_i2c_master_wait_for_sync(module);
688: 4b04 ldr r3, [pc, #16] ; (69c <_i2c_master_write+0x38>)
68a: 4798 blx r3
i2c_module->DATA.reg = module->buffer[buffer_index];
68c: 6a23 ldr r3, [r4, #32]
68e: 199e adds r6, r3, r6
690: 7833 ldrb r3, [r6, #0]
692: b2db uxtb r3, r3
694: 2228 movs r2, #40 ; 0x28
696: 54ab strb r3, [r5, r2]
698: e7ed b.n 676 <_i2c_master_write+0x12>
69a: 46c0 nop ; (mov r8, r8)
69c: 000005d1 .word 0x000005d1
000006a0 <_i2c_master_interrupt_handler>:
*
* \param[in] instance SERCOM instance that triggered the interrupt
*/
void _i2c_master_interrupt_handler(
uint8_t instance)
{
6a0: b570 push {r4, r5, r6, lr}
/* Get software module for callback handling */
struct i2c_master_module *module =
6a2: 0080 lsls r0, r0, #2
6a4: 4b75 ldr r3, [pc, #468] ; (87c <_i2c_master_interrupt_handler+0x1dc>)
6a6: 58c4 ldr r4, [r0, r3]
(struct i2c_master_module*)_sercom_instances[instance];
Assert(module);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
6a8: 6825 ldr r5, [r4, #0]
bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
6aa: 682b ldr r3, [r5, #0]
6ac: 011b lsls r3, r3, #4
6ae: 0fda lsrs r2, r3, #31
/* Combine callback registered and enabled masks */
uint8_t callback_mask = module->enabled_callback;
6b0: 7e63 ldrb r3, [r4, #25]
callback_mask &= module->registered_callback;
6b2: 7e26 ldrb r6, [r4, #24]
6b4: 401e ands r6, r3
/* Check if the module should respond to address ack */
if ((module->buffer_length <= 0) && (module->buffer_remaining > 0)) {
6b6: 8b63 ldrh r3, [r4, #26]
6b8: b29b uxth r3, r3
6ba: 2b00 cmp r3, #0
6bc: d103 bne.n 6c6 <_i2c_master_interrupt_handler+0x26>
6be: 8ba3 ldrh r3, [r4, #28]
6c0: b29b uxth r3, r3
6c2: 2b00 cmp r3, #0
6c4: d123 bne.n 70e <_i2c_master_interrupt_handler+0x6e>
/* Call function for address response */
_i2c_master_async_address_response(module);
/* Check if buffer write is done */
} else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
6c6: 8b63 ldrh r3, [r4, #26]
6c8: b29b uxth r3, r3
6ca: 2b00 cmp r3, #0
6cc: d008 beq.n 6e0 <_i2c_master_interrupt_handler+0x40>
6ce: 8ba3 ldrh r3, [r4, #28]
6d0: b29b uxth r3, r3
6d2: 2b00 cmp r3, #0
6d4: d104 bne.n 6e0 <_i2c_master_interrupt_handler+0x40>
(module->status == STATUS_BUSY) &&
6d6: 3325 adds r3, #37 ; 0x25
6d8: 5ce3 ldrb r3, [r4, r3]
} else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
6da: 2b05 cmp r3, #5
6dc: d100 bne.n 6e0 <_i2c_master_interrupt_handler+0x40>
6de: e06d b.n 7bc <_i2c_master_interrupt_handler+0x11c>
if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) {
module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
}
/* Continue buffer write/read */
} else if ((module->buffer_length > 0) && (module->buffer_remaining > 0)){
6e0: 8b63 ldrh r3, [r4, #26]
6e2: b29b uxth r3, r3
6e4: 2b00 cmp r3, #0
6e6: d024 beq.n 732 <_i2c_master_interrupt_handler+0x92>
6e8: 8ba3 ldrh r3, [r4, #28]
6ea: b29b uxth r3, r3
6ec: 2b00 cmp r3, #0
6ee: d020 beq.n 732 <_i2c_master_interrupt_handler+0x92>
/* Check that bus ownership is not lost */
if ((!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) &&
6f0: 8b6b ldrh r3, [r5, #26]
6f2: 069b lsls r3, r3, #26
6f4: d500 bpl.n 6f8 <_i2c_master_interrupt_handler+0x58>
6f6: e081 b.n 7fc <_i2c_master_interrupt_handler+0x15c>
6f8: 2a00 cmp r2, #0
6fa: d004 beq.n 706 <_i2c_master_interrupt_handler+0x66>
(!(sclsm_flag && (module->buffer_remaining == 1)))) {
6fc: 8ba3 ldrh r3, [r4, #28]
6fe: b29b uxth r3, r3
700: 2b01 cmp r3, #1
702: d100 bne.n 706 <_i2c_master_interrupt_handler+0x66>
704: e07a b.n 7fc <_i2c_master_interrupt_handler+0x15c>
module->status = STATUS_ERR_PACKET_COLLISION;
706: 2241 movs r2, #65 ; 0x41
708: 2325 movs r3, #37 ; 0x25
70a: 54e2 strb r2, [r4, r3]
70c: e011 b.n 732 <_i2c_master_interrupt_handler+0x92>
if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB)
70e: 7e2b ldrb r3, [r5, #24]
710: 07db lsls r3, r3, #31
712: d507 bpl.n 724 <_i2c_master_interrupt_handler+0x84>
i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
714: 2301 movs r3, #1
716: 762b strb r3, [r5, #24]
if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
718: 8b6b ldrh r3, [r5, #26]
71a: 079b lsls r3, r3, #30
71c: d52e bpl.n 77c <_i2c_master_interrupt_handler+0xdc>
module->status = STATUS_ERR_PACKET_COLLISION;
71e: 2241 movs r2, #65 ; 0x41
720: 2325 movs r3, #37 ; 0x25
722: 54e2 strb r2, [r4, r3]
module->buffer_length = module->buffer_remaining;
724: 8ba3 ldrh r3, [r4, #28]
726: b29b uxth r3, r3
728: 8363 strh r3, [r4, #26]
if (module->status == STATUS_BUSY) {
72a: 2325 movs r3, #37 ; 0x25
72c: 5ce3 ldrb r3, [r4, r3]
72e: 2b05 cmp r3, #5
730: d038 beq.n 7a4 <_i2c_master_interrupt_handler+0x104>
_i2c_master_read(module);
}
}
/* Check if read buffer transfer is complete */
if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
732: 8b63 ldrh r3, [r4, #26]
734: b29b uxth r3, r3
736: 2b00 cmp r3, #0
738: d007 beq.n 74a <_i2c_master_interrupt_handler+0xaa>
73a: 8ba3 ldrh r3, [r4, #28]
73c: b29b uxth r3, r3
73e: 2b00 cmp r3, #0
740: d103 bne.n 74a <_i2c_master_interrupt_handler+0xaa>
(module->status == STATUS_BUSY) &&
742: 3325 adds r3, #37 ; 0x25
744: 5ce3 ldrb r3, [r4, r3]
if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
746: 2b05 cmp r3, #5
748: d064 beq.n 814 <_i2c_master_interrupt_handler+0x174>
module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
}
}
/* Check for error */
if ((module->status != STATUS_BUSY) && (module->status != STATUS_OK)) {
74a: 2325 movs r3, #37 ; 0x25
74c: 5ce3 ldrb r3, [r4, r3]
74e: 2b05 cmp r3, #5
750: d013 beq.n 77a <_i2c_master_interrupt_handler+0xda>
752: 2325 movs r3, #37 ; 0x25
754: 5ce3 ldrb r3, [r4, r3]
756: 2b00 cmp r3, #0
758: d00f beq.n 77a <_i2c_master_interrupt_handler+0xda>
/* Stop packet operation */
i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB |
75a: 2303 movs r3, #3
75c: 752b strb r3, [r5, #20]
SERCOM_I2CM_INTENCLR_SB;
module->buffer_length = 0;
75e: 2300 movs r3, #0
760: 8363 strh r3, [r4, #26]
module->buffer_remaining = 0;
762: 83a3 strh r3, [r4, #28]
/* Send nack and stop command unless arbitration is lost */
if ((module->status != STATUS_ERR_PACKET_COLLISION) &&
764: 3325 adds r3, #37 ; 0x25
766: 5ce3 ldrb r3, [r4, r3]
768: 2b41 cmp r3, #65 ; 0x41
76a: d003 beq.n 774 <_i2c_master_interrupt_handler+0xd4>
76c: 7aa3 ldrb r3, [r4, #10]
76e: 2b00 cmp r3, #0
770: d000 beq.n 774 <_i2c_master_interrupt_handler+0xd4>
772: e075 b.n 860 <_i2c_master_interrupt_handler+0x1c0>
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT |
SERCOM_I2CM_CTRLB_CMD(3);
}
/* Call error callback if enabled and registered */
if (callback_mask & (1 << I2C_MASTER_CALLBACK_ERROR)) {
774: 0773 lsls r3, r6, #29
776: d500 bpl.n 77a <_i2c_master_interrupt_handler+0xda>
778: e07b b.n 872 <_i2c_master_interrupt_handler+0x1d2>
module->callbacks[I2C_MASTER_CALLBACK_ERROR](module);
}
}
}
77a: bd70 pop {r4, r5, r6, pc}
else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
77c: 8b6b ldrh r3, [r5, #26]
77e: 075b lsls r3, r3, #29
780: d5d0 bpl.n 724 <_i2c_master_interrupt_handler+0x84>
module->status = STATUS_ERR_BAD_ADDRESS;
782: 2218 movs r2, #24
784: 2325 movs r3, #37 ; 0x25
786: 54e2 strb r2, [r4, r3]
module->buffer_remaining = 0;
788: 2300 movs r3, #0
78a: 83a3 strh r3, [r4, #28]
if (module->send_stop) {
78c: 7aa3 ldrb r3, [r4, #10]
78e: 2b00 cmp r3, #0
790: d0c8 beq.n 724 <_i2c_master_interrupt_handler+0x84>
_i2c_master_wait_for_sync(module);
792: 0020 movs r0, r4
794: 4b3a ldr r3, [pc, #232] ; (880 <_i2c_master_interrupt_handler+0x1e0>)
796: 4798 blx r3
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
798: 686a ldr r2, [r5, #4]
79a: 23c0 movs r3, #192 ; 0xc0
79c: 029b lsls r3, r3, #10
79e: 4313 orrs r3, r2
7a0: 606b str r3, [r5, #4]
7a2: e7bf b.n 724 <_i2c_master_interrupt_handler+0x84>
if (module->transfer_direction == I2C_TRANSFER_WRITE) {
7a4: 331f adds r3, #31
7a6: 5ce3 ldrb r3, [r4, r3]
7a8: 2b00 cmp r3, #0
7aa: d003 beq.n 7b4 <_i2c_master_interrupt_handler+0x114>
_i2c_master_read(module);
7ac: 0020 movs r0, r4
7ae: 4b35 ldr r3, [pc, #212] ; (884 <_i2c_master_interrupt_handler+0x1e4>)
7b0: 4798 blx r3
7b2: e7be b.n 732 <_i2c_master_interrupt_handler+0x92>
_i2c_master_write(module);
7b4: 0020 movs r0, r4
7b6: 4b34 ldr r3, [pc, #208] ; (888 <_i2c_master_interrupt_handler+0x1e8>)
7b8: 4798 blx r3
7ba: e7ba b.n 732 <_i2c_master_interrupt_handler+0x92>
(module->transfer_direction == I2C_TRANSFER_WRITE)) {
7bc: 331f adds r3, #31
7be: 5ce3 ldrb r3, [r4, r3]
(module->status == STATUS_BUSY) &&
7c0: 2b00 cmp r3, #0
7c2: d000 beq.n 7c6 <_i2c_master_interrupt_handler+0x126>
7c4: e78c b.n 6e0 <_i2c_master_interrupt_handler+0x40>
i2c_module->INTENCLR.reg =
7c6: 3303 adds r3, #3
7c8: 752b strb r3, [r5, #20]
module->buffer_length = 0;
7ca: 2300 movs r3, #0
7cc: 8363 strh r3, [r4, #26]
module->status = STATUS_OK;
7ce: 3325 adds r3, #37 ; 0x25
7d0: 2200 movs r2, #0
7d2: 54e2 strb r2, [r4, r3]
if (module->send_stop) {
7d4: 7aa3 ldrb r3, [r4, #10]
7d6: 2b00 cmp r3, #0
7d8: d107 bne.n 7ea <_i2c_master_interrupt_handler+0x14a>
i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
7da: 2301 movs r3, #1
7dc: 762b strb r3, [r5, #24]
if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) {
7de: 07f3 lsls r3, r6, #31
7e0: d5a7 bpl.n 732 <_i2c_master_interrupt_handler+0x92>
module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
7e2: 68e3 ldr r3, [r4, #12]
7e4: 0020 movs r0, r4
7e6: 4798 blx r3
7e8: e7a3 b.n 732 <_i2c_master_interrupt_handler+0x92>
_i2c_master_wait_for_sync(module);
7ea: 0020 movs r0, r4
7ec: 4b24 ldr r3, [pc, #144] ; (880 <_i2c_master_interrupt_handler+0x1e0>)
7ee: 4798 blx r3
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
7f0: 686a ldr r2, [r5, #4]
7f2: 23c0 movs r3, #192 ; 0xc0
7f4: 029b lsls r3, r3, #10
7f6: 4313 orrs r3, r2
7f8: 606b str r3, [r5, #4]
7fa: e7f0 b.n 7de <_i2c_master_interrupt_handler+0x13e>
} else if (module->transfer_direction == I2C_TRANSFER_WRITE) {
7fc: 2324 movs r3, #36 ; 0x24
7fe: 5ce3 ldrb r3, [r4, r3]
800: 2b00 cmp r3, #0
802: d103 bne.n 80c <_i2c_master_interrupt_handler+0x16c>
_i2c_master_write(module);
804: 0020 movs r0, r4
806: 4b20 ldr r3, [pc, #128] ; (888 <_i2c_master_interrupt_handler+0x1e8>)
808: 4798 blx r3
80a: e792 b.n 732 <_i2c_master_interrupt_handler+0x92>
_i2c_master_read(module);
80c: 0020 movs r0, r4
80e: 4b1d ldr r3, [pc, #116] ; (884 <_i2c_master_interrupt_handler+0x1e4>)
810: 4798 blx r3
812: e78e b.n 732 <_i2c_master_interrupt_handler+0x92>
(module->transfer_direction == I2C_TRANSFER_READ)) {
814: 331f adds r3, #31
816: 5ce3 ldrb r3, [r4, r3]
(module->status == STATUS_BUSY) &&
818: 2b01 cmp r3, #1
81a: d196 bne.n 74a <_i2c_master_interrupt_handler+0xaa>
if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) {
81c: 7e2b ldrb r3, [r5, #24]
81e: 079b lsls r3, r3, #30
820: d501 bpl.n 826 <_i2c_master_interrupt_handler+0x186>
i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
822: 2302 movs r3, #2
824: 762b strb r3, [r5, #24]
i2c_module->INTENCLR.reg =
826: 2303 movs r3, #3
828: 752b strb r3, [r5, #20]
module->buffer_length = 0;
82a: 2300 movs r3, #0
82c: 8363 strh r3, [r4, #26]
module->status = STATUS_OK;
82e: 3325 adds r3, #37 ; 0x25
830: 2200 movs r2, #0
832: 54e2 strb r2, [r4, r3]
if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE))
834: 07b3 lsls r3, r6, #30
836: d503 bpl.n 840 <_i2c_master_interrupt_handler+0x1a0>
&& (module->transfer_direction == I2C_TRANSFER_READ)) {
838: 2324 movs r3, #36 ; 0x24
83a: 5ce3 ldrb r3, [r4, r3]
83c: 2b01 cmp r3, #1
83e: d00b beq.n 858 <_i2c_master_interrupt_handler+0x1b8>
} else if ((callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE))
840: 07f3 lsls r3, r6, #31
842: d400 bmi.n 846 <_i2c_master_interrupt_handler+0x1a6>
844: e781 b.n 74a <_i2c_master_interrupt_handler+0xaa>
&& (module->transfer_direction == I2C_TRANSFER_WRITE)) {
846: 2324 movs r3, #36 ; 0x24
848: 5ce3 ldrb r3, [r4, r3]
84a: 2b00 cmp r3, #0
84c: d000 beq.n 850 <_i2c_master_interrupt_handler+0x1b0>
84e: e77c b.n 74a <_i2c_master_interrupt_handler+0xaa>
module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
850: 68e3 ldr r3, [r4, #12]
852: 0020 movs r0, r4
854: 4798 blx r3
856: e778 b.n 74a <_i2c_master_interrupt_handler+0xaa>
module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module);
858: 6923 ldr r3, [r4, #16]
85a: 0020 movs r0, r4
85c: 4798 blx r3
85e: e774 b.n 74a <_i2c_master_interrupt_handler+0xaa>
_i2c_master_wait_for_sync(module);
860: 0020 movs r0, r4
862: 4b07 ldr r3, [pc, #28] ; (880 <_i2c_master_interrupt_handler+0x1e0>)
864: 4798 blx r3
i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT |
866: 686a ldr r2, [r5, #4]
868: 23e0 movs r3, #224 ; 0xe0
86a: 02db lsls r3, r3, #11
86c: 4313 orrs r3, r2
86e: 606b str r3, [r5, #4]
870: e780 b.n 774 <_i2c_master_interrupt_handler+0xd4>
module->callbacks[I2C_MASTER_CALLBACK_ERROR](module);
872: 6963 ldr r3, [r4, #20]
874: 0020 movs r0, r4
876: 4798 blx r3
}
878: e77f b.n 77a <_i2c_master_interrupt_handler+0xda>
87a: 46c0 nop ; (mov r8, r8)
87c: 20000244 .word 0x20000244
880: 000005d1 .word 0x000005d1
884: 000005dd .word 0x000005dd
888: 00000665 .word 0x00000665
0000088c <_read>:
int __attribute__((weak))
_read (int file, char * ptr, int len); // Remove GCC compiler warning
int __attribute__((weak))
_read (int file, char * ptr, int len)
{
88c: b5f0 push {r4, r5, r6, r7, lr}
88e: 46c6 mov lr, r8
890: b500 push {lr}
892: 000c movs r4, r1
894: 4690 mov r8, r2
int nChars = 0;
if (file != 0) {
896: 2800 cmp r0, #0
898: d10f bne.n 8ba <_read+0x2e>
return -1;
}
for (; len > 0; --len) {
89a: 2a00 cmp r2, #0
89c: dd11 ble.n 8c2 <_read+0x36>
89e: 188f adds r7, r1, r2
ptr_get(stdio_base, ptr);
8a0: 4e09 ldr r6, [pc, #36] ; (8c8 <_read+0x3c>)
8a2: 4d0a ldr r5, [pc, #40] ; (8cc <_read+0x40>)
8a4: 6830 ldr r0, [r6, #0]
8a6: 0021 movs r1, r4
8a8: 682b ldr r3, [r5, #0]
8aa: 4798 blx r3
ptr++;
8ac: 3401 adds r4, #1
for (; len > 0; --len) {
8ae: 42bc cmp r4, r7
8b0: d1f8 bne.n 8a4 <_read+0x18>
nChars++;
}
return nChars;
}
8b2: 4640 mov r0, r8
8b4: bc04 pop {r2}
8b6: 4690 mov r8, r2
8b8: bdf0 pop {r4, r5, r6, r7, pc}
return -1;
8ba: 2301 movs r3, #1
8bc: 425b negs r3, r3
8be: 4698 mov r8, r3
8c0: e7f7 b.n 8b2 <_read+0x26>
for (; len > 0; --len) {
8c2: 4680 mov r8, r0
8c4: e7f5 b.n 8b2 <_read+0x26>
8c6: 46c0 nop ; (mov r8, r8)
8c8: 200000d8 .word 0x200000d8
8cc: 200000d0 .word 0x200000d0
000008d0 <_write>:
int __attribute__((weak))
_write (int file, char * ptr, int len);
int __attribute__((weak))
_write (int file, char * ptr, int len)
{
8d0: b5f0 push {r4, r5, r6, r7, lr}
8d2: 46c6 mov lr, r8
8d4: b500 push {lr}
8d6: 000e movs r6, r1
8d8: 0015 movs r5, r2
int nChars = 0;
if ((file != 1) && (file != 2) && (file!=3)) {
8da: 3801 subs r0, #1
8dc: 2802 cmp r0, #2
8de: d810 bhi.n 902 <_write+0x32>
return -1;
}
for (; len != 0; --len) {
8e0: 2a00 cmp r2, #0
8e2: d011 beq.n 908 <_write+0x38>
8e4: 2400 movs r4, #0
if (ptr_put(stdio_base, *ptr++) < 0) {
8e6: 4b0c ldr r3, [pc, #48] ; (918 <_write+0x48>)
8e8: 4698 mov r8, r3
8ea: 4f0c ldr r7, [pc, #48] ; (91c <_write+0x4c>)
8ec: 4643 mov r3, r8
8ee: 6818 ldr r0, [r3, #0]
8f0: 5d31 ldrb r1, [r6, r4]
8f2: 683b ldr r3, [r7, #0]
8f4: 4798 blx r3
8f6: 2800 cmp r0, #0
8f8: db08 blt.n 90c <_write+0x3c>
return -1;
}
++nChars;
8fa: 3401 adds r4, #1
for (; len != 0; --len) {
8fc: 42a5 cmp r5, r4
8fe: d1f5 bne.n 8ec <_write+0x1c>
900: e006 b.n 910 <_write+0x40>
return -1;
902: 2401 movs r4, #1
904: 4264 negs r4, r4
906: e003 b.n 910 <_write+0x40>
for (; len != 0; --len) {
908: 0014 movs r4, r2
90a: e001 b.n 910 <_write+0x40>
return -1;
90c: 2401 movs r4, #1
90e: 4264 negs r4, r4
}
return nChars;
}
910: 0020 movs r0, r4
912: bc04 pop {r2}
914: 4690 mov r8, r2
916: bdf0 pop {r4, r5, r6, r7, pc}
918: 200000d8 .word 0x200000d8
91c: 200000d4 .word 0x200000d4
00000920 <p_i2c_write_byte>:
volatile uint8_t i2c_master_buff[P_I2C_BUFFER_SIZE];
int ctr = 0;
int p_i2c_write_byte(i2c_device* dev, uint8_t byte, _Bool bShouldStop)
{
920: b570 push {r4, r5, r6, lr}
p_i2c_pkt.data[0] = 0x0;
922: 4b1b ldr r3, [pc, #108] ; (990 <p_i2c_write_byte+0x70>)
924: 2400 movs r4, #0
926: 685d ldr r5, [r3, #4]
928: 702c strb r4, [r5, #0]
p_i2c_pkt.data[0] = byte;
92a: 685c ldr r4, [r3, #4]
92c: 7021 strb r1, [r4, #0]
p_i2c_pkt.address = dev->addr;
92e: 7801 ldrb r1, [r0, #0]
930: 8019 strh r1, [r3, #0]
p_i2c_pkt.data_length = 1;
932: 2101 movs r1, #1
934: 8059 strh r1, [r3, #2]
if(bShouldStop)
936: 2a00 cmp r2, #0
938: d114 bne.n 964 <p_i2c_write_byte+0x44>
}
else
{
#warning add timeout handling
while(i2c_master_write_packet_wait_no_stop(&p_i2c_mod, &p_i2c_pkt) != STATUS_OK)
93a: 001d movs r5, r3
93c: 4c15 ldr r4, [pc, #84] ; (994 <p_i2c_write_byte+0x74>)
93e: 4e16 ldr r6, [pc, #88] ; (998 <p_i2c_write_byte+0x78>)
940: 0029 movs r1, r5
942: 0020 movs r0, r4
944: 47b0 blx r6
946: 2800 cmp r0, #0
948: d020 beq.n 98c <p_i2c_write_byte+0x6c>
{
if(ctr++ >= 2000)
94a: 4a14 ldr r2, [pc, #80] ; (99c <p_i2c_write_byte+0x7c>)
94c: 6813 ldr r3, [r2, #0]
94e: 1c59 adds r1, r3, #1
950: 6011 str r1, [r2, #0]
952: 4a13 ldr r2, [pc, #76] ; (9a0 <p_i2c_write_byte+0x80>)
954: 4293 cmp r3, r2
956: ddf3 ble.n 940 <p_i2c_write_byte+0x20>
{
ctr = 0;
958: 2200 movs r2, #0
95a: 4b10 ldr r3, [pc, #64] ; (99c <p_i2c_write_byte+0x7c>)
95c: 601a str r2, [r3, #0]
return -1;
95e: 2001 movs r0, #1
960: 4240 negs r0, r0
962: e013 b.n 98c <p_i2c_write_byte+0x6c>
while(i2c_master_write_packet_wait(&p_i2c_mod, &p_i2c_pkt) != STATUS_OK)
964: 4d0a ldr r5, [pc, #40] ; (990 <p_i2c_write_byte+0x70>)
966: 4c0b ldr r4, [pc, #44] ; (994 <p_i2c_write_byte+0x74>)
968: 4e0e ldr r6, [pc, #56] ; (9a4 <p_i2c_write_byte+0x84>)
96a: 0029 movs r1, r5
96c: 0020 movs r0, r4
96e: 47b0 blx r6
970: 2800 cmp r0, #0
972: d00b beq.n 98c <p_i2c_write_byte+0x6c>
if(ctr++ >= 2000)
974: 4a09 ldr r2, [pc, #36] ; (99c <p_i2c_write_byte+0x7c>)
976: 6813 ldr r3, [r2, #0]
978: 1c59 adds r1, r3, #1
97a: 6011 str r1, [r2, #0]
97c: 4a08 ldr r2, [pc, #32] ; (9a0 <p_i2c_write_byte+0x80>)
97e: 4293 cmp r3, r2
980: ddf3 ble.n 96a <p_i2c_write_byte+0x4a>
ctr = 0;
982: 2200 movs r2, #0
984: 4b05 ldr r3, [pc, #20] ; (99c <p_i2c_write_byte+0x7c>)
986: 601a str r2, [r3, #0]
return -1;
988: 2001 movs r0, #1
98a: 4240 negs r0, r0
}
}
}
return 0;
}
98c: bd70 pop {r4, r5, r6, pc}
98e: 46c0 nop ; (mov r8, r8)
990: 20000204 .word 0x20000204
994: 200001dc .word 0x200001dc
998: 000005ad .word 0x000005ad
99c: 20000084 .word 0x20000084
9a0: 000007cf .word 0x000007cf
9a4: 00000589 .word 0x00000589
000009a8 <p_i2c_master_bus_init>:
memcpy(dev->buffer, i2c_master_buff, numBytes);
}
void p_i2c_master_bus_init(void)
{
9a8: b530 push {r4, r5, lr}
9aa: b08f sub sp, #60 ; 0x3c
/*Sanity check argument */
Assert(config);
config->baud_rate = I2C_MASTER_BAUD_RATE_100KHZ;
#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ;
config->transfer_speed = I2C_MASTER_SPEED_STANDARD_AND_FAST;
9ac: ab01 add r3, sp, #4
9ae: 2200 movs r2, #0
9b0: 9203 str r2, [sp, #12]
#endif
config->generator_source = GCLK_GENERATOR_0;
9b2: 731a strb r2, [r3, #12]
config->run_in_standby = false;
9b4: 761a strb r2, [r3, #24]
config->start_hold_time = I2C_MASTER_START_HOLD_TIME_300NS_600NS;
9b6: 2180 movs r1, #128 ; 0x80
9b8: 0389 lsls r1, r1, #14
9ba: 9105 str r1, [sp, #20]
config->buffer_timeout = 65535;
9bc: 2101 movs r1, #1
9be: 4249 negs r1, r1
9c0: 82d9 strh r1, [r3, #22]
config->unknown_bus_state_timeout = 65535;
9c2: 8299 strh r1, [r3, #20]
config->pinmux_pad0 = PINMUX_DEFAULT;
config->pinmux_pad1 = PINMUX_DEFAULT;
config->scl_low_timeout = false;
9c4: 3125 adds r1, #37 ; 0x25
9c6: 545a strb r2, [r3, r1]
config->inactive_timeout = I2C_MASTER_INACTIVE_TIMEOUT_DISABLED;
9c8: 920b str r2, [sp, #44] ; 0x2c
#ifdef FEATURE_I2C_SCL_STRETCH_MODE
config->scl_stretch_only_after_ack_bit = false;
9ca: 3108 adds r1, #8
9cc: 545a strb r2, [r3, r1]
#endif
#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
config->slave_scl_low_extend_timeout = false;
9ce: 3101 adds r1, #1
9d0: 545a strb r2, [r3, r1]
config->master_scl_low_extend_timeout = false;
9d2: 3101 adds r1, #1
9d4: 545a strb r2, [r3, r1]
#endif
/* The typical value is 215ns */
config->sda_scl_rise_time_ns = 215;
9d6: 31a9 adds r1, #169 ; 0xa9
9d8: 8619 strh r1, [r3, #48] ; 0x30
struct i2c_master_config i2c_conf;
i2c_master_get_config_defaults(&i2c_conf);
i2c_conf.pinmux_pad0 = P_I2C_PINMUX_PAD0;
9da: 491b ldr r1, [pc, #108] ; (a48 <p_i2c_master_bus_init+0xa0>)
9dc: 9108 str r1, [sp, #32]
i2c_conf.pinmux_pad1 = P_I2C_PINMUX_PAD1;
9de: 491b ldr r1, [pc, #108] ; (a4c <p_i2c_master_bus_init+0xa4>)
9e0: 9109 str r1, [sp, #36] ; 0x24
i2c_conf.baud_rate = P_I2C_CLOCK_SPEED;
9e2: 21c8 movs r1, #200 ; 0xc8
9e4: 0049 lsls r1, r1, #1
9e6: 9101 str r1, [sp, #4]
i2c_conf.baud_rate_high_speed = false;
9e8: 9202 str r2, [sp, #8]
i2c_conf.run_in_standby = false;
i2c_conf.generator_source = GCLK_GENERATOR_0;
// packet init
p_i2c_pkt.data = i2c_master_buff;
9ea: 4b19 ldr r3, [pc, #100] ; (a50 <p_i2c_master_bus_init+0xa8>)
9ec: 4919 ldr r1, [pc, #100] ; (a54 <p_i2c_master_bus_init+0xac>)
9ee: 6059 str r1, [r3, #4]
p_i2c_pkt.data_length = 1;
9f0: 2101 movs r1, #1
9f2: 8059 strh r1, [r3, #2]
p_i2c_pkt.ten_bit_address = false;
9f4: 721a strb r2, [r3, #8]
while(i2c_master_init(&p_i2c_mod, P_I2C_SERCOM, &i2c_conf) != STATUS_OK);
9f6: 4d18 ldr r5, [pc, #96] ; (a58 <p_i2c_master_bus_init+0xb0>)
9f8: 4c18 ldr r4, [pc, #96] ; (a5c <p_i2c_master_bus_init+0xb4>)
9fa: aa01 add r2, sp, #4
9fc: 4918 ldr r1, [pc, #96] ; (a60 <p_i2c_master_bus_init+0xb8>)
9fe: 0028 movs r0, r5
a00: 47a0 blx r4
a02: 2800 cmp r0, #0
a04: d1f9 bne.n 9fa <p_i2c_master_bus_init+0x52>
{
/* Sanity check of arguments */
Assert(module);
Assert(module->hw);
SercomI2cm *const i2c_module = &(module->hw->I2CM);
a06: 4b14 ldr r3, [pc, #80] ; (a58 <p_i2c_master_bus_init+0xb0>)
a08: 681c ldr r4, [r3, #0]
return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
a0a: 2207 movs r2, #7
a0c: 69e3 ldr r3, [r4, #28]
while (i2c_master_is_syncing(module)) {
a0e: 421a tst r2, r3
a10: d1fc bne.n a0c <p_i2c_master_bus_init+0x64>
/* Wait for module to sync */
_i2c_master_wait_for_sync(module);
/* Enable module */
i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
a12: 6823 ldr r3, [r4, #0]
a14: 2202 movs r2, #2
a16: 4313 orrs r3, r2
a18: 6023 str r3, [r4, #0]
#if I2C_MASTER_CALLBACK_MODE == true
/* Enable module interrupts */
system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
a1a: 4d0f ldr r5, [pc, #60] ; (a58 <p_i2c_master_bus_init+0xb0>)
a1c: 6828 ldr r0, [r5, #0]
a1e: 4b11 ldr r3, [pc, #68] ; (a64 <p_i2c_master_bus_init+0xbc>)
a20: 4798 blx r3
* \param[in] vector Interrupt vector to enable
*/
static inline void system_interrupt_enable(
const enum system_interrupt_vector vector)
{
NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
a22: 231f movs r3, #31
a24: 4018 ands r0, r3
a26: 3b1e subs r3, #30
a28: 4083 lsls r3, r0
a2a: 4a0f ldr r2, [pc, #60] ; (a68 <p_i2c_master_bus_init+0xc0>)
a2c: 6013 str r3, [r2, #0]
#endif
/* Start timeout if bus state is unknown */
while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) {
timeout_counter++;
if(timeout_counter >= (module->unknown_bus_state_timeout)) {
a2e: 88e8 ldrh r0, [r5, #6]
uint32_t timeout_counter = 0;
a30: 2300 movs r3, #0
while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) {
a32: 2110 movs r1, #16
a34: 8b62 ldrh r2, [r4, #26]
a36: 420a tst r2, r1
a38: d104 bne.n a44 <p_i2c_master_bus_init+0x9c>
timeout_counter++;
a3a: 3301 adds r3, #1
if(timeout_counter >= (module->unknown_bus_state_timeout)) {
a3c: 4283 cmp r3, r0
a3e: d3f9 bcc.n a34 <p_i2c_master_bus_init+0x8c>
/* Timeout, force bus state to idle */
i2c_module->STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(1);
a40: 2310 movs r3, #16
a42: 8363 strh r3, [r4, #26]
i2c_master_enable(&p_i2c_mod);
}
a44: b00f add sp, #60 ; 0x3c
a46: bd30 pop {r4, r5, pc}
a48: 00080003 .word 0x00080003
a4c: 00090003 .word 0x00090003
a50: 20000204 .word 0x20000204
a54: 200000dc .word 0x200000dc
a58: 200001dc .word 0x200001dc
a5c: 00000121 .word 0x00000121
a60: 42001000 .word 0x42001000
a64: 000014c9 .word 0x000014c9
a68: e000e100 .word 0xe000e100
00000a6c <usart_serial_getchar>:
* \param[out] c Destination for the read character.
*/
static inline void usart_serial_getchar(
struct usart_module *const module,
uint8_t *c)
{
a6c: b570 push {r4, r5, r6, lr}
a6e: b082 sub sp, #8
a70: 0005 movs r5, r0
a72: 000e movs r6, r1
uint16_t temp = 0;
a74: 2200 movs r2, #0
a76: 466b mov r3, sp
a78: 80da strh r2, [r3, #6]
while(STATUS_OK != usart_read_wait(module, &temp));
a7a: 4c06 ldr r4, [pc, #24] ; (a94 <usart_serial_getchar+0x28>)
a7c: 466b mov r3, sp
a7e: 1d99 adds r1, r3, #6
a80: 0028 movs r0, r5
a82: 47a0 blx r4
a84: 2800 cmp r0, #0
a86: d1f9 bne.n a7c <usart_serial_getchar+0x10>
*c = temp;
a88: 466b mov r3, sp
a8a: 3306 adds r3, #6
a8c: 881b ldrh r3, [r3, #0]
a8e: 7033 strb r3, [r6, #0]
}
a90: b002 add sp, #8
a92: bd70 pop {r4, r5, r6, pc}
a94: 00000f17 .word 0x00000f17
00000a98 <usart_serial_putchar>:
{
a98: b570 push {r4, r5, r6, lr}
a9a: 0005 movs r5, r0
while(STATUS_OK !=usart_write_wait(module, c));
a9c: b28c uxth r4, r1
a9e: 4e03 ldr r6, [pc, #12] ; (aac <usart_serial_putchar+0x14>)
aa0: 0021 movs r1, r4
aa2: 0028 movs r0, r5
aa4: 47b0 blx r6
aa6: 2800 cmp r0, #0
aa8: d1fa bne.n aa0 <usart_serial_putchar+0x8>
}
aaa: bd70 pop {r4, r5, r6, pc}
aac: 00000ef1 .word 0x00000ef1
00000ab0 <p_usart_init>:
#include "p_usart.h"
struct usart_module du_mod;
void p_usart_init(void)
{
ab0: b5f0 push {r4, r5, r6, r7, lr}
ab2: b091 sub sp, #68 ; 0x44
{
/* Sanity check arguments */
Assert(config);
/* Set default config in the config struct */
config->data_order = USART_DATAORDER_LSB;
ab4: 2380 movs r3, #128 ; 0x80
ab6: 05db lsls r3, r3, #23
ab8: 9300 str r3, [sp, #0]
config->transfer_mode = USART_TRANSFER_ASYNCHRONOUSLY;
aba: 2300 movs r3, #0
abc: 9301 str r3, [sp, #4]
config->parity = USART_PARITY_NONE;
abe: 22ff movs r2, #255 ; 0xff
ac0: 4669 mov r1, sp
ac2: 810a strh r2, [r1, #8]
config->stopbits = USART_STOPBITS_1;
ac4: 2200 movs r2, #0
ac6: 728b strb r3, [r1, #10]
config->character_size = USART_CHARACTER_SIZE_8BIT;
ac8: 72cb strb r3, [r1, #11]
config->baudrate = 9600;
config->receiver_enable = true;
aca: 2401 movs r4, #1
acc: 2124 movs r1, #36 ; 0x24
ace: 4668 mov r0, sp
ad0: 5444 strb r4, [r0, r1]
config->transmitter_enable = true;
ad2: 3101 adds r1, #1
ad4: 5444 strb r4, [r0, r1]
config->clock_polarity_inverted = false;
ad6: 3101 adds r1, #1
ad8: 5443 strb r3, [r0, r1]
config->use_external_clock = false;
ada: 3101 adds r1, #1
adc: 5443 strb r3, [r0, r1]
config->ext_clock_freq = 0;
ade: 930a str r3, [sp, #40] ; 0x28
config->mux_setting = USART_RX_1_TX_2_XCK_3;
config->run_in_standby = false;
ae0: 3105 adds r1, #5
ae2: 5443 strb r3, [r0, r1]
config->generator_source = GCLK_GENERATOR_0;
ae4: 3101 adds r1, #1
ae6: 5443 strb r3, [r0, r1]
config->pinmux_pad0 = PINMUX_DEFAULT;
config->pinmux_pad1 = PINMUX_DEFAULT;
config->pinmux_pad2 = PINMUX_DEFAULT;
config->pinmux_pad3 = PINMUX_DEFAULT;
#ifdef FEATURE_USART_OVER_SAMPLE
config->sample_adjustment = USART_SAMPLE_ADJUSTMENT_7_8_9;
ae8: 9305 str r3, [sp, #20]
config->sample_rate = USART_SAMPLE_RATE_16X_ARITHMETIC;
aea: 8203 strh r3, [r0, #16]
#endif
#ifdef FEATURE_USART_LIN_SLAVE
config->lin_slave_enable = false;
aec: 76c3 strb r3, [r0, #27]
config->lin_header_delay = LIN_MASTER_HEADER_DELAY_0;
config->lin_break_length = LIN_MASTER_BREAK_LENGTH_13_BIT;
#endif
#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
config->immediate_buffer_overflow_notification = false;
aee: 7602 strb r2, [r0, #24]
#endif
#ifdef FEATURE_USART_START_FRAME_DECTION
config->start_frame_detection_enable = false;
af0: 7702 strb r2, [r0, #28]
#endif
#ifdef FEATURE_USART_IRDA
config->encoding_format_enable = false;
af2: 7642 strb r2, [r0, #25]
config->receive_pulse_length = 19;
af4: 2313 movs r3, #19
af6: 7683 strb r3, [r0, #26]
config->iso7816_config.inhibit_nack = ISO7816_INHIBIT_NACK_DISABLE;
config->iso7816_config.successive_recv_nack = ISO7816_SUCCESSIVE_RECV_NACK_DISABLE;
config->iso7816_config.max_iterations = 7;
#endif
#ifdef FEATURE_USART_COLLISION_DECTION
config->collision_detection_enable = false;
af8: 7742 strb r2, [r0, #29]
struct usart_config uconf;
usart_get_config_defaults(&uconf);
uconf.pinmux_pad0 = DEBUG_USART_PINMUX_PAD0;
afa: 4b1e ldr r3, [pc, #120] ; (b74 <p_usart_init+0xc4>)
afc: 930c str r3, [sp, #48] ; 0x30
uconf.pinmux_pad1 = DEBUG_USART_PINMUX_PAD1;
afe: 4b1e ldr r3, [pc, #120] ; (b78 <p_usart_init+0xc8>)
b00: 930d str r3, [sp, #52] ; 0x34
uconf.pinmux_pad2 = DEBUG_USART_PINMUX_PAD2;
b02: 2301 movs r3, #1
b04: 425b negs r3, r3
b06: 930e str r3, [sp, #56] ; 0x38
uconf.pinmux_pad3 = DEBUG_USART_PINMUX_PAD3;
b08: 930f str r3, [sp, #60] ; 0x3c
uconf.mux_setting = DEBUG_USART_MUX_SETTING;
b0a: 2380 movs r3, #128 ; 0x80
b0c: 035b lsls r3, r3, #13
b0e: 9303 str r3, [sp, #12]
uconf.baudrate = DEBUG_USART_BAUDRATE;
b10: 23e1 movs r3, #225 ; 0xe1
b12: 025b lsls r3, r3, #9
b14: 9308 str r3, [sp, #32]
static inline void stdio_serial_init(
struct usart_module *const module,
usart_inst_t const hw,
const struct usart_config *const config)
{
stdio_base = (void *)module;
b16: 4d19 ldr r5, [pc, #100] ; (b7c <p_usart_init+0xcc>)
b18: 4b19 ldr r3, [pc, #100] ; (b80 <p_usart_init+0xd0>)
b1a: 601d str r5, [r3, #0]
ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
b1c: 4a19 ldr r2, [pc, #100] ; (b84 <p_usart_init+0xd4>)
b1e: 4b1a ldr r3, [pc, #104] ; (b88 <p_usart_init+0xd8>)
b20: 601a str r2, [r3, #0]
ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
b22: 4a1a ldr r2, [pc, #104] ; (b8c <p_usart_init+0xdc>)
b24: 4b1a ldr r3, [pc, #104] ; (b90 <p_usart_init+0xe0>)
b26: 601a str r2, [r3, #0]
if (usart_init(module, hw, config) == STATUS_OK) {
b28: 466a mov r2, sp
b2a: 491a ldr r1, [pc, #104] ; (b94 <p_usart_init+0xe4>)
b2c: 0028 movs r0, r5
b2e: 4b1a ldr r3, [pc, #104] ; (b98 <p_usart_init+0xe8>)
b30: 4798 blx r3
usart_serial_init(module, hw, config);
# if defined(__GNUC__)
// Specify that stdout and stdin should not be buffered.
setbuf(stdout, NULL);
b32: 4f1a ldr r7, [pc, #104] ; (b9c <p_usart_init+0xec>)
b34: 683b ldr r3, [r7, #0]
b36: 6898 ldr r0, [r3, #8]
b38: 2100 movs r1, #0
b3a: 4e19 ldr r6, [pc, #100] ; (ba0 <p_usart_init+0xf0>)
b3c: 47b0 blx r6
setbuf(stdin, NULL);
b3e: 683b ldr r3, [r7, #0]
b40: 6858 ldr r0, [r3, #4]
b42: 2100 movs r1, #0
b44: 47b0 blx r6
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
b46: 682e ldr r6, [r5, #0]
#if USART_CALLBACK_MODE == true
/* Enable Global interrupt for module */
system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
b48: 0030 movs r0, r6
b4a: 4b16 ldr r3, [pc, #88] ; (ba4 <p_usart_init+0xf4>)
b4c: 4798 blx r3
b4e: 231f movs r3, #31
b50: 4018 ands r0, r3
b52: 4084 lsls r4, r0
b54: 4b14 ldr r3, [pc, #80] ; (ba8 <p_usart_init+0xf8>)
b56: 601c str r4, [r3, #0]
SercomUsart *const usart_hw = &(module->hw->USART);
b58: 682a ldr r2, [r5, #0]
return (usart_hw->SYNCBUSY.reg);
b5a: 69d3 ldr r3, [r2, #28]
while (usart_is_syncing(module)) {
b5c: 2b00 cmp r3, #0
b5e: d1fc bne.n b5a <p_usart_init+0xaa>
/* Wait until synchronization is complete */
_usart_wait_for_sync(module);
/* Enable USART module */
usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
b60: 6833 ldr r3, [r6, #0]
b62: 2202 movs r2, #2
b64: 4313 orrs r3, r2
b66: 6033 str r3, [r6, #0]
stdio_serial_init(&du_mod, DEBUG_USART_MODULE, &uconf);
usart_enable(&du_mod);
printf("Hello world\n");
b68: 4810 ldr r0, [pc, #64] ; (bac <p_usart_init+0xfc>)
b6a: 4b11 ldr r3, [pc, #68] ; (bb0 <p_usart_init+0x100>)
b6c: 4798 blx r3
b6e: b011 add sp, #68 ; 0x44
b70: bdf0 pop {r4, r5, r6, r7, pc}
b72: 46c0 nop ; (mov r8, r8)
b74: 00160002 .word 0x00160002
b78: 00170002 .word 0x00170002
b7c: 20000210 .word 0x20000210
b80: 200000d8 .word 0x200000d8
b84: 00000a99 .word 0x00000a99
b88: 200000d4 .word 0x200000d4
b8c: 00000a6d .word 0x00000a6d
b90: 200000d0 .word 0x200000d0
b94: 42001400 .word 0x42001400
b98: 00000bb5 .word 0x00000bb5
b9c: 20000004 .word 0x20000004
ba0: 000038d9 .word 0x000038d9
ba4: 000014c9 .word 0x000014c9
ba8: e000e100 .word 0xe000e100
bac: 00004888 .word 0x00004888
bb0: 000038c5 .word 0x000038c5
00000bb4 <usart_init>:
*/
enum status_code usart_init(
struct usart_module *const module,
Sercom *const hw,
const struct usart_config *const config)
{
bb4: b5f0 push {r4, r5, r6, r7, lr}
bb6: 46de mov lr, fp
bb8: 4657 mov r7, sl
bba: 464e mov r6, r9
bbc: 4645 mov r5, r8
bbe: b5e0 push {r5, r6, r7, lr}
bc0: b091 sub sp, #68 ; 0x44
bc2: 0005 movs r5, r0
bc4: 000c movs r4, r1
bc6: 0016 movs r6, r2
Assert(config);
enum status_code status_code = STATUS_OK;
/* Assign module pointer to software instance struct */
module->hw = hw;
bc8: 6029 str r1, [r5, #0]
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
bca: 0008 movs r0, r1
bcc: 4bba ldr r3, [pc, #744] ; (eb8 <usart_init+0x304>)
bce: 4798 blx r3
bd0: 0002 movs r2, r0
#else
pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
#endif
if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
bd2: 6823 ldr r3, [r4, #0]
/* The module is busy resetting itself */
return STATUS_BUSY;
bd4: 2005 movs r0, #5
if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
bd6: 07db lsls r3, r3, #31
bd8: d506 bpl.n be8 <usart_init+0x34>
_sercom_set_handler(instance_index, _usart_interrupt_handler);
_sercom_instances[instance_index] = module;
#endif
return status_code;
}
bda: b011 add sp, #68 ; 0x44
bdc: bc3c pop {r2, r3, r4, r5}
bde: 4690 mov r8, r2
be0: 4699 mov r9, r3
be2: 46a2 mov sl, r4
be4: 46ab mov fp, r5
be6: bdf0 pop {r4, r5, r6, r7, pc}
if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
be8: 6823 ldr r3, [r4, #0]
return STATUS_ERR_DENIED;
bea: 3017 adds r0, #23
if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
bec: 079b lsls r3, r3, #30
bee: d4f4 bmi.n bda <usart_init+0x26>
case SYSTEM_CLOCK_APB_APBB:
PM->APBBMASK.reg |= mask;
break;
case SYSTEM_CLOCK_APB_APBC:
PM->APBCMASK.reg |= mask;
bf0: 49b2 ldr r1, [pc, #712] ; (ebc <usart_init+0x308>)
bf2: 6a08 ldr r0, [r1, #32]
pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
bf4: 1c97 adds r7, r2, #2
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
bf6: 2301 movs r3, #1
bf8: 40bb lsls r3, r7
bfa: 4303 orrs r3, r0
bfc: 620b str r3, [r1, #32]
gclk_chan_conf.source_generator = config->generator_source;
bfe: a90f add r1, sp, #60 ; 0x3c
c00: 272d movs r7, #45 ; 0x2d
c02: 5df3 ldrb r3, [r6, r7]
c04: 700b strb r3, [r1, #0]
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
c06: 3214 adds r2, #20
system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
c08: b2d3 uxtb r3, r2
c0a: 9302 str r3, [sp, #8]
c0c: 0018 movs r0, r3
c0e: 4bac ldr r3, [pc, #688] ; (ec0 <usart_init+0x30c>)
c10: 4798 blx r3
system_gclk_chan_enable(gclk_index);
c12: 9802 ldr r0, [sp, #8]
c14: 4bab ldr r3, [pc, #684] ; (ec4 <usart_init+0x310>)
c16: 4798 blx r3
sercom_set_gclk_generator(config->generator_source, false);
c18: 5df0 ldrb r0, [r6, r7]
c1a: 2100 movs r1, #0
c1c: 4baa ldr r3, [pc, #680] ; (ec8 <usart_init+0x314>)
c1e: 4798 blx r3
module->character_size = config->character_size;
c20: 7af3 ldrb r3, [r6, #11]
c22: 716b strb r3, [r5, #5]
module->receiver_enabled = config->receiver_enable;
c24: 2324 movs r3, #36 ; 0x24
c26: 5cf3 ldrb r3, [r6, r3]
c28: 71ab strb r3, [r5, #6]
module->transmitter_enabled = config->transmitter_enable;
c2a: 2325 movs r3, #37 ; 0x25
c2c: 5cf3 ldrb r3, [r6, r3]
c2e: 71eb strb r3, [r5, #7]
module->lin_slave_enabled = config->lin_slave_enable;
c30: 7ef3 ldrb r3, [r6, #27]
c32: 722b strb r3, [r5, #8]
module->start_frame_detection_enabled = config->start_frame_detection_enable;
c34: 7f33 ldrb r3, [r6, #28]
c36: 726b strb r3, [r5, #9]
SercomUsart *const usart_hw = &(module->hw->USART);
c38: 682b ldr r3, [r5, #0]
c3a: 4698 mov r8, r3
uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
c3c: 0018 movs r0, r3
c3e: 4b9e ldr r3, [pc, #632] ; (eb8 <usart_init+0x304>)
c40: 4798 blx r3
gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
c42: 3014 adds r0, #20
uint16_t baud = 0;
c44: 2200 movs r2, #0
c46: 230e movs r3, #14
c48: a906 add r1, sp, #24
c4a: 468c mov ip, r1
c4c: 4463 add r3, ip
c4e: 801a strh r2, [r3, #0]
switch (config->sample_rate) {
c50: 8a32 ldrh r2, [r6, #16]
c52: 9202 str r2, [sp, #8]
c54: 2380 movs r3, #128 ; 0x80
c56: 01db lsls r3, r3, #7
c58: 429a cmp r2, r3
c5a: d100 bne.n c5e <usart_init+0xaa>
c5c: e09a b.n d94 <usart_init+0x1e0>
c5e: d90f bls.n c80 <usart_init+0xcc>
c60: 23c0 movs r3, #192 ; 0xc0
c62: 01db lsls r3, r3, #7
c64: 9a02 ldr r2, [sp, #8]
c66: 429a cmp r2, r3
c68: d100 bne.n c6c <usart_init+0xb8>
c6a: e08e b.n d8a <usart_init+0x1d6>
c6c: 2380 movs r3, #128 ; 0x80
c6e: 021b lsls r3, r3, #8
c70: 429a cmp r2, r3
c72: d000 beq.n c76 <usart_init+0xc2>
c74: e11b b.n eae <usart_init+0x2fa>
sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
c76: 2303 movs r3, #3
c78: 9306 str r3, [sp, #24]
mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
c7a: 2300 movs r3, #0
c7c: 9307 str r3, [sp, #28]
c7e: e008 b.n c92 <usart_init+0xde>
switch (config->sample_rate) {
c80: 2380 movs r3, #128 ; 0x80
c82: 019b lsls r3, r3, #6
c84: 429a cmp r2, r3
c86: d000 beq.n c8a <usart_init+0xd6>
c88: e111 b.n eae <usart_init+0x2fa>
sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
c8a: 2310 movs r3, #16
c8c: 9306 str r3, [sp, #24]
mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
c8e: 3b0f subs r3, #15
c90: 9307 str r3, [sp, #28]
ctrla = (uint32_t)config->data_order |
c92: 6833 ldr r3, [r6, #0]
c94: 9305 str r3, [sp, #20]
(uint32_t)config->mux_setting |
c96: 68f3 ldr r3, [r6, #12]
c98: 469b mov fp, r3
config->sample_adjustment |
c9a: 6973 ldr r3, [r6, #20]
c9c: 9303 str r3, [sp, #12]
(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
c9e: 7e33 ldrb r3, [r6, #24]
ca0: 9304 str r3, [sp, #16]
(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
ca2: 2326 movs r3, #38 ; 0x26
ca4: 5cf3 ldrb r3, [r6, r3]
ca6: 469a mov sl, r3
transfer_mode = (uint32_t)config->transfer_mode;
ca8: 6873 ldr r3, [r6, #4]
caa: 4699 mov r9, r3
switch (transfer_mode)
cac: 2b00 cmp r3, #0
cae: d100 bne.n cb2 <usart_init+0xfe>
cb0: e09c b.n dec <usart_init+0x238>
cb2: 2380 movs r3, #128 ; 0x80
cb4: 055b lsls r3, r3, #21
cb6: 4599 cmp r9, r3
cb8: d100 bne.n cbc <usart_init+0x108>
cba: e080 b.n dbe <usart_init+0x20a>
if(config->encoding_format_enable) {
cbc: 7e73 ldrb r3, [r6, #25]
cbe: 2b00 cmp r3, #0
cc0: d002 beq.n cc8 <usart_init+0x114>
usart_hw->RXPL.reg = config->receive_pulse_length;
cc2: 7eb3 ldrb r3, [r6, #26]
cc4: 4642 mov r2, r8
cc6: 7393 strb r3, [r2, #14]
usart_hw->BAUD.reg = baud;
cc8: 230e movs r3, #14
cca: aa06 add r2, sp, #24
ccc: 4694 mov ip, r2
cce: 4463 add r3, ip
cd0: 881b ldrh r3, [r3, #0]
cd2: 4642 mov r2, r8
cd4: 8193 strh r3, [r2, #12]
ctrla |= transfer_mode;
cd6: 9b05 ldr r3, [sp, #20]
cd8: 465a mov r2, fp
cda: 4313 orrs r3, r2
cdc: 9a03 ldr r2, [sp, #12]
cde: 4313 orrs r3, r2
ce0: 464a mov r2, r9
ce2: 4313 orrs r3, r2
ce4: 9f02 ldr r7, [sp, #8]
ce6: 431f orrs r7, r3
(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
ce8: 9b04 ldr r3, [sp, #16]
cea: 021b lsls r3, r3, #8
ctrla |= transfer_mode;
cec: 431f orrs r7, r3
(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
cee: 4653 mov r3, sl
cf0: 075b lsls r3, r3, #29
ctrla |= transfer_mode;
cf2: 431f orrs r7, r3
if (config->use_external_clock == false) {
cf4: 2327 movs r3, #39 ; 0x27
cf6: 5cf3 ldrb r3, [r6, r3]
cf8: 2b00 cmp r3, #0
cfa: d101 bne.n d00 <usart_init+0x14c>
ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
cfc: 3304 adds r3, #4
cfe: 431f orrs r7, r3
(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
d00: 7e73 ldrb r3, [r6, #25]
d02: 029b lsls r3, r3, #10
(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
d04: 7f32 ldrb r2, [r6, #28]
d06: 0252 lsls r2, r2, #9
(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
d08: 4313 orrs r3, r2
(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
d0a: 7f72 ldrb r2, [r6, #29]
d0c: 0212 lsls r2, r2, #8
(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
d0e: 4313 orrs r3, r2
(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
d10: 2224 movs r2, #36 ; 0x24
d12: 5cb2 ldrb r2, [r6, r2]
d14: 0452 lsls r2, r2, #17
(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
d16: 4313 orrs r3, r2
(config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
d18: 2225 movs r2, #37 ; 0x25
d1a: 5cb2 ldrb r2, [r6, r2]
d1c: 0412 lsls r2, r2, #16
(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
d1e: 4313 orrs r3, r2
ctrlb |= (uint32_t)config->character_size;
d20: 7ab1 ldrb r1, [r6, #10]
d22: 7af2 ldrb r2, [r6, #11]
d24: 4311 orrs r1, r2
d26: 4319 orrs r1, r3
if (config->parity != USART_PARITY_NONE) {
d28: 8933 ldrh r3, [r6, #8]
d2a: 2bff cmp r3, #255 ; 0xff
d2c: d100 bne.n d30 <usart_init+0x17c>
d2e: e081 b.n e34 <usart_init+0x280>
ctrla |= SERCOM_USART_CTRLA_FORM(1);
d30: 2280 movs r2, #128 ; 0x80
d32: 0452 lsls r2, r2, #17
d34: 4317 orrs r7, r2
ctrlb |= config->parity;
d36: 4319 orrs r1, r3
if (config->run_in_standby || system_is_debugger_present()) {
d38: 232c movs r3, #44 ; 0x2c
d3a: 5cf3 ldrb r3, [r6, r3]
d3c: 2b00 cmp r3, #0
d3e: d103 bne.n d48 <usart_init+0x194>
d40: 4b62 ldr r3, [pc, #392] ; (ecc <usart_init+0x318>)
d42: 789b ldrb r3, [r3, #2]
d44: 079b lsls r3, r3, #30
d46: d501 bpl.n d4c <usart_init+0x198>
ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
d48: 2380 movs r3, #128 ; 0x80
d4a: 431f orrs r7, r3
SercomUsart *const usart_hw = &(module->hw->USART);
d4c: 682a ldr r2, [r5, #0]
return (usart_hw->SYNCBUSY.reg);
d4e: 69d3 ldr r3, [r2, #28]
while (usart_is_syncing(module)) {
d50: 2b00 cmp r3, #0
d52: d1fc bne.n d4e <usart_init+0x19a>
usart_hw->CTRLB.reg = ctrlb;
d54: 4643 mov r3, r8
d56: 6059 str r1, [r3, #4]
SercomUsart *const usart_hw = &(module->hw->USART);
d58: 682a ldr r2, [r5, #0]
return (usart_hw->SYNCBUSY.reg);
d5a: 69d3 ldr r3, [r2, #28]
while (usart_is_syncing(module)) {
d5c: 2b00 cmp r3, #0
d5e: d1fc bne.n d5a <usart_init+0x1a6>
usart_hw->CTRLA.reg = ctrla;
d60: 4643 mov r3, r8
d62: 601f str r7, [r3, #0]
config->mux_position = SYSTEM_PINMUX_GPIO;
d64: ab0e add r3, sp, #56 ; 0x38
d66: 2280 movs r2, #128 ; 0x80
d68: 701a strb r2, [r3, #0]
config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
d6a: 2200 movs r2, #0
d6c: 705a strb r2, [r3, #1]
config->powersave = false;
d6e: 70da strb r2, [r3, #3]
pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
d70: 709a strb r2, [r3, #2]
uint32_t pad_pinmuxes[] = {
d72: 6b33 ldr r3, [r6, #48] ; 0x30
d74: 930a str r3, [sp, #40] ; 0x28
d76: 6b73 ldr r3, [r6, #52] ; 0x34
d78: 930b str r3, [sp, #44] ; 0x2c
d7a: 6bb3 ldr r3, [r6, #56] ; 0x38
d7c: 930c str r3, [sp, #48] ; 0x30
d7e: 6bf3 ldr r3, [r6, #60] ; 0x3c
d80: 9302 str r3, [sp, #8]
d82: 930d str r3, [sp, #52] ; 0x34
d84: 2700 movs r7, #0
uint32_t current_pinmux = pad_pinmuxes[pad];
d86: ae0a add r6, sp, #40 ; 0x28
d88: e063 b.n e52 <usart_init+0x29e>
sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
d8a: 2308 movs r3, #8
d8c: 9306 str r3, [sp, #24]
mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
d8e: 3b07 subs r3, #7
d90: 9307 str r3, [sp, #28]
d92: e77e b.n c92 <usart_init+0xde>
ctrla = (uint32_t)config->data_order |
d94: 6833 ldr r3, [r6, #0]
d96: 9305 str r3, [sp, #20]
(uint32_t)config->mux_setting |
d98: 68f3 ldr r3, [r6, #12]
d9a: 469b mov fp, r3
config->sample_adjustment |
d9c: 6973 ldr r3, [r6, #20]
d9e: 9303 str r3, [sp, #12]
(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
da0: 7e33 ldrb r3, [r6, #24]
da2: 9304 str r3, [sp, #16]
(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
da4: 2326 movs r3, #38 ; 0x26
da6: 5cf3 ldrb r3, [r6, r3]
da8: 469a mov sl, r3
transfer_mode = (uint32_t)config->transfer_mode;
daa: 6873 ldr r3, [r6, #4]
dac: 4699 mov r9, r3
switch (transfer_mode)
dae: 2b00 cmp r3, #0
db0: d018 beq.n de4 <usart_init+0x230>
db2: 2380 movs r3, #128 ; 0x80
db4: 055b lsls r3, r3, #21
db6: 4599 cmp r9, r3
db8: d001 beq.n dbe <usart_init+0x20a>
enum status_code status_code = STATUS_OK;
dba: 2000 movs r0, #0
dbc: e025 b.n e0a <usart_init+0x256>
if (!config->use_external_clock) {
dbe: 2327 movs r3, #39 ; 0x27
dc0: 5cf3 ldrb r3, [r6, r3]
dc2: 2b00 cmp r3, #0
dc4: d000 beq.n dc8 <usart_init+0x214>
dc6: e779 b.n cbc <usart_init+0x108>
status_code = _sercom_get_sync_baud_val(config->baudrate,
dc8: 6a33 ldr r3, [r6, #32]
dca: 001f movs r7, r3
dcc: b2c0 uxtb r0, r0
dce: 4b40 ldr r3, [pc, #256] ; (ed0 <usart_init+0x31c>)
dd0: 4798 blx r3
dd2: 0001 movs r1, r0
dd4: 220e movs r2, #14
dd6: ab06 add r3, sp, #24
dd8: 469c mov ip, r3
dda: 4462 add r2, ip
ddc: 0038 movs r0, r7
dde: 4b3d ldr r3, [pc, #244] ; (ed4 <usart_init+0x320>)
de0: 4798 blx r3
de2: e012 b.n e0a <usart_init+0x256>
sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
de4: 2308 movs r3, #8
de6: 9306 str r3, [sp, #24]
mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
de8: 2300 movs r3, #0
dea: 9307 str r3, [sp, #28]
if (config->use_external_clock) {
dec: 2327 movs r3, #39 ; 0x27
dee: 5cf3 ldrb r3, [r6, r3]
df0: 2b00 cmp r3, #0
df2: d00e beq.n e12 <usart_init+0x25e>
status_code =
df4: 9b06 ldr r3, [sp, #24]
df6: 9300 str r3, [sp, #0]
df8: 9b07 ldr r3, [sp, #28]
dfa: 220e movs r2, #14
dfc: a906 add r1, sp, #24
dfe: 468c mov ip, r1
e00: 4462 add r2, ip
e02: 6ab1 ldr r1, [r6, #40] ; 0x28
e04: 6a30 ldr r0, [r6, #32]
e06: 4f34 ldr r7, [pc, #208] ; (ed8 <usart_init+0x324>)
e08: 47b8 blx r7
if (status_code != STATUS_OK) {
e0a: 2800 cmp r0, #0
e0c: d000 beq.n e10 <usart_init+0x25c>
e0e: e6e4 b.n bda <usart_init+0x26>
e10: e754 b.n cbc <usart_init+0x108>
_sercom_get_async_baud_val(config->baudrate,
e12: 6a33 ldr r3, [r6, #32]
e14: 001f movs r7, r3
e16: b2c0 uxtb r0, r0
e18: 4b2d ldr r3, [pc, #180] ; (ed0 <usart_init+0x31c>)
e1a: 4798 blx r3
e1c: 0001 movs r1, r0
status_code =
e1e: 9b06 ldr r3, [sp, #24]
e20: 9300 str r3, [sp, #0]
e22: 9b07 ldr r3, [sp, #28]
e24: 220e movs r2, #14
e26: a806 add r0, sp, #24
e28: 4684 mov ip, r0
e2a: 4462 add r2, ip
e2c: 0038 movs r0, r7
e2e: 4f2a ldr r7, [pc, #168] ; (ed8 <usart_init+0x324>)
e30: 47b8 blx r7
e32: e7ea b.n e0a <usart_init+0x256>
if(config->lin_slave_enable) {
e34: 7ef3 ldrb r3, [r6, #27]
e36: 2b00 cmp r3, #0
e38: d100 bne.n e3c <usart_init+0x288>
e3a: e77d b.n d38 <usart_init+0x184>
ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
e3c: 2380 movs r3, #128 ; 0x80
e3e: 04db lsls r3, r3, #19
e40: 431f orrs r7, r3
e42: e779 b.n d38 <usart_init+0x184>
current_pinmux = _sercom_get_default_pad(hw, pad);
e44: 0020 movs r0, r4
e46: 4b25 ldr r3, [pc, #148] ; (edc <usart_init+0x328>)
e48: 4798 blx r3
e4a: e007 b.n e5c <usart_init+0x2a8>
e4c: 3701 adds r7, #1
for (uint8_t pad = 0; pad < 4; pad++) {
e4e: 2f04 cmp r7, #4
e50: d00d beq.n e6e <usart_init+0x2ba>
e52: b2f9 uxtb r1, r7
uint32_t current_pinmux = pad_pinmuxes[pad];
e54: 00bb lsls r3, r7, #2
e56: 5998 ldr r0, [r3, r6]
if (current_pinmux == PINMUX_DEFAULT) {
e58: 2800 cmp r0, #0
e5a: d0f3 beq.n e44 <usart_init+0x290>
if (current_pinmux != PINMUX_UNUSED) {
e5c: 1c43 adds r3, r0, #1
e5e: d0f5 beq.n e4c <usart_init+0x298>
pin_conf.mux_position = current_pinmux & 0xFFFF;
e60: a90e add r1, sp, #56 ; 0x38
e62: 7008 strb r0, [r1, #0]
system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
e64: 0c00 lsrs r0, r0, #16
e66: b2c0 uxtb r0, r0
e68: 4b1d ldr r3, [pc, #116] ; (ee0 <usart_init+0x32c>)
e6a: 4798 blx r3
e6c: e7ee b.n e4c <usart_init+0x298>
module->callback[i] = NULL;
e6e: 2300 movs r3, #0
e70: 60eb str r3, [r5, #12]
e72: 612b str r3, [r5, #16]
e74: 616b str r3, [r5, #20]
e76: 61ab str r3, [r5, #24]
e78: 61eb str r3, [r5, #28]
e7a: 622b str r3, [r5, #32]
module->tx_buffer_ptr = NULL;
e7c: 62ab str r3, [r5, #40] ; 0x28
module->rx_buffer_ptr = NULL;
e7e: 626b str r3, [r5, #36] ; 0x24
module->remaining_tx_buffer_length = 0x0000;
e80: 2200 movs r2, #0
e82: 85eb strh r3, [r5, #46] ; 0x2e
module->remaining_rx_buffer_length = 0x0000;
e84: 85ab strh r3, [r5, #44] ; 0x2c
module->callback_reg_mask = 0x00;
e86: 3330 adds r3, #48 ; 0x30
e88: 54ea strb r2, [r5, r3]
module->callback_enable_mask = 0x00;
e8a: 3301 adds r3, #1
e8c: 54ea strb r2, [r5, r3]
module->rx_status = STATUS_OK;
e8e: 3301 adds r3, #1
e90: 54ea strb r2, [r5, r3]
module->tx_status = STATUS_OK;
e92: 3301 adds r3, #1
e94: 54ea strb r2, [r5, r3]
uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
e96: 6828 ldr r0, [r5, #0]
e98: 4b07 ldr r3, [pc, #28] ; (eb8 <usart_init+0x304>)
e9a: 4798 blx r3
e9c: 0004 movs r4, r0
_sercom_set_handler(instance_index, _usart_interrupt_handler);
e9e: 4911 ldr r1, [pc, #68] ; (ee4 <usart_init+0x330>)
ea0: 4b11 ldr r3, [pc, #68] ; (ee8 <usart_init+0x334>)
ea2: 4798 blx r3
_sercom_instances[instance_index] = module;
ea4: 00a4 lsls r4, r4, #2
ea6: 4b11 ldr r3, [pc, #68] ; (eec <usart_init+0x338>)
ea8: 50e5 str r5, [r4, r3]
return status_code;
eaa: 2000 movs r0, #0
eac: e695 b.n bda <usart_init+0x26>
enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
eae: 2310 movs r3, #16
eb0: 9306 str r3, [sp, #24]
enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
eb2: 2300 movs r3, #0
eb4: 9307 str r3, [sp, #28]
eb6: e6ec b.n c92 <usart_init+0xde>
eb8: 00001451 .word 0x00001451
ebc: 40000400 .word 0x40000400
ec0: 00001a6d .word 0x00001a6d
ec4: 000019e1 .word 0x000019e1
ec8: 0000128d .word 0x0000128d
ecc: 41002000 .word 0x41002000
ed0: 00001a89 .word 0x00001a89
ed4: 000011cf .word 0x000011cf
ed8: 000011f9 .word 0x000011f9
edc: 000012d9 .word 0x000012d9
ee0: 00001b65 .word 0x00001b65
ee4: 00000f81 .word 0x00000f81
ee8: 0000148d .word 0x0000148d
eec: 20000244 .word 0x20000244
00000ef0 <usart_write_wait>:
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
/* Check that the transmitter is enabled */
if (!(module->transmitter_enabled)) {
ef0: 79c2 ldrb r2, [r0, #7]
return STATUS_ERR_DENIED;
ef2: 231c movs r3, #28
if (!(module->transmitter_enabled)) {
ef4: 2a00 cmp r2, #0
ef6: d101 bne.n efc <usart_write_wait+0xc>
while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
/* Wait until data is sent */
}
return STATUS_OK;
}
ef8: 0018 movs r0, r3
efa: 4770 bx lr
if (module->remaining_tx_buffer_length > 0) {
efc: 8dc2 ldrh r2, [r0, #46] ; 0x2e
efe: b292 uxth r2, r2
return STATUS_BUSY;
f00: 3b17 subs r3, #23
if (module->remaining_tx_buffer_length > 0) {
f02: 2a00 cmp r2, #0
f04: d1f8 bne.n ef8 <usart_write_wait+0x8>
SercomUsart *const usart_hw = &(module->hw->USART);
f06: 6802 ldr r2, [r0, #0]
usart_hw->DATA.reg = tx_data;
f08: 8511 strh r1, [r2, #40] ; 0x28
while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
f0a: 2102 movs r1, #2
f0c: 7e13 ldrb r3, [r2, #24]
f0e: 420b tst r3, r1
f10: d0fc beq.n f0c <usart_write_wait+0x1c>
return STATUS_OK;
f12: 2300 movs r3, #0
f14: e7f0 b.n ef8 <usart_write_wait+0x8>
00000f16 <usart_read_wait>:
/* Get a pointer to the hardware module instance */
SercomUsart *const usart_hw = &(module->hw->USART);
/* Check that the receiver is enabled */
if (!(module->receiver_enabled)) {
f16: 7982 ldrb r2, [r0, #6]
return STATUS_ERR_DENIED;
f18: 231c movs r3, #28
if (!(module->receiver_enabled)) {
f1a: 2a00 cmp r2, #0
f1c: d101 bne.n f22 <usart_read_wait+0xc>
/* Read data from USART module */
*rx_data = usart_hw->DATA.reg;
return STATUS_OK;
}
f1e: 0018 movs r0, r3
f20: 4770 bx lr
if (module->remaining_rx_buffer_length > 0) {
f22: 8d82 ldrh r2, [r0, #44] ; 0x2c
f24: b292 uxth r2, r2
return STATUS_BUSY;
f26: 3b17 subs r3, #23
if (module->remaining_rx_buffer_length > 0) {
f28: 2a00 cmp r2, #0
f2a: d1f8 bne.n f1e <usart_read_wait+0x8>
SercomUsart *const usart_hw = &(module->hw->USART);
f2c: 6802 ldr r2, [r0, #0]
if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
f2e: 7e10 ldrb r0, [r2, #24]
f30: 0740 lsls r0, r0, #29
f32: d5f4 bpl.n f1e <usart_read_wait+0x8>
error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
f34: 8b53 ldrh r3, [r2, #26]
f36: b2db uxtb r3, r3
if (error_code) {
f38: 0698 lsls r0, r3, #26
f3a: d01d beq.n f78 <usart_read_wait+0x62>
if (error_code & SERCOM_USART_STATUS_FERR) {
f3c: 0798 lsls r0, r3, #30
f3e: d503 bpl.n f48 <usart_read_wait+0x32>
usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
f40: 2302 movs r3, #2
f42: 8353 strh r3, [r2, #26]
return STATUS_ERR_BAD_FORMAT;
f44: 3318 adds r3, #24
f46: e7ea b.n f1e <usart_read_wait+0x8>
} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
f48: 0758 lsls r0, r3, #29
f4a: d503 bpl.n f54 <usart_read_wait+0x3e>
usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
f4c: 2304 movs r3, #4
f4e: 8353 strh r3, [r2, #26]
return STATUS_ERR_OVERFLOW;
f50: 331a adds r3, #26
f52: e7e4 b.n f1e <usart_read_wait+0x8>
} else if (error_code & SERCOM_USART_STATUS_PERR) {
f54: 07d8 lsls r0, r3, #31
f56: d503 bpl.n f60 <usart_read_wait+0x4a>
usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
f58: 2301 movs r3, #1
f5a: 8353 strh r3, [r2, #26]
return STATUS_ERR_BAD_DATA;
f5c: 3312 adds r3, #18
f5e: e7de b.n f1e <usart_read_wait+0x8>
else if (error_code & SERCOM_USART_STATUS_ISF) {
f60: 06d8 lsls r0, r3, #27
f62: d503 bpl.n f6c <usart_read_wait+0x56>
usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
f64: 2310 movs r3, #16
f66: 8353 strh r3, [r2, #26]
return STATUS_ERR_PROTOCOL;
f68: 3332 adds r3, #50 ; 0x32
f6a: e7d8 b.n f1e <usart_read_wait+0x8>
else if (error_code & SERCOM_USART_STATUS_COLL) {
f6c: 069b lsls r3, r3, #26
f6e: d503 bpl.n f78 <usart_read_wait+0x62>
usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
f70: 2320 movs r3, #32
f72: 8353 strh r3, [r2, #26]
return STATUS_ERR_PACKET_COLLISION;
f74: 3321 adds r3, #33 ; 0x21
f76: e7d2 b.n f1e <usart_read_wait+0x8>
*rx_data = usart_hw->DATA.reg;
f78: 8d13 ldrh r3, [r2, #40] ; 0x28
f7a: 800b strh r3, [r1, #0]
return STATUS_OK;
f7c: 2300 movs r3, #0
f7e: e7ce b.n f1e <usart_read_wait+0x8>
00000f80 <_usart_interrupt_handler>:
* \param[in] instance ID of the SERCOM instance calling the interrupt
* handler.
*/
void _usart_interrupt_handler(
uint8_t instance)
{
f80: b5f8 push {r3, r4, r5, r6, r7, lr}
uint16_t callback_status;
uint8_t error_code;
/* Get device instance from the look-up table */
struct usart_module *module
f82: 0080 lsls r0, r0, #2
f84: 4b62 ldr r3, [pc, #392] ; (1110 <_usart_interrupt_handler+0x190>)
f86: 58c5 ldr r5, [r0, r3]
= (struct usart_module *)_sercom_instances[instance];
/* Pointer to the hardware module instance */
SercomUsart *const usart_hw
= &(module->hw->USART);
f88: 682c ldr r4, [r5, #0]
return (usart_hw->SYNCBUSY.reg);
f8a: 69e3 ldr r3, [r4, #28]
while (usart_is_syncing(module)) {
f8c: 2b00 cmp r3, #0
f8e: d1fc bne.n f8a <_usart_interrupt_handler+0xa>
/* Wait for the synchronization to complete */
_usart_wait_for_sync(module);
/* Read and mask interrupt flag register */
interrupt_status = usart_hw->INTFLAG.reg;
f90: 7e23 ldrb r3, [r4, #24]
interrupt_status &= usart_hw->INTENSET.reg;
f92: 7da6 ldrb r6, [r4, #22]
f94: 401e ands r6, r3
callback_status = module->callback_reg_mask &
f96: 2330 movs r3, #48 ; 0x30
f98: 5ceb ldrb r3, [r5, r3]
f9a: 2231 movs r2, #49 ; 0x31
f9c: 5caf ldrb r7, [r5, r2]
f9e: 401f ands r7, r3
module->callback_enable_mask;
/* Check if a DATA READY interrupt has occurred,
* and if there is more to transfer */
if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
fa0: 07f3 lsls r3, r6, #31
fa2: d522 bpl.n fea <_usart_interrupt_handler+0x6a>
if (module->remaining_tx_buffer_length) {
fa4: 8deb ldrh r3, [r5, #46] ; 0x2e
fa6: b29b uxth r3, r3
fa8: 2b00 cmp r3, #0
faa: d01c beq.n fe6 <_usart_interrupt_handler+0x66>
/* Write value will be at least 8-bits long */
uint16_t data_to_send = *(module->tx_buffer_ptr);
fac: 6aaa ldr r2, [r5, #40] ; 0x28
fae: 7813 ldrb r3, [r2, #0]
fb0: b2db uxtb r3, r3
/* Increment 8-bit pointer */
(module->tx_buffer_ptr)++;
fb2: 1c51 adds r1, r2, #1
fb4: 62a9 str r1, [r5, #40] ; 0x28
if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
fb6: 7969 ldrb r1, [r5, #5]
fb8: 2901 cmp r1, #1
fba: d00e beq.n fda <_usart_interrupt_handler+0x5a>
uint16_t data_to_send = *(module->tx_buffer_ptr);
fbc: b29b uxth r3, r3
data_to_send |= (*(module->tx_buffer_ptr) << 8);
/* Increment 8-bit pointer */
(module->tx_buffer_ptr)++;
}
/* Write the data to send */
usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
fbe: 05db lsls r3, r3, #23
fc0: 0ddb lsrs r3, r3, #23
fc2: 8523 strh r3, [r4, #40] ; 0x28
if (--(module->remaining_tx_buffer_length) == 0) {
fc4: 8deb ldrh r3, [r5, #46] ; 0x2e
fc6: 3b01 subs r3, #1
fc8: b29b uxth r3, r3
fca: 85eb strh r3, [r5, #46] ; 0x2e
fcc: 2b00 cmp r3, #0
fce: d10c bne.n fea <_usart_interrupt_handler+0x6a>
/* Disable the Data Register Empty Interrupt */
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
fd0: 3301 adds r3, #1
fd2: 7523 strb r3, [r4, #20]
/* Enable Transmission Complete interrupt */
usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
fd4: 3301 adds r3, #1
fd6: 75a3 strb r3, [r4, #22]
fd8: e007 b.n fea <_usart_interrupt_handler+0x6a>
data_to_send |= (*(module->tx_buffer_ptr) << 8);
fda: 7851 ldrb r1, [r2, #1]
fdc: 0209 lsls r1, r1, #8
fde: 430b orrs r3, r1
(module->tx_buffer_ptr)++;
fe0: 3202 adds r2, #2
fe2: 62aa str r2, [r5, #40] ; 0x28
fe4: e7eb b.n fbe <_usart_interrupt_handler+0x3e>
}
} else {
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
fe6: 2301 movs r3, #1
fe8: 7523 strb r3, [r4, #20]
}
}
/* Check if the Transmission Complete interrupt has occurred and
* that the transmit buffer is empty */
if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
fea: 07b3 lsls r3, r6, #30
fec: d506 bpl.n ffc <_usart_interrupt_handler+0x7c>
/* Disable TX Complete Interrupt, and set STATUS_OK */
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
fee: 2302 movs r3, #2
ff0: 7523 strb r3, [r4, #20]
module->tx_status = STATUS_OK;
ff2: 2200 movs r2, #0
ff4: 3331 adds r3, #49 ; 0x31
ff6: 54ea strb r2, [r5, r3]
/* Run callback if registered and enabled */
if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {
ff8: 07fb lsls r3, r7, #31
ffa: d41a bmi.n 1032 <_usart_interrupt_handler+0xb2>
}
}
/* Check if the Receive Complete interrupt has occurred, and that
* there's more data to receive */
if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
ffc: 0773 lsls r3, r6, #29
ffe: d565 bpl.n 10cc <_usart_interrupt_handler+0x14c>
if (module->remaining_rx_buffer_length) {
1000: 8dab ldrh r3, [r5, #44] ; 0x2c
1002: b29b uxth r3, r3
1004: 2b00 cmp r3, #0
1006: d05f beq.n 10c8 <_usart_interrupt_handler+0x148>
/* Read out the status code and mask away all but the 4 LSBs*/
error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
1008: 8b63 ldrh r3, [r4, #26]
100a: b2db uxtb r3, r3
#if !SAMD20
/* CTS status should not be considered as an error */
if(error_code & SERCOM_USART_STATUS_CTS) {
100c: 071a lsls r2, r3, #28
100e: d414 bmi.n 103a <_usart_interrupt_handler+0xba>
error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
1010: 223f movs r2, #63 ; 0x3f
1012: 4013 ands r3, r2
if(error_code & SERCOM_USART_STATUS_TXE) {
error_code &= ~SERCOM_USART_STATUS_TXE;
}
#endif
/* Check if an error has occurred during the receiving */
if (error_code) {
1014: 2b00 cmp r3, #0
1016: d034 beq.n 1082 <_usart_interrupt_handler+0x102>
/* Check which error occurred */
if (error_code & SERCOM_USART_STATUS_FERR) {
1018: 079a lsls r2, r3, #30
101a: d511 bpl.n 1040 <_usart_interrupt_handler+0xc0>
/* Store the error code and clear flag by writing 1 to it */
module->rx_status = STATUS_ERR_BAD_FORMAT;
101c: 221a movs r2, #26
101e: 2332 movs r3, #50 ; 0x32
1020: 54ea strb r2, [r5, r3]
usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
1022: 3b30 subs r3, #48 ; 0x30
1024: 8363 strh r3, [r4, #26]
usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
}
#endif
/* Run callback if registered and enabled */
if (callback_status
1026: 077b lsls r3, r7, #29
1028: d550 bpl.n 10cc <_usart_interrupt_handler+0x14c>
& (1 << USART_CALLBACK_ERROR)) {
(*(module->callback[USART_CALLBACK_ERROR]))(module);
102a: 0028 movs r0, r5
102c: 696b ldr r3, [r5, #20]
102e: 4798 blx r3
1030: e04c b.n 10cc <_usart_interrupt_handler+0x14c>
(*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
1032: 0028 movs r0, r5
1034: 68eb ldr r3, [r5, #12]
1036: 4798 blx r3
1038: e7e0 b.n ffc <_usart_interrupt_handler+0x7c>
error_code &= ~SERCOM_USART_STATUS_CTS;
103a: 2237 movs r2, #55 ; 0x37
103c: 4013 ands r3, r2
103e: e7e9 b.n 1014 <_usart_interrupt_handler+0x94>
} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
1040: 075a lsls r2, r3, #29
1042: d505 bpl.n 1050 <_usart_interrupt_handler+0xd0>
module->rx_status = STATUS_ERR_OVERFLOW;
1044: 221e movs r2, #30
1046: 2332 movs r3, #50 ; 0x32
1048: 54ea strb r2, [r5, r3]
usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
104a: 3b2e subs r3, #46 ; 0x2e
104c: 8363 strh r3, [r4, #26]
104e: e7ea b.n 1026 <_usart_interrupt_handler+0xa6>
} else if (error_code & SERCOM_USART_STATUS_PERR) {
1050: 07da lsls r2, r3, #31
1052: d505 bpl.n 1060 <_usart_interrupt_handler+0xe0>
module->rx_status = STATUS_ERR_BAD_DATA;
1054: 2213 movs r2, #19
1056: 2332 movs r3, #50 ; 0x32
1058: 54ea strb r2, [r5, r3]
usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
105a: 3b31 subs r3, #49 ; 0x31
105c: 8363 strh r3, [r4, #26]
105e: e7e2 b.n 1026 <_usart_interrupt_handler+0xa6>
else if (error_code & SERCOM_USART_STATUS_ISF) {
1060: 06da lsls r2, r3, #27
1062: d505 bpl.n 1070 <_usart_interrupt_handler+0xf0>
module->rx_status = STATUS_ERR_PROTOCOL;
1064: 2242 movs r2, #66 ; 0x42
1066: 2332 movs r3, #50 ; 0x32
1068: 54ea strb r2, [r5, r3]
usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
106a: 3b22 subs r3, #34 ; 0x22
106c: 8363 strh r3, [r4, #26]
106e: e7da b.n 1026 <_usart_interrupt_handler+0xa6>
else if (error_code & SERCOM_USART_STATUS_COLL) {
1070: 2220 movs r2, #32
1072: 421a tst r2, r3
1074: d0d7 beq.n 1026 <_usart_interrupt_handler+0xa6>
module->rx_status = STATUS_ERR_PACKET_COLLISION;
1076: 3221 adds r2, #33 ; 0x21
1078: 2332 movs r3, #50 ; 0x32
107a: 54ea strb r2, [r5, r3]
usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
107c: 3b12 subs r3, #18
107e: 8363 strh r3, [r4, #26]
1080: e7d1 b.n 1026 <_usart_interrupt_handler+0xa6>
} else {
/* Read current packet from DATA register,
* increment buffer pointer and decrement buffer length */
uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
1082: 8d23 ldrh r3, [r4, #40] ; 0x28
1084: 05db lsls r3, r3, #23
1086: 0ddb lsrs r3, r3, #23
/* Read value will be at least 8-bits long */
*(module->rx_buffer_ptr) = received_data;
1088: b2da uxtb r2, r3
108a: 6a69 ldr r1, [r5, #36] ; 0x24
108c: 700a strb r2, [r1, #0]
/* Increment 8-bit pointer */
module->rx_buffer_ptr += 1;
108e: 6a6a ldr r2, [r5, #36] ; 0x24
1090: 1c51 adds r1, r2, #1
1092: 6269 str r1, [r5, #36] ; 0x24
if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
1094: 7969 ldrb r1, [r5, #5]
1096: 2901 cmp r1, #1
1098: d010 beq.n 10bc <_usart_interrupt_handler+0x13c>
/* Increment 8-bit pointer */
module->rx_buffer_ptr += 1;
}
/* Check if the last character have been received */
if(--(module->remaining_rx_buffer_length) == 0) {
109a: 8dab ldrh r3, [r5, #44] ; 0x2c
109c: 3b01 subs r3, #1
109e: b29b uxth r3, r3
10a0: 85ab strh r3, [r5, #44] ; 0x2c
10a2: 2b00 cmp r3, #0
10a4: d112 bne.n 10cc <_usart_interrupt_handler+0x14c>
/* Disable RX Complete Interrupt,
* and set STATUS_OK */
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
10a6: 3304 adds r3, #4
10a8: 7523 strb r3, [r4, #20]
module->rx_status = STATUS_OK;
10aa: 2200 movs r2, #0
10ac: 332e adds r3, #46 ; 0x2e
10ae: 54ea strb r2, [r5, r3]
/* Run callback if registered and enabled */
if (callback_status
10b0: 07bb lsls r3, r7, #30
10b2: d50b bpl.n 10cc <_usart_interrupt_handler+0x14c>
& (1 << USART_CALLBACK_BUFFER_RECEIVED)) {
(*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
10b4: 0028 movs r0, r5
10b6: 692b ldr r3, [r5, #16]
10b8: 4798 blx r3
10ba: e007 b.n 10cc <_usart_interrupt_handler+0x14c>
*(module->rx_buffer_ptr) = (received_data >> 8);
10bc: 0a1b lsrs r3, r3, #8
10be: 7053 strb r3, [r2, #1]
module->rx_buffer_ptr += 1;
10c0: 6a6b ldr r3, [r5, #36] ; 0x24
10c2: 3301 adds r3, #1
10c4: 626b str r3, [r5, #36] ; 0x24
10c6: e7e8 b.n 109a <_usart_interrupt_handler+0x11a>
}
}
}
} else {
/* This should not happen. Disable Receive Complete interrupt. */
usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
10c8: 2304 movs r3, #4
10ca: 7523 strb r3, [r4, #20]
}
}
#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
10cc: 06f3 lsls r3, r6, #27
10ce: d504 bpl.n 10da <_usart_interrupt_handler+0x15a>
/* Disable interrupts */
usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
10d0: 2310 movs r3, #16
10d2: 7523 strb r3, [r4, #20]
/* Clear interrupt flag */
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
10d4: 7623 strb r3, [r4, #24]
/* Run callback if registered and enabled */
if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) {
10d6: 06fb lsls r3, r7, #27
10d8: d40e bmi.n 10f8 <_usart_interrupt_handler+0x178>
}
}
#endif
#ifdef FEATURE_USART_LIN_SLAVE
if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
10da: 06b3 lsls r3, r6, #26
10dc: d504 bpl.n 10e8 <_usart_interrupt_handler+0x168>
/* Disable interrupts */
usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
10de: 2320 movs r3, #32
10e0: 7523 strb r3, [r4, #20]
/* Clear interrupt flag */
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
10e2: 7623 strb r3, [r4, #24]
/* Run callback if registered and enabled */
if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) {
10e4: 073b lsls r3, r7, #28
10e6: d40b bmi.n 1100 <_usart_interrupt_handler+0x180>
}
}
#endif
#ifdef FEATURE_USART_START_FRAME_DECTION
if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
10e8: 0733 lsls r3, r6, #28
10ea: d504 bpl.n 10f6 <_usart_interrupt_handler+0x176>
/* Disable interrupts */
usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
10ec: 2308 movs r3, #8
10ee: 7523 strb r3, [r4, #20]
/* Clear interrupt flag */
usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
10f0: 7623 strb r3, [r4, #24]
/* Run callback if registered and enabled */
if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) {
10f2: 06bb lsls r3, r7, #26
10f4: d408 bmi.n 1108 <_usart_interrupt_handler+0x188>
(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
}
}
#endif
}
10f6: bdf8 pop {r3, r4, r5, r6, r7, pc}
(*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
10f8: 0028 movs r0, r5
10fa: 69eb ldr r3, [r5, #28]
10fc: 4798 blx r3
10fe: e7ec b.n 10da <_usart_interrupt_handler+0x15a>
(*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
1100: 0028 movs r0, r5
1102: 69ab ldr r3, [r5, #24]
1104: 4798 blx r3
1106: e7ef b.n 10e8 <_usart_interrupt_handler+0x168>
(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
1108: 6a2b ldr r3, [r5, #32]
110a: 0028 movs r0, r5
110c: 4798 blx r3
}
110e: e7f2 b.n 10f6 <_usart_interrupt_handler+0x176>
1110: 20000244 .word 0x20000244
00001114 <long_division>:
/**
* \internal Calculate 64 bit division, ref can be found in
* http://en.wikipedia.org/wiki/Division_algorithm#Long_division
*/
static uint64_t long_division(uint64_t n, uint64_t d)
{
1114: b5f0 push {r4, r5, r6, r7, lr}
1116: 46de mov lr, fp
1118: 4657 mov r7, sl
111a: 464e mov r6, r9
111c: 4645 mov r5, r8
111e: b5e0 push {r5, r6, r7, lr}
1120: b087 sub sp, #28
1122: 4680 mov r8, r0
1124: 9104 str r1, [sp, #16]
1126: 0016 movs r6, r2
1128: 001f movs r7, r3
int32_t i;
uint64_t q = 0, r = 0, bit_shift;
112a: 2200 movs r2, #0
112c: 2300 movs r3, #0
112e: 2100 movs r1, #0
1130: 468b mov fp, r1
for (i = 63; i >= 0; i--) {
1132: 243f movs r4, #63 ; 0x3f
bit_shift = (uint64_t)1 << i;
1134: 2001 movs r0, #1
1136: 0021 movs r1, r4
1138: 9600 str r6, [sp, #0]
113a: 9701 str r7, [sp, #4]
113c: 465c mov r4, fp
113e: 9403 str r4, [sp, #12]
1140: 4644 mov r4, r8
1142: 9405 str r4, [sp, #20]
1144: e013 b.n 116e <long_division+0x5a>
1146: 2420 movs r4, #32
1148: 1a64 subs r4, r4, r1
114a: 0005 movs r5, r0
114c: 40e5 lsrs r5, r4
114e: 46a8 mov r8, r5
1150: e014 b.n 117c <long_division+0x68>
if (n & bit_shift) {
r |= 0x01;
}
if (r >= d) {
r = r - d;
1152: 9c00 ldr r4, [sp, #0]
1154: 9d01 ldr r5, [sp, #4]
1156: 1b12 subs r2, r2, r4
1158: 41ab sbcs r3, r5
q |= bit_shift;
115a: 465c mov r4, fp
115c: 464d mov r5, r9
115e: 432c orrs r4, r5
1160: 46a3 mov fp, r4
1162: 9c03 ldr r4, [sp, #12]
1164: 4645 mov r5, r8
1166: 432c orrs r4, r5
1168: 9403 str r4, [sp, #12]
for (i = 63; i >= 0; i--) {
116a: 3901 subs r1, #1
116c: d325 bcc.n 11ba <long_division+0xa6>
bit_shift = (uint64_t)1 << i;
116e: 2420 movs r4, #32
1170: 4264 negs r4, r4
1172: 190c adds r4, r1, r4
1174: d4e7 bmi.n 1146 <long_division+0x32>
1176: 0005 movs r5, r0
1178: 40a5 lsls r5, r4
117a: 46a8 mov r8, r5
117c: 0004 movs r4, r0
117e: 408c lsls r4, r1
1180: 46a1 mov r9, r4
r = r << 1;
1182: 1892 adds r2, r2, r2
1184: 415b adcs r3, r3
1186: 0014 movs r4, r2
1188: 001d movs r5, r3
if (n & bit_shift) {
118a: 9e05 ldr r6, [sp, #20]
118c: 464f mov r7, r9
118e: 403e ands r6, r7
1190: 46b4 mov ip, r6
1192: 9e04 ldr r6, [sp, #16]
1194: 4647 mov r7, r8
1196: 403e ands r6, r7
1198: 46b2 mov sl, r6
119a: 4666 mov r6, ip
119c: 4657 mov r7, sl
119e: 433e orrs r6, r7
11a0: d003 beq.n 11aa <long_division+0x96>
r |= 0x01;
11a2: 0006 movs r6, r0
11a4: 4326 orrs r6, r4
11a6: 0032 movs r2, r6
11a8: 002b movs r3, r5
if (r >= d) {
11aa: 9c00 ldr r4, [sp, #0]
11ac: 9d01 ldr r5, [sp, #4]
11ae: 429d cmp r5, r3
11b0: d8db bhi.n 116a <long_division+0x56>
11b2: d1ce bne.n 1152 <long_division+0x3e>
11b4: 4294 cmp r4, r2
11b6: d8d8 bhi.n 116a <long_division+0x56>
11b8: e7cb b.n 1152 <long_division+0x3e>
11ba: 9b03 ldr r3, [sp, #12]
}
}
return q;
}
11bc: 4658 mov r0, fp
11be: 0019 movs r1, r3
11c0: b007 add sp, #28
11c2: bc3c pop {r2, r3, r4, r5}
11c4: 4690 mov r8, r2
11c6: 4699 mov r9, r3
11c8: 46a2 mov sl, r4
11ca: 46ab mov fp, r5
11cc: bdf0 pop {r4, r5, r6, r7, pc}
000011ce <_sercom_get_sync_baud_val>:
*/
enum status_code _sercom_get_sync_baud_val(
const uint32_t baudrate,
const uint32_t external_clock,
uint16_t *const baudvalue)
{
11ce: b510 push {r4, lr}
uint16_t baud_calculated = 0;
uint32_t clock_value = external_clock;
/* Check if baudrate is outside of valid range */
if (baudrate > (external_clock / 2)) {
11d0: 0849 lsrs r1, r1, #1
/* Return with error code */
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
11d2: 2340 movs r3, #64 ; 0x40
11d4: 2400 movs r4, #0
if (baudrate > (external_clock / 2)) {
11d6: 4281 cmp r1, r0
11d8: d202 bcs.n 11e0 <_sercom_get_sync_baud_val+0x12>
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
} else {
*baudvalue = baud_calculated;
return STATUS_OK;
}
}
11da: 0018 movs r0, r3
11dc: bd10 pop {r4, pc}
baud_calculated++;
11de: 001c movs r4, r3
clock_value = clock_value - baudrate;
11e0: 1a09 subs r1, r1, r0
baud_calculated++;
11e2: 1c63 adds r3, r4, #1
11e4: b29b uxth r3, r3
while (clock_value >= baudrate) {
11e6: 4288 cmp r0, r1
11e8: d9f9 bls.n 11de <_sercom_get_sync_baud_val+0x10>
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
11ea: 2340 movs r3, #64 ; 0x40
if (baud_calculated > 0xFF) {
11ec: 2cff cmp r4, #255 ; 0xff
11ee: d8f4 bhi.n 11da <_sercom_get_sync_baud_val+0xc>
*baudvalue = baud_calculated;
11f0: 8014 strh r4, [r2, #0]
return STATUS_OK;
11f2: 2300 movs r3, #0
11f4: e7f1 b.n 11da <_sercom_get_sync_baud_val+0xc>
...
000011f8 <_sercom_get_async_baud_val>:
const uint32_t baudrate,
const uint32_t peripheral_clock,
uint16_t *const baudval,
enum sercom_asynchronous_operation_mode mode,
enum sercom_asynchronous_sample_num sample_num)
{
11f8: b5f0 push {r4, r5, r6, r7, lr}
11fa: b083 sub sp, #12
11fc: 000f movs r7, r1
11fe: 0016 movs r6, r2
1200: aa08 add r2, sp, #32
1202: 7811 ldrb r1, [r2, #0]
uint8_t baud_fp;
uint32_t baud_int = 0;
uint64_t temp1;
/* Check if the baudrate is outside of valid range */
if ((baudrate * sample_num) > peripheral_clock) {
1204: 0004 movs r4, r0
1206: 434c muls r4, r1
/* Return with error code */
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
1208: 2240 movs r2, #64 ; 0x40
if ((baudrate * sample_num) > peripheral_clock) {
120a: 42bc cmp r4, r7
120c: d902 bls.n 1214 <_sercom_get_async_baud_val+0x1c>
baud_calculated = baud_int | (baud_fp << 13);
}
*baudval = baud_calculated;
return STATUS_OK;
}
120e: 0010 movs r0, r2
1210: b003 add sp, #12
1212: bdf0 pop {r4, r5, r6, r7, pc}
if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
1214: 2b00 cmp r3, #0
1216: d114 bne.n 1242 <_sercom_get_async_baud_val+0x4a>
temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
1218: 0002 movs r2, r0
121a: 0008 movs r0, r1
121c: 2100 movs r1, #0
121e: 4c19 ldr r4, [pc, #100] ; (1284 <_sercom_get_async_baud_val+0x8c>)
1220: 47a0 blx r4
1222: 0001 movs r1, r0
ratio = long_division(temp1, peripheral_clock);
1224: 003a movs r2, r7
1226: 2300 movs r3, #0
1228: 2000 movs r0, #0
122a: 4c17 ldr r4, [pc, #92] ; (1288 <_sercom_get_async_baud_val+0x90>)
122c: 47a0 blx r4
scale = ((uint64_t)1 << SHIFT) - ratio;
122e: 2200 movs r2, #0
1230: 2301 movs r3, #1
1232: 1a12 subs r2, r2, r0
1234: 418b sbcs r3, r1
baud_calculated = (65536 * scale) >> SHIFT;
1236: 0c12 lsrs r2, r2, #16
1238: 041b lsls r3, r3, #16
123a: 431a orrs r2, r3
*baudval = baud_calculated;
123c: 8032 strh r2, [r6, #0]
return STATUS_OK;
123e: 2200 movs r2, #0
1240: e7e5 b.n 120e <_sercom_get_async_baud_val+0x16>
uint64_t baud_calculated = 0;
1242: 2200 movs r2, #0
} else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
1244: 2b01 cmp r3, #1
1246: d1f9 bne.n 123c <_sercom_get_async_baud_val+0x44>
temp1 = ((uint64_t)baudrate * sample_num);
1248: 000a movs r2, r1
124a: 2300 movs r3, #0
124c: 2100 movs r1, #0
124e: 4c0d ldr r4, [pc, #52] ; (1284 <_sercom_get_async_baud_val+0x8c>)
1250: 47a0 blx r4
1252: 0002 movs r2, r0
1254: 000b movs r3, r1
1256: 9200 str r2, [sp, #0]
1258: 9301 str r3, [sp, #4]
baud_int = long_division( peripheral_clock, temp1);
125a: 0038 movs r0, r7
125c: 2100 movs r1, #0
125e: 4c0a ldr r4, [pc, #40] ; (1288 <_sercom_get_async_baud_val+0x90>)
1260: 47a0 blx r4
1262: 0005 movs r5, r0
if(baud_int > BAUD_INT_MAX) {
1264: 2380 movs r3, #128 ; 0x80
1266: 019b lsls r3, r3, #6
return STATUS_ERR_BAUDRATE_UNAVAILABLE;
1268: 2240 movs r2, #64 ; 0x40
if(baud_int > BAUD_INT_MAX) {
126a: 4298 cmp r0, r3
126c: d8cf bhi.n 120e <_sercom_get_async_baud_val+0x16>
temp1 = long_division( 8 * (uint64_t)peripheral_clock, temp1);
126e: 0f79 lsrs r1, r7, #29
1270: 00f8 lsls r0, r7, #3
1272: 9a00 ldr r2, [sp, #0]
1274: 9b01 ldr r3, [sp, #4]
1276: 47a0 blx r4
baud_fp = temp1 - 8 * baud_int;
1278: 00ea lsls r2, r5, #3
127a: 1a82 subs r2, r0, r2
baud_calculated = baud_int | (baud_fp << 13);
127c: b2d2 uxtb r2, r2
127e: 0352 lsls r2, r2, #13
1280: 432a orrs r2, r5
1282: e7db b.n 123c <_sercom_get_async_baud_val+0x44>
1284: 00001e5d .word 0x00001e5d
1288: 00001115 .word 0x00001115
0000128c <sercom_set_gclk_generator>:
* forced.
*/
enum status_code sercom_set_gclk_generator(
const enum gclk_generator generator_source,
const bool force_change)
{
128c: b510 push {r4, lr}
128e: b082 sub sp, #8
1290: 0004 movs r4, r0
/* Check if valid option */
if (!_sercom_config.generator_is_set || force_change) {
1292: 4b0e ldr r3, [pc, #56] ; (12cc <sercom_set_gclk_generator+0x40>)
1294: 781b ldrb r3, [r3, #0]
1296: 2b00 cmp r3, #0
1298: d007 beq.n 12aa <sercom_set_gclk_generator+0x1e>
129a: 2900 cmp r1, #0
129c: d105 bne.n 12aa <sercom_set_gclk_generator+0x1e>
/* Save config */
_sercom_config.generator_source = generator_source;
_sercom_config.generator_is_set = true;
return STATUS_OK;
} else if (generator_source == _sercom_config.generator_source) {
129e: 4b0b ldr r3, [pc, #44] ; (12cc <sercom_set_gclk_generator+0x40>)
12a0: 785b ldrb r3, [r3, #1]
12a2: 4283 cmp r3, r0
12a4: d010 beq.n 12c8 <sercom_set_gclk_generator+0x3c>
/* Return status OK if same config */
return STATUS_OK;
}
/* Return invalid config to already initialized GCLK */
return STATUS_ERR_ALREADY_INITIALIZED;
12a6: 201d movs r0, #29
12a8: e00c b.n 12c4 <sercom_set_gclk_generator+0x38>
gclk_chan_conf.source_generator = generator_source;
12aa: a901 add r1, sp, #4
12ac: 700c strb r4, [r1, #0]
system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
12ae: 2013 movs r0, #19
12b0: 4b07 ldr r3, [pc, #28] ; (12d0 <sercom_set_gclk_generator+0x44>)
12b2: 4798 blx r3
system_gclk_chan_enable(SERCOM_GCLK_ID);
12b4: 2013 movs r0, #19
12b6: 4b07 ldr r3, [pc, #28] ; (12d4 <sercom_set_gclk_generator+0x48>)
12b8: 4798 blx r3
_sercom_config.generator_source = generator_source;
12ba: 4b04 ldr r3, [pc, #16] ; (12cc <sercom_set_gclk_generator+0x40>)
12bc: 705c strb r4, [r3, #1]
_sercom_config.generator_is_set = true;
12be: 2201 movs r2, #1
12c0: 701a strb r2, [r3, #0]
return STATUS_OK;
12c2: 2000 movs r0, #0
}
12c4: b002 add sp, #8
12c6: bd10 pop {r4, pc}
return STATUS_OK;
12c8: 2000 movs r0, #0
12ca: e7fb b.n 12c4 <sercom_set_gclk_generator+0x38>
12cc: 20000088 .word 0x20000088
12d0: 00001a6d .word 0x00001a6d
12d4: 000019e1 .word 0x000019e1
000012d8 <_sercom_get_default_pad>:
*/
uint32_t _sercom_get_default_pad(
Sercom *const sercom_module,
const uint8_t pad)
{
switch ((uintptr_t)sercom_module) {
12d8: 4b40 ldr r3, [pc, #256] ; (13dc <_sercom_get_default_pad+0x104>)
12da: 4298 cmp r0, r3
12dc: d031 beq.n 1342 <_sercom_get_default_pad+0x6a>
12de: d90a bls.n 12f6 <_sercom_get_default_pad+0x1e>
12e0: 4b3f ldr r3, [pc, #252] ; (13e0 <_sercom_get_default_pad+0x108>)
12e2: 4298 cmp r0, r3
12e4: d04d beq.n 1382 <_sercom_get_default_pad+0xaa>
12e6: 4b3f ldr r3, [pc, #252] ; (13e4 <_sercom_get_default_pad+0x10c>)
12e8: 4298 cmp r0, r3
12ea: d05a beq.n 13a2 <_sercom_get_default_pad+0xca>
12ec: 4b3e ldr r3, [pc, #248] ; (13e8 <_sercom_get_default_pad+0x110>)
12ee: 4298 cmp r0, r3
12f0: d037 beq.n 1362 <_sercom_get_default_pad+0x8a>
/* Auto-generate a lookup table for the default SERCOM pad defaults */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
}
Assert(false);
return 0;
12f2: 2000 movs r0, #0
}
12f4: 4770 bx lr
switch ((uintptr_t)sercom_module) {
12f6: 4b3d ldr r3, [pc, #244] ; (13ec <_sercom_get_default_pad+0x114>)
12f8: 4298 cmp r0, r3
12fa: d00c beq.n 1316 <_sercom_get_default_pad+0x3e>
12fc: 4b3c ldr r3, [pc, #240] ; (13f0 <_sercom_get_default_pad+0x118>)
12fe: 4298 cmp r0, r3
1300: d1f7 bne.n 12f2 <_sercom_get_default_pad+0x1a>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
1302: 2901 cmp r1, #1
1304: d017 beq.n 1336 <_sercom_get_default_pad+0x5e>
1306: 2900 cmp r1, #0
1308: d05d beq.n 13c6 <_sercom_get_default_pad+0xee>
130a: 2902 cmp r1, #2
130c: d015 beq.n 133a <_sercom_get_default_pad+0x62>
130e: 2903 cmp r1, #3
1310: d015 beq.n 133e <_sercom_get_default_pad+0x66>
return 0;
1312: 2000 movs r0, #0
1314: e7ee b.n 12f4 <_sercom_get_default_pad+0x1c>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
1316: 2901 cmp r1, #1
1318: d007 beq.n 132a <_sercom_get_default_pad+0x52>
131a: 2900 cmp r1, #0
131c: d051 beq.n 13c2 <_sercom_get_default_pad+0xea>
131e: 2902 cmp r1, #2
1320: d005 beq.n 132e <_sercom_get_default_pad+0x56>
1322: 2903 cmp r1, #3
1324: d005 beq.n 1332 <_sercom_get_default_pad+0x5a>
return 0;
1326: 2000 movs r0, #0
1328: e7e4 b.n 12f4 <_sercom_get_default_pad+0x1c>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
132a: 4832 ldr r0, [pc, #200] ; (13f4 <_sercom_get_default_pad+0x11c>)
132c: e7e2 b.n 12f4 <_sercom_get_default_pad+0x1c>
132e: 4832 ldr r0, [pc, #200] ; (13f8 <_sercom_get_default_pad+0x120>)
1330: e7e0 b.n 12f4 <_sercom_get_default_pad+0x1c>
1332: 4832 ldr r0, [pc, #200] ; (13fc <_sercom_get_default_pad+0x124>)
1334: e7de b.n 12f4 <_sercom_get_default_pad+0x1c>
1336: 4832 ldr r0, [pc, #200] ; (1400 <_sercom_get_default_pad+0x128>)
1338: e7dc b.n 12f4 <_sercom_get_default_pad+0x1c>
133a: 4832 ldr r0, [pc, #200] ; (1404 <_sercom_get_default_pad+0x12c>)
133c: e7da b.n 12f4 <_sercom_get_default_pad+0x1c>
133e: 4832 ldr r0, [pc, #200] ; (1408 <_sercom_get_default_pad+0x130>)
1340: e7d8 b.n 12f4 <_sercom_get_default_pad+0x1c>
1342: 2901 cmp r1, #1
1344: d007 beq.n 1356 <_sercom_get_default_pad+0x7e>
1346: 2900 cmp r1, #0
1348: d03f beq.n 13ca <_sercom_get_default_pad+0xf2>
134a: 2902 cmp r1, #2
134c: d005 beq.n 135a <_sercom_get_default_pad+0x82>
134e: 2903 cmp r1, #3
1350: d005 beq.n 135e <_sercom_get_default_pad+0x86>
return 0;
1352: 2000 movs r0, #0
1354: e7ce b.n 12f4 <_sercom_get_default_pad+0x1c>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
1356: 482d ldr r0, [pc, #180] ; (140c <_sercom_get_default_pad+0x134>)
1358: e7cc b.n 12f4 <_sercom_get_default_pad+0x1c>
135a: 482d ldr r0, [pc, #180] ; (1410 <_sercom_get_default_pad+0x138>)
135c: e7ca b.n 12f4 <_sercom_get_default_pad+0x1c>
135e: 482d ldr r0, [pc, #180] ; (1414 <_sercom_get_default_pad+0x13c>)
1360: e7c8 b.n 12f4 <_sercom_get_default_pad+0x1c>
1362: 2901 cmp r1, #1
1364: d007 beq.n 1376 <_sercom_get_default_pad+0x9e>
1366: 2900 cmp r1, #0
1368: d031 beq.n 13ce <_sercom_get_default_pad+0xf6>
136a: 2902 cmp r1, #2
136c: d005 beq.n 137a <_sercom_get_default_pad+0xa2>
136e: 2903 cmp r1, #3
1370: d005 beq.n 137e <_sercom_get_default_pad+0xa6>
return 0;
1372: 2000 movs r0, #0
1374: e7be b.n 12f4 <_sercom_get_default_pad+0x1c>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
1376: 4828 ldr r0, [pc, #160] ; (1418 <_sercom_get_default_pad+0x140>)
1378: e7bc b.n 12f4 <_sercom_get_default_pad+0x1c>
137a: 4828 ldr r0, [pc, #160] ; (141c <_sercom_get_default_pad+0x144>)
137c: e7ba b.n 12f4 <_sercom_get_default_pad+0x1c>
137e: 4828 ldr r0, [pc, #160] ; (1420 <_sercom_get_default_pad+0x148>)
1380: e7b8 b.n 12f4 <_sercom_get_default_pad+0x1c>
1382: 2901 cmp r1, #1
1384: d007 beq.n 1396 <_sercom_get_default_pad+0xbe>
1386: 2900 cmp r1, #0
1388: d023 beq.n 13d2 <_sercom_get_default_pad+0xfa>
138a: 2902 cmp r1, #2
138c: d005 beq.n 139a <_sercom_get_default_pad+0xc2>
138e: 2903 cmp r1, #3
1390: d005 beq.n 139e <_sercom_get_default_pad+0xc6>
return 0;
1392: 2000 movs r0, #0
1394: e7ae b.n 12f4 <_sercom_get_default_pad+0x1c>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
1396: 4823 ldr r0, [pc, #140] ; (1424 <_sercom_get_default_pad+0x14c>)
1398: e7ac b.n 12f4 <_sercom_get_default_pad+0x1c>
139a: 4823 ldr r0, [pc, #140] ; (1428 <_sercom_get_default_pad+0x150>)
139c: e7aa b.n 12f4 <_sercom_get_default_pad+0x1c>
139e: 4823 ldr r0, [pc, #140] ; (142c <_sercom_get_default_pad+0x154>)
13a0: e7a8 b.n 12f4 <_sercom_get_default_pad+0x1c>
13a2: 2901 cmp r1, #1
13a4: d007 beq.n 13b6 <_sercom_get_default_pad+0xde>
13a6: 2900 cmp r1, #0
13a8: d015 beq.n 13d6 <_sercom_get_default_pad+0xfe>
13aa: 2902 cmp r1, #2
13ac: d005 beq.n 13ba <_sercom_get_default_pad+0xe2>
13ae: 2903 cmp r1, #3
13b0: d005 beq.n 13be <_sercom_get_default_pad+0xe6>
return 0;
13b2: 2000 movs r0, #0
13b4: e79e b.n 12f4 <_sercom_get_default_pad+0x1c>
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
13b6: 481e ldr r0, [pc, #120] ; (1430 <_sercom_get_default_pad+0x158>)
13b8: e79c b.n 12f4 <_sercom_get_default_pad+0x1c>
13ba: 481e ldr r0, [pc, #120] ; (1434 <_sercom_get_default_pad+0x15c>)
13bc: e79a b.n 12f4 <_sercom_get_default_pad+0x1c>
13be: 481e ldr r0, [pc, #120] ; (1438 <_sercom_get_default_pad+0x160>)
13c0: e798 b.n 12f4 <_sercom_get_default_pad+0x1c>
13c2: 481e ldr r0, [pc, #120] ; (143c <_sercom_get_default_pad+0x164>)
13c4: e796 b.n 12f4 <_sercom_get_default_pad+0x1c>
13c6: 2003 movs r0, #3
13c8: e794 b.n 12f4 <_sercom_get_default_pad+0x1c>
13ca: 481d ldr r0, [pc, #116] ; (1440 <_sercom_get_default_pad+0x168>)
13cc: e792 b.n 12f4 <_sercom_get_default_pad+0x1c>
13ce: 481d ldr r0, [pc, #116] ; (1444 <_sercom_get_default_pad+0x16c>)
13d0: e790 b.n 12f4 <_sercom_get_default_pad+0x1c>
13d2: 481d ldr r0, [pc, #116] ; (1448 <_sercom_get_default_pad+0x170>)
13d4: e78e b.n 12f4 <_sercom_get_default_pad+0x1c>
13d6: 481d ldr r0, [pc, #116] ; (144c <_sercom_get_default_pad+0x174>)
13d8: e78c b.n 12f4 <_sercom_get_default_pad+0x1c>
13da: 46c0 nop ; (mov r8, r8)
13dc: 42001000 .word 0x42001000
13e0: 42001800 .word 0x42001800
13e4: 42001c00 .word 0x42001c00
13e8: 42001400 .word 0x42001400
13ec: 42000800 .word 0x42000800
13f0: 42000c00 .word 0x42000c00
13f4: 00050003 .word 0x00050003
13f8: 00060003 .word 0x00060003
13fc: 00070003 .word 0x00070003
1400: 00010003 .word 0x00010003
1404: 001e0003 .word 0x001e0003
1408: 001f0003 .word 0x001f0003
140c: 00090003 .word 0x00090003
1410: 000a0003 .word 0x000a0003
1414: 000b0003 .word 0x000b0003
1418: 00110003 .word 0x00110003
141c: 00120003 .word 0x00120003
1420: 00130003 .word 0x00130003
1424: 000d0003 .word 0x000d0003
1428: 000e0003 .word 0x000e0003
142c: 000f0003 .word 0x000f0003
1430: 00170003 .word 0x00170003
1434: 00180003 .word 0x00180003
1438: 00190003 .word 0x00190003
143c: 00040003 .word 0x00040003
1440: 00080003 .word 0x00080003
1444: 00100003 .word 0x00100003
1448: 000c0003 .word 0x000c0003
144c: 00160003 .word 0x00160003
00001450 <_sercom_get_sercom_inst_index>:
*
* \return Index of given instance.
*/
uint8_t _sercom_get_sercom_inst_index(
Sercom *const sercom_instance)
{
1450: b530 push {r4, r5, lr}
1452: b087 sub sp, #28
/* Save all available SERCOM instances for compare */
Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
1454: 4b0b ldr r3, [pc, #44] ; (1484 <_sercom_get_sercom_inst_index+0x34>)
1456: 466a mov r2, sp
1458: cb32 ldmia r3!, {r1, r4, r5}
145a: c232 stmia r2!, {r1, r4, r5}
145c: cb32 ldmia r3!, {r1, r4, r5}
145e: c232 stmia r2!, {r1, r4, r5}
/* Find index for sercom instance */
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
1460: 9b00 ldr r3, [sp, #0]
1462: 4283 cmp r3, r0
1464: d00b beq.n 147e <_sercom_get_sercom_inst_index+0x2e>
1466: 2301 movs r3, #1
1468: 009a lsls r2, r3, #2
146a: 4669 mov r1, sp
146c: 5852 ldr r2, [r2, r1]
146e: 4282 cmp r2, r0
1470: d006 beq.n 1480 <_sercom_get_sercom_inst_index+0x30>
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
1472: 3301 adds r3, #1
1474: 2b06 cmp r3, #6
1476: d1f7 bne.n 1468 <_sercom_get_sercom_inst_index+0x18>
}
}
/* Invalid data given */
Assert(false);
return 0;
1478: 2000 movs r0, #0
}
147a: b007 add sp, #28
147c: bd30 pop {r4, r5, pc}
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
147e: 2300 movs r3, #0
return i;
1480: b2d8 uxtb r0, r3
1482: e7fa b.n 147a <_sercom_get_sercom_inst_index+0x2a>
1484: 00004894 .word 0x00004894
00001488 <_sercom_default_handler>:
*/
static void _sercom_default_handler(
const uint8_t instance)
{
Assert(false);
}
1488: 4770 bx lr
...
0000148c <_sercom_set_handler>:
* \param[in] interrupt_handler Pointer to instance callback handler.
*/
void _sercom_set_handler(
const uint8_t instance,
const sercom_handler_t interrupt_handler)
{
148c: b5f0 push {r4, r5, r6, r7, lr}
/* Initialize handlers with default handler and device instances with 0 */
if (_handler_table_initialized == false) {
148e: 4b0a ldr r3, [pc, #40] ; (14b8 <_sercom_set_handler+0x2c>)
1490: 781b ldrb r3, [r3, #0]
1492: 2b00 cmp r3, #0
1494: d10c bne.n 14b0 <_sercom_set_handler+0x24>
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
_sercom_interrupt_handlers[i] = &_sercom_default_handler;
1496: 4f09 ldr r7, [pc, #36] ; (14bc <_sercom_set_handler+0x30>)
1498: 4e09 ldr r6, [pc, #36] ; (14c0 <_sercom_set_handler+0x34>)
_sercom_instances[i] = NULL;
149a: 4d0a ldr r5, [pc, #40] ; (14c4 <_sercom_set_handler+0x38>)
149c: 2400 movs r4, #0
_sercom_interrupt_handlers[i] = &_sercom_default_handler;
149e: 51de str r6, [r3, r7]
_sercom_instances[i] = NULL;
14a0: 195a adds r2, r3, r5
14a2: 6014 str r4, [r2, #0]
14a4: 3304 adds r3, #4
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
14a6: 2b18 cmp r3, #24
14a8: d1f9 bne.n 149e <_sercom_set_handler+0x12>
}
_handler_table_initialized = true;
14aa: 2201 movs r2, #1
14ac: 4b02 ldr r3, [pc, #8] ; (14b8 <_sercom_set_handler+0x2c>)
14ae: 701a strb r2, [r3, #0]
}
/* Save interrupt handler */
_sercom_interrupt_handlers[instance] = interrupt_handler;
14b0: 0080 lsls r0, r0, #2
14b2: 4b02 ldr r3, [pc, #8] ; (14bc <_sercom_set_handler+0x30>)
14b4: 50c1 str r1, [r0, r3]
}
14b6: bdf0 pop {r4, r5, r6, r7, pc}
14b8: 2000008a .word 0x2000008a
14bc: 2000008c .word 0x2000008c
14c0: 00001489 .word 0x00001489
14c4: 20000244 .word 0x20000244
000014c8 <_sercom_get_interrupt_vector>:
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM6
* \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
*/
enum system_interrupt_vector _sercom_get_interrupt_vector(
Sercom *const sercom_instance)
{
14c8: b500 push {lr}
14ca: b083 sub sp, #12
const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
14cc: 2309 movs r3, #9
14ce: 466a mov r2, sp
14d0: 7013 strb r3, [r2, #0]
14d2: 3301 adds r3, #1
14d4: 7053 strb r3, [r2, #1]
14d6: 3301 adds r3, #1
14d8: 7093 strb r3, [r2, #2]
14da: 3301 adds r3, #1
14dc: 70d3 strb r3, [r2, #3]
14de: 3301 adds r3, #1
14e0: 7113 strb r3, [r2, #4]
14e2: 3301 adds r3, #1
14e4: 7153 strb r3, [r2, #5]
{
MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
};
/* Retrieve the index of the SERCOM being requested */
uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
14e6: 4b03 ldr r3, [pc, #12] ; (14f4 <_sercom_get_interrupt_vector+0x2c>)
14e8: 4798 blx r3
/* Get the vector number from the lookup table for the requested SERCOM */
return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
14ea: 466b mov r3, sp
14ec: 5618 ldrsb r0, [r3, r0]
}
14ee: b003 add sp, #12
14f0: bd00 pop {pc}
14f2: 46c0 nop ; (mov r8, r8)
14f4: 00001451 .word 0x00001451
000014f8 <SERCOM0_Handler>:
/** Auto-generate a set of interrupt handlers for each SERCOM in the device */
MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~)
14f8: b510 push {r4, lr}
14fa: 4b02 ldr r3, [pc, #8] ; (1504 <SERCOM0_Handler+0xc>)
14fc: 681b ldr r3, [r3, #0]
14fe: 2000 movs r0, #0
1500: 4798 blx r3
1502: bd10 pop {r4, pc}
1504: 2000008c .word 0x2000008c
00001508 <SERCOM1_Handler>:
1508: b510 push {r4, lr}
150a: 4b02 ldr r3, [pc, #8] ; (1514 <SERCOM1_Handler+0xc>)
150c: 685b ldr r3, [r3, #4]
150e: 2001 movs r0, #1
1510: 4798 blx r3
1512: bd10 pop {r4, pc}
1514: 2000008c .word 0x2000008c
00001518 <SERCOM2_Handler>:
1518: b510 push {r4, lr}
151a: 4b02 ldr r3, [pc, #8] ; (1524 <SERCOM2_Handler+0xc>)
151c: 689b ldr r3, [r3, #8]
151e: 2002 movs r0, #2
1520: 4798 blx r3
1522: bd10 pop {r4, pc}
1524: 2000008c .word 0x2000008c
00001528 <SERCOM3_Handler>:
1528: b510 push {r4, lr}
152a: 4b02 ldr r3, [pc, #8] ; (1534 <SERCOM3_Handler+0xc>)
152c: 68db ldr r3, [r3, #12]
152e: 2003 movs r0, #3
1530: 4798 blx r3
1532: bd10 pop {r4, pc}
1534: 2000008c .word 0x2000008c
00001538 <SERCOM4_Handler>:
1538: b510 push {r4, lr}
153a: 4b02 ldr r3, [pc, #8] ; (1544 <SERCOM4_Handler+0xc>)
153c: 691b ldr r3, [r3, #16]
153e: 2004 movs r0, #4
1540: 4798 blx r3
1542: bd10 pop {r4, pc}
1544: 2000008c .word 0x2000008c
00001548 <SERCOM5_Handler>:
1548: b510 push {r4, lr}
154a: 4b02 ldr r3, [pc, #8] ; (1554 <SERCOM5_Handler+0xc>)
154c: 695b ldr r3, [r3, #20]
154e: 2005 movs r0, #5
1550: 4798 blx r3
1552: bd10 pop {r4, pc}
1554: 2000008c .word 0x2000008c
00001558 <cpu_irq_enter_critical>:
volatile bool g_interrupt_enabled = true;
#endif
void cpu_irq_enter_critical(void)
{
if (cpu_irq_critical_section_counter == 0) {
1558: 4b0c ldr r3, [pc, #48] ; (158c <cpu_irq_enter_critical+0x34>)
155a: 681b ldr r3, [r3, #0]
155c: 2b00 cmp r3, #0
155e: d106 bne.n 156e <cpu_irq_enter_critical+0x16>
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
1560: f3ef 8310 mrs r3, PRIMASK
if (cpu_irq_is_enabled()) {
1564: 2b00 cmp r3, #0
1566: d007 beq.n 1578 <cpu_irq_enter_critical+0x20>
cpu_irq_disable();
cpu_irq_prev_interrupt_state = true;
} else {
/* Make sure the to save the prev state as false */
cpu_irq_prev_interrupt_state = false;
1568: 2200 movs r2, #0
156a: 4b09 ldr r3, [pc, #36] ; (1590 <cpu_irq_enter_critical+0x38>)
156c: 701a strb r2, [r3, #0]
}
}
cpu_irq_critical_section_counter++;
156e: 4a07 ldr r2, [pc, #28] ; (158c <cpu_irq_enter_critical+0x34>)
1570: 6813 ldr r3, [r2, #0]
1572: 3301 adds r3, #1
1574: 6013 str r3, [r2, #0]
}
1576: 4770 bx lr
__ASM volatile ("cpsid i" : : : "memory");
1578: b672 cpsid i
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__STATIC_FORCEINLINE void __DMB(void)
{
__ASM volatile ("dmb 0xF":::"memory");
157a: f3bf 8f5f dmb sy
cpu_irq_disable();
157e: 2200 movs r2, #0
1580: 4b04 ldr r3, [pc, #16] ; (1594 <cpu_irq_enter_critical+0x3c>)
1582: 701a strb r2, [r3, #0]
cpu_irq_prev_interrupt_state = true;
1584: 3201 adds r2, #1
1586: 4b02 ldr r3, [pc, #8] ; (1590 <cpu_irq_enter_critical+0x38>)
1588: 701a strb r2, [r3, #0]
158a: e7f0 b.n 156e <cpu_irq_enter_critical+0x16>
158c: 200000a4 .word 0x200000a4
1590: 200000a8 .word 0x200000a8
1594: 20000000 .word 0x20000000
00001598 <cpu_irq_leave_critical>:
void cpu_irq_leave_critical(void)
{
/* Check if the user is trying to leave a critical section when not in a critical section */
Assert(cpu_irq_critical_section_counter > 0);
cpu_irq_critical_section_counter--;
1598: 4b08 ldr r3, [pc, #32] ; (15bc <cpu_irq_leave_critical+0x24>)
159a: 681a ldr r2, [r3, #0]
159c: 3a01 subs r2, #1
159e: 601a str r2, [r3, #0]
/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
was enabled when entering critical state */
if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
15a0: 681b ldr r3, [r3, #0]
15a2: 2b00 cmp r3, #0
15a4: d109 bne.n 15ba <cpu_irq_leave_critical+0x22>
15a6: 4b06 ldr r3, [pc, #24] ; (15c0 <cpu_irq_leave_critical+0x28>)
15a8: 781b ldrb r3, [r3, #0]
15aa: 2b00 cmp r3, #0
15ac: d005 beq.n 15ba <cpu_irq_leave_critical+0x22>
cpu_irq_enable();
15ae: 2201 movs r2, #1
15b0: 4b04 ldr r3, [pc, #16] ; (15c4 <cpu_irq_leave_critical+0x2c>)
15b2: 701a strb r2, [r3, #0]
15b4: f3bf 8f5f dmb sy
__ASM volatile ("cpsie i" : : : "memory");
15b8: b662 cpsie i
}
}
15ba: 4770 bx lr
15bc: 200000a4 .word 0x200000a4
15c0: 200000a8 .word 0x200000a8
15c4: 20000000 .word 0x20000000
000015c8 <system_board_init>:
void board_init(void);
# pragma weak board_init=system_board_init
#endif
void system_board_init(void)
{
15c8: b5f0 push {r4, r5, r6, r7, lr}
15ca: b083 sub sp, #12
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->direction = PORT_PIN_DIR_INPUT;
config->input_pull = PORT_PIN_PULL_UP;
15cc: ac01 add r4, sp, #4
15ce: 2501 movs r5, #1
15d0: 7065 strb r5, [r4, #1]
config->powersave = false;
15d2: 2700 movs r7, #0
15d4: 70a7 strb r7, [r4, #2]
struct port_config pin_conf;
port_get_config_defaults(&pin_conf);
/* Configure LEDs as outputs, turn them off */
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
15d6: 7025 strb r5, [r4, #0]
port_pin_set_config(LED_0_PIN, &pin_conf);
15d8: 0021 movs r1, r4
15da: 203e movs r0, #62 ; 0x3e
15dc: 4e06 ldr r6, [pc, #24] ; (15f8 <system_board_init+0x30>)
15de: 47b0 blx r6
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
/* Set the pin to high or low atomically based on the requested level */
if (level) {
port_base->OUTSET.reg = pin_mask;
15e0: 2280 movs r2, #128 ; 0x80
15e2: 05d2 lsls r2, r2, #23
15e4: 4b05 ldr r3, [pc, #20] ; (15fc <system_board_init+0x34>)
15e6: 619a str r2, [r3, #24]
port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
/* Set buttons as inputs */
pin_conf.direction = PORT_PIN_DIR_INPUT;
15e8: 7027 strb r7, [r4, #0]
pin_conf.input_pull = PORT_PIN_PULL_UP;
15ea: 7065 strb r5, [r4, #1]
port_pin_set_config(BUTTON_0_PIN, &pin_conf);
15ec: 0021 movs r1, r4
15ee: 200f movs r0, #15
15f0: 47b0 blx r6
port_pin_set_output_level(AT86RFX_RST_PIN, true);
port_pin_set_output_level(AT86RFX_SLP_PIN, true);
pin_conf.direction = PORT_PIN_DIR_INPUT;
port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
#endif
}
15f2: b003 add sp, #12
15f4: bdf0 pop {r4, r5, r6, r7, pc}
15f6: 46c0 nop ; (mov r8, r8)
15f8: 00001601 .word 0x00001601
15fc: 41004480 .word 0x41004480
00001600 <port_pin_set_config>:
* \param[in] config Configuration settings for the pin
*/
void port_pin_set_config(
const uint8_t gpio_pin,
const struct port_config *const config)
{
1600: b500 push {lr}
1602: b083 sub sp, #12
config->mux_position = SYSTEM_PINMUX_GPIO;
1604: ab01 add r3, sp, #4
1606: 2280 movs r2, #128 ; 0x80
1608: 701a strb r2, [r3, #0]
struct system_pinmux_config pinmux_config;
system_pinmux_get_config_defaults(&pinmux_config);
pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;
160a: 780a ldrb r2, [r1, #0]
160c: 705a strb r2, [r3, #1]
pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;
160e: 784a ldrb r2, [r1, #1]
1610: 709a strb r2, [r3, #2]
pinmux_config.powersave = config->powersave;
1612: 788a ldrb r2, [r1, #2]
1614: 70da strb r2, [r3, #3]
system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
1616: 0019 movs r1, r3
1618: 4b01 ldr r3, [pc, #4] ; (1620 <port_pin_set_config+0x20>)
161a: 4798 blx r3
}
161c: b003 add sp, #12
161e: bd00 pop {pc}
1620: 00001b65 .word 0x00001b65
00001624 <system_clock_source_get_hz>:
*
* \returns Frequency of the given clock source, in Hz.
*/
uint32_t system_clock_source_get_hz(
const enum system_clock_source clock_source)
{
1624: b510 push {r4, lr}
switch (clock_source) {
1626: 2808 cmp r0, #8
1628: d803 bhi.n 1632 <system_clock_source_get_hz+0xe>
162a: 0080 lsls r0, r0, #2
162c: 4b1c ldr r3, [pc, #112] ; (16a0 <system_clock_source_get_hz+0x7c>)
162e: 581b ldr r3, [r3, r0]
1630: 469f mov pc, r3
return _system_clock_inst.dpll.frequency;
#endif
default:
return 0;
1632: 2000 movs r0, #0
1634: e032 b.n 169c <system_clock_source_get_hz+0x78>
return _system_clock_inst.xosc.frequency;
1636: 4b1b ldr r3, [pc, #108] ; (16a4 <system_clock_source_get_hz+0x80>)
1638: 6918 ldr r0, [r3, #16]
163a: e02f b.n 169c <system_clock_source_get_hz+0x78>
return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
163c: 4b1a ldr r3, [pc, #104] ; (16a8 <system_clock_source_get_hz+0x84>)
163e: 6a1b ldr r3, [r3, #32]
1640: 059b lsls r3, r3, #22
1642: 0f9b lsrs r3, r3, #30
1644: 4819 ldr r0, [pc, #100] ; (16ac <system_clock_source_get_hz+0x88>)
1646: 40d8 lsrs r0, r3
1648: e028 b.n 169c <system_clock_source_get_hz+0x78>
return _system_clock_inst.xosc32k.frequency;
164a: 4b16 ldr r3, [pc, #88] ; (16a4 <system_clock_source_get_hz+0x80>)
164c: 6958 ldr r0, [r3, #20]
164e: e025 b.n 169c <system_clock_source_get_hz+0x78>
if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
1650: 4b14 ldr r3, [pc, #80] ; (16a4 <system_clock_source_get_hz+0x80>)
1652: 681b ldr r3, [r3, #0]
return 0;
1654: 2000 movs r0, #0
if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
1656: 079b lsls r3, r3, #30
1658: d520 bpl.n 169c <system_clock_source_get_hz+0x78>
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
165a: 4913 ldr r1, [pc, #76] ; (16a8 <system_clock_source_get_hz+0x84>)
165c: 2210 movs r2, #16
165e: 68cb ldr r3, [r1, #12]
1660: 421a tst r2, r3
1662: d0fc beq.n 165e <system_clock_source_get_hz+0x3a>
switch(_system_clock_inst.dfll.control &
1664: 4b0f ldr r3, [pc, #60] ; (16a4 <system_clock_source_get_hz+0x80>)
1666: 681a ldr r2, [r3, #0]
1668: 2324 movs r3, #36 ; 0x24
166a: 4013 ands r3, r2
166c: 2b04 cmp r3, #4
166e: d001 beq.n 1674 <system_clock_source_get_hz+0x50>
return 48000000UL;
1670: 480f ldr r0, [pc, #60] ; (16b0 <system_clock_source_get_hz+0x8c>)
1672: e013 b.n 169c <system_clock_source_get_hz+0x78>
return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
1674: 2000 movs r0, #0
1676: 4b0f ldr r3, [pc, #60] ; (16b4 <system_clock_source_get_hz+0x90>)
1678: 4798 blx r3
(_system_clock_inst.dfll.mul & 0xffff);
167a: 4b0a ldr r3, [pc, #40] ; (16a4 <system_clock_source_get_hz+0x80>)
167c: 689b ldr r3, [r3, #8]
167e: 041b lsls r3, r3, #16
1680: 0c1b lsrs r3, r3, #16
return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
1682: 4358 muls r0, r3
1684: e00a b.n 169c <system_clock_source_get_hz+0x78>
if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
1686: 2350 movs r3, #80 ; 0x50
1688: 4a07 ldr r2, [pc, #28] ; (16a8 <system_clock_source_get_hz+0x84>)
168a: 5cd3 ldrb r3, [r2, r3]
return 0;
168c: 2000 movs r0, #0
if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
168e: 075b lsls r3, r3, #29
1690: d504 bpl.n 169c <system_clock_source_get_hz+0x78>
return _system_clock_inst.dpll.frequency;
1692: 4b04 ldr r3, [pc, #16] ; (16a4 <system_clock_source_get_hz+0x80>)
1694: 68d8 ldr r0, [r3, #12]
1696: e001 b.n 169c <system_clock_source_get_hz+0x78>
return 32768UL;
1698: 2080 movs r0, #128 ; 0x80
169a: 0200 lsls r0, r0, #8
}
}
169c: bd10 pop {r4, pc}
169e: 46c0 nop ; (mov r8, r8)
16a0: 000048ac .word 0x000048ac
16a4: 200000ac .word 0x200000ac
16a8: 40000800 .word 0x40000800
16ac: 007a1200 .word 0x007a1200
16b0: 02dc6c00 .word 0x02dc6c00
16b4: 00001a89 .word 0x00001a89
000016b8 <system_clock_source_osc8m_set_config>:
*
* \param[in] config OSC8M configuration structure containing the new config
*/
void system_clock_source_osc8m_set_config(
struct system_clock_source_osc8m_config *const config)
{
16b8: b570 push {r4, r5, r6, lr}
SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
16ba: 490c ldr r1, [pc, #48] ; (16ec <system_clock_source_osc8m_set_config+0x34>)
16bc: 6a0b ldr r3, [r1, #32]
/* Use temporary struct to reduce register access */
temp.bit.PRESC = config->prescaler;
16be: 7804 ldrb r4, [r0, #0]
temp.bit.ONDEMAND = config->on_demand;
16c0: 7885 ldrb r5, [r0, #2]
temp.bit.RUNSTDBY = config->run_in_standby;
SYSCTRL->OSC8M = temp;
16c2: 7840 ldrb r0, [r0, #1]
16c4: 2201 movs r2, #1
16c6: 4010 ands r0, r2
16c8: 0180 lsls r0, r0, #6
16ca: 2640 movs r6, #64 ; 0x40
16cc: 43b3 bics r3, r6
16ce: 4303 orrs r3, r0
16d0: 402a ands r2, r5
16d2: 01d2 lsls r2, r2, #7
16d4: 2080 movs r0, #128 ; 0x80
16d6: 4383 bics r3, r0
16d8: 4313 orrs r3, r2
16da: 2203 movs r2, #3
16dc: 4022 ands r2, r4
16de: 0212 lsls r2, r2, #8
16e0: 4803 ldr r0, [pc, #12] ; (16f0 <system_clock_source_osc8m_set_config+0x38>)
16e2: 4003 ands r3, r0
16e4: 4313 orrs r3, r2
16e6: 620b str r3, [r1, #32]
}
16e8: bd70 pop {r4, r5, r6, pc}
16ea: 46c0 nop ; (mov r8, r8)
16ec: 40000800 .word 0x40000800
16f0: fffffcff .word 0xfffffcff
000016f4 <system_clock_source_enable>:
* device
*/
enum status_code system_clock_source_enable(
const enum system_clock_source clock_source)
{
switch (clock_source) {
16f4: 2808 cmp r0, #8
16f6: d803 bhi.n 1700 <system_clock_source_enable+0xc>
16f8: 0080 lsls r0, r0, #2
16fa: 4b25 ldr r3, [pc, #148] ; (1790 <system_clock_source_enable+0x9c>)
16fc: 581b ldr r3, [r3, r0]
16fe: 469f mov pc, r3
/* Always enabled */
return STATUS_OK;
default:
Assert(false);
return STATUS_ERR_INVALID_ARG;
1700: 2017 movs r0, #23
1702: e044 b.n 178e <system_clock_source_enable+0x9a>
SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
1704: 4a23 ldr r2, [pc, #140] ; (1794 <system_clock_source_enable+0xa0>)
1706: 6a13 ldr r3, [r2, #32]
1708: 2102 movs r1, #2
170a: 430b orrs r3, r1
170c: 6213 str r3, [r2, #32]
return STATUS_OK;
170e: 2000 movs r0, #0
1710: e03d b.n 178e <system_clock_source_enable+0x9a>
SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
1712: 4a20 ldr r2, [pc, #128] ; (1794 <system_clock_source_enable+0xa0>)
1714: 6993 ldr r3, [r2, #24]
1716: 2102 movs r1, #2
1718: 430b orrs r3, r1
171a: 6193 str r3, [r2, #24]
}
return STATUS_OK;
171c: 2000 movs r0, #0
break;
171e: e036 b.n 178e <system_clock_source_enable+0x9a>
SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
1720: 4a1c ldr r2, [pc, #112] ; (1794 <system_clock_source_enable+0xa0>)
1722: 8a13 ldrh r3, [r2, #16]
1724: 2102 movs r1, #2
1726: 430b orrs r3, r1
1728: 8213 strh r3, [r2, #16]
return STATUS_OK;
172a: 2000 movs r0, #0
break;
172c: e02f b.n 178e <system_clock_source_enable+0x9a>
SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
172e: 4a19 ldr r2, [pc, #100] ; (1794 <system_clock_source_enable+0xa0>)
1730: 8a93 ldrh r3, [r2, #20]
1732: 2102 movs r1, #2
1734: 430b orrs r3, r1
1736: 8293 strh r3, [r2, #20]
return STATUS_OK;
1738: 2000 movs r0, #0
break;
173a: e028 b.n 178e <system_clock_source_enable+0x9a>
_system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
173c: 4916 ldr r1, [pc, #88] ; (1798 <system_clock_source_enable+0xa4>)
173e: 680b ldr r3, [r1, #0]
1740: 2202 movs r2, #2
1742: 4313 orrs r3, r2
1744: 600b str r3, [r1, #0]
SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
1746: 4b13 ldr r3, [pc, #76] ; (1794 <system_clock_source_enable+0xa0>)
1748: 849a strh r2, [r3, #36] ; 0x24
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
174a: 0019 movs r1, r3
174c: 320e adds r2, #14
174e: 68cb ldr r3, [r1, #12]
1750: 421a tst r2, r3
1752: d0fc beq.n 174e <system_clock_source_enable+0x5a>
SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
1754: 4a10 ldr r2, [pc, #64] ; (1798 <system_clock_source_enable+0xa4>)
1756: 6891 ldr r1, [r2, #8]
1758: 4b0e ldr r3, [pc, #56] ; (1794 <system_clock_source_enable+0xa0>)
175a: 62d9 str r1, [r3, #44] ; 0x2c
SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
175c: 6852 ldr r2, [r2, #4]
175e: 629a str r2, [r3, #40] ; 0x28
SYSCTRL->DFLLCTRL.reg = 0;
1760: 2200 movs r2, #0
1762: 849a strh r2, [r3, #36] ; 0x24
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
1764: 0019 movs r1, r3
1766: 3210 adds r2, #16
1768: 68cb ldr r3, [r1, #12]
176a: 421a tst r2, r3
176c: d0fc beq.n 1768 <system_clock_source_enable+0x74>
SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
176e: 4b0a ldr r3, [pc, #40] ; (1798 <system_clock_source_enable+0xa4>)
1770: 681b ldr r3, [r3, #0]
1772: b29b uxth r3, r3
1774: 4a07 ldr r2, [pc, #28] ; (1794 <system_clock_source_enable+0xa0>)
1776: 8493 strh r3, [r2, #36] ; 0x24
return STATUS_OK;
1778: 2000 movs r0, #0
177a: e008 b.n 178e <system_clock_source_enable+0x9a>
SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
177c: 4905 ldr r1, [pc, #20] ; (1794 <system_clock_source_enable+0xa0>)
177e: 2244 movs r2, #68 ; 0x44
1780: 5c8b ldrb r3, [r1, r2]
1782: 2002 movs r0, #2
1784: 4303 orrs r3, r0
1786: 548b strb r3, [r1, r2]
return STATUS_OK;
1788: 2000 movs r0, #0
break;
178a: e000 b.n 178e <system_clock_source_enable+0x9a>
return STATUS_OK;
178c: 2000 movs r0, #0
}
178e: 4770 bx lr
1790: 000048d0 .word 0x000048d0
1794: 40000800 .word 0x40000800
1798: 200000ac .word 0x200000ac
0000179c <system_clock_init>:
* \note OSC8M is always enabled and if user selects other clocks for GCLK generators,
* the OSC8M default enable can be disabled after system_clock_init. Make sure the
* clock switch successfully before disabling OSC8M.
*/
void system_clock_init(void)
{
179c: b530 push {r4, r5, lr}
179e: b085 sub sp, #20
/* Various bits in the INTFLAG register can be set to one at startup.
This will ensure that these bits are cleared */
SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
17a0: 22c2 movs r2, #194 ; 0xc2
17a2: 00d2 lsls r2, r2, #3
17a4: 4b1a ldr r3, [pc, #104] ; (1810 <system_clock_init+0x74>)
17a6: 609a str r2, [r3, #8]
static inline void system_flash_set_waitstates(uint8_t wait_states)
{
Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
NVMCTRL->CTRLB.bit.RWS = wait_states;
17a8: 4a1a ldr r2, [pc, #104] ; (1814 <system_clock_init+0x78>)
17aa: 6853 ldr r3, [r2, #4]
17ac: 211e movs r1, #30
17ae: 438b bics r3, r1
17b0: 6053 str r3, [r2, #4]
gclk_conf.source_generator = GCLK_GENERATOR_1;
17b2: 2301 movs r3, #1
17b4: 466a mov r2, sp
17b6: 7013 strb r3, [r2, #0]
for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
17b8: 2400 movs r4, #0
system_gclk_chan_set_config(gclk_id, &gclk_conf);
17ba: 4d17 ldr r5, [pc, #92] ; (1818 <system_clock_init+0x7c>)
17bc: b2e0 uxtb r0, r4
17be: 4669 mov r1, sp
17c0: 47a8 blx r5
for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
17c2: 3401 adds r4, #1
17c4: 2c25 cmp r4, #37 ; 0x25
17c6: d1f9 bne.n 17bc <system_clock_init+0x20>
config->run_in_standby = false;
17c8: a803 add r0, sp, #12
17ca: 2400 movs r4, #0
17cc: 7044 strb r4, [r0, #1]
config->on_demand = true;
17ce: 2501 movs r5, #1
17d0: 7085 strb r5, [r0, #2]
/* OSC8M */
struct system_clock_source_osc8m_config osc8m_conf;
system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER;
17d2: 7004 strb r4, [r0, #0]
osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND;
osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
system_clock_source_osc8m_set_config(&osc8m_conf);
17d4: 4b11 ldr r3, [pc, #68] ; (181c <system_clock_init+0x80>)
17d6: 4798 blx r3
system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
17d8: 2006 movs r0, #6
17da: 4b11 ldr r3, [pc, #68] ; (1820 <system_clock_init+0x84>)
17dc: 4798 blx r3
/* GCLK */
#if CONF_CLOCK_CONFIGURE_GCLK == true
system_gclk_init();
17de: 4b11 ldr r3, [pc, #68] ; (1824 <system_clock_init+0x88>)
17e0: 4798 blx r3
PM->CPUSEL.reg = (uint32_t)divider;
17e2: 4b11 ldr r3, [pc, #68] ; (1828 <system_clock_init+0x8c>)
17e4: 721c strb r4, [r3, #8]
PM->APBASEL.reg = (uint32_t)divider;
17e6: 725c strb r4, [r3, #9]
PM->APBBSEL.reg = (uint32_t)divider;
17e8: 729c strb r4, [r3, #10]
PM->APBCSEL.reg = (uint32_t)divider;
17ea: 72dc strb r4, [r3, #11]
{
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->division_factor = 1;
17ec: 9501 str r5, [sp, #4]
config->high_when_disabled = false;
17ee: 466b mov r3, sp
17f0: 705c strb r4, [r3, #1]
#if SAML21 || SAML22 || SAMR30 || SAMR34 || SAMR35
config->source_clock = GCLK_SOURCE_OSC16M;
#elif (SAMC20) || (SAMC21)
config->source_clock = GCLK_SOURCE_OSC48M;
#else
config->source_clock = GCLK_SOURCE_OSC8M;
17f2: 2306 movs r3, #6
17f4: 466a mov r2, sp
17f6: 7013 strb r3, [r2, #0]
#endif
config->run_in_standby = false;
17f8: 7214 strb r4, [r2, #8]
config->output_enable = false;
17fa: 7254 strb r4, [r2, #9]
system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER);
/* GCLK 0 */
#if CONF_CLOCK_CONFIGURE_GCLK == true
/* Configure the main GCLK last as it might depend on other generators */
_CONF_CLOCK_GCLK_CONFIG(0, ~);
17fc: 4669 mov r1, sp
17fe: 2000 movs r0, #0
1800: 4b0a ldr r3, [pc, #40] ; (182c <system_clock_init+0x90>)
1802: 4798 blx r3
1804: 2000 movs r0, #0
1806: 4b0a ldr r3, [pc, #40] ; (1830 <system_clock_init+0x94>)
1808: 4798 blx r3
#endif
}
180a: b005 add sp, #20
180c: bd30 pop {r4, r5, pc}
180e: 46c0 nop ; (mov r8, r8)
1810: 40000800 .word 0x40000800
1814: 41004000 .word 0x41004000
1818: 00001a6d .word 0x00001a6d
181c: 000016b9 .word 0x000016b9
1820: 000016f5 .word 0x000016f5
1824: 00001835 .word 0x00001835
1828: 40000400 .word 0x40000400
182c: 00001859 .word 0x00001859
1830: 00001911 .word 0x00001911
00001834 <system_gclk_init>:
PM->APBAMASK.reg |= mask;
1834: 4a06 ldr r2, [pc, #24] ; (1850 <system_gclk_init+0x1c>)
1836: 6993 ldr r3, [r2, #24]
1838: 2108 movs r1, #8
183a: 430b orrs r3, r1
183c: 6193 str r3, [r2, #24]
{
/* Turn on the digital interface clock */
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
/* Software reset the module to ensure it is re-initialized correctly */
GCLK->CTRL.reg = GCLK_CTRL_SWRST;
183e: 2201 movs r2, #1
1840: 4b04 ldr r3, [pc, #16] ; (1854 <system_gclk_init+0x20>)
1842: 701a strb r2, [r3, #0]
while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
1844: 0019 movs r1, r3
1846: 780b ldrb r3, [r1, #0]
1848: 4213 tst r3, r2
184a: d1fc bne.n 1846 <system_gclk_init+0x12>
/* Wait for reset to complete */
}
}
184c: 4770 bx lr
184e: 46c0 nop ; (mov r8, r8)
1850: 40000400 .word 0x40000400
1854: 40000c00 .word 0x40000c00
00001858 <system_gclk_gen_set_config>:
* \param[in] config Configuration settings for the generator
*/
void system_gclk_gen_set_config(
const uint8_t generator,
struct system_gclk_gen_config *const config)
{
1858: b570 push {r4, r5, r6, lr}
185a: 0006 movs r6, r0
/* Sanity check arguments */
Assert(config);
/* Cache new register configurations to minimize sync requirements. */
uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
185c: 0004 movs r4, r0
uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos);
/* Select the requested source clock for the generator */
new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
185e: 780d ldrb r5, [r1, #0]
1860: 022d lsls r5, r5, #8
1862: 4305 orrs r5, r0
/* Configure the clock to be either high or low when disabled */
if (config->high_when_disabled) {
1864: 784b ldrb r3, [r1, #1]
1866: 2b00 cmp r3, #0
1868: d002 beq.n 1870 <system_gclk_gen_set_config+0x18>
new_genctrl_config |= GCLK_GENCTRL_OOV;
186a: 2380 movs r3, #128 ; 0x80
186c: 02db lsls r3, r3, #11
186e: 431d orrs r5, r3
}
/* Configure if the clock output to I/O pin should be enabled. */
if (config->output_enable) {
1870: 7a4b ldrb r3, [r1, #9]
1872: 2b00 cmp r3, #0
1874: d002 beq.n 187c <system_gclk_gen_set_config+0x24>
new_genctrl_config |= GCLK_GENCTRL_OE;
1876: 2380 movs r3, #128 ; 0x80
1878: 031b lsls r3, r3, #12
187a: 431d orrs r5, r3
}
/* Set division factor */
if (config->division_factor > 1) {
187c: 6848 ldr r0, [r1, #4]
187e: 2801 cmp r0, #1
1880: d910 bls.n 18a4 <system_gclk_gen_set_config+0x4c>
/* Check if division is a power of two */
if (((config->division_factor & (config->division_factor - 1)) == 0)) {
1882: 1e43 subs r3, r0, #1
1884: 4218 tst r0, r3
1886: d134 bne.n 18f2 <system_gclk_gen_set_config+0x9a>
* register */
uint32_t div2_count = 0;
uint32_t mask;
for (mask = (1UL << 1); mask < config->division_factor;
1888: 2802 cmp r0, #2
188a: d930 bls.n 18ee <system_gclk_gen_set_config+0x96>
188c: 2302 movs r3, #2
188e: 2200 movs r2, #0
mask <<= 1) {
div2_count++;
1890: 3201 adds r2, #1
mask <<= 1) {
1892: 005b lsls r3, r3, #1
for (mask = (1UL << 1); mask < config->division_factor;
1894: 4298 cmp r0, r3
1896: d8fb bhi.n 1890 <system_gclk_gen_set_config+0x38>
}
/* Set binary divider power of 2 division factor */
new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos;
1898: 0212 lsls r2, r2, #8
189a: 4332 orrs r2, r6
189c: 0014 movs r4, r2
new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
189e: 2380 movs r3, #128 ; 0x80
18a0: 035b lsls r3, r3, #13
18a2: 431d orrs r5, r3
}
}
/* Enable or disable the clock in standby mode */
if (config->run_in_standby) {
18a4: 7a0b ldrb r3, [r1, #8]
18a6: 2b00 cmp r3, #0
18a8: d002 beq.n 18b0 <system_gclk_gen_set_config+0x58>
new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
18aa: 2380 movs r3, #128 ; 0x80
18ac: 039b lsls r3, r3, #14
18ae: 431d orrs r5, r3
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
18b0: 4a13 ldr r2, [pc, #76] ; (1900 <system_gclk_gen_set_config+0xa8>)
18b2: 7853 ldrb r3, [r2, #1]
}
while (system_gclk_is_syncing()) {
18b4: b25b sxtb r3, r3
18b6: 2b00 cmp r3, #0
18b8: dbfb blt.n 18b2 <system_gclk_gen_set_config+0x5a>
cpu_irq_enter_critical();
18ba: 4b12 ldr r3, [pc, #72] ; (1904 <system_gclk_gen_set_config+0xac>)
18bc: 4798 blx r3
};
system_interrupt_enter_critical_section();
/* Select the correct generator */
*((uint8_t*)&GCLK->GENDIV.reg) = generator;
18be: 4b12 ldr r3, [pc, #72] ; (1908 <system_gclk_gen_set_config+0xb0>)
18c0: 701e strb r6, [r3, #0]
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
18c2: 4a0f ldr r2, [pc, #60] ; (1900 <system_gclk_gen_set_config+0xa8>)
18c4: 7853 ldrb r3, [r2, #1]
/* Write the new generator configuration */
while (system_gclk_is_syncing()) {
18c6: b25b sxtb r3, r3
18c8: 2b00 cmp r3, #0
18ca: dbfb blt.n 18c4 <system_gclk_gen_set_config+0x6c>
/* Wait for synchronization */
};
GCLK->GENDIV.reg = new_gendiv_config;
18cc: 4b0c ldr r3, [pc, #48] ; (1900 <system_gclk_gen_set_config+0xa8>)
18ce: 609c str r4, [r3, #8]
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
18d0: 001a movs r2, r3
18d2: 7853 ldrb r3, [r2, #1]
while (system_gclk_is_syncing()) {
18d4: b25b sxtb r3, r3
18d6: 2b00 cmp r3, #0
18d8: dbfb blt.n 18d2 <system_gclk_gen_set_config+0x7a>
/* Wait for synchronization */
};
GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
18da: 4a09 ldr r2, [pc, #36] ; (1900 <system_gclk_gen_set_config+0xa8>)
18dc: 6853 ldr r3, [r2, #4]
18de: 2180 movs r1, #128 ; 0x80
18e0: 0249 lsls r1, r1, #9
18e2: 400b ands r3, r1
18e4: 431d orrs r5, r3
18e6: 6055 str r5, [r2, #4]
cpu_irq_leave_critical();
18e8: 4b08 ldr r3, [pc, #32] ; (190c <system_gclk_gen_set_config+0xb4>)
18ea: 4798 blx r3
system_interrupt_leave_critical_section();
}
18ec: bd70 pop {r4, r5, r6, pc}
for (mask = (1UL << 1); mask < config->division_factor;
18ee: 2200 movs r2, #0
18f0: e7d2 b.n 1898 <system_gclk_gen_set_config+0x40>
(config->division_factor) << GCLK_GENDIV_DIV_Pos;
18f2: 0204 lsls r4, r0, #8
new_gendiv_config |=
18f4: 4334 orrs r4, r6
new_genctrl_config |= GCLK_GENCTRL_IDC;
18f6: 2380 movs r3, #128 ; 0x80
18f8: 029b lsls r3, r3, #10
18fa: 431d orrs r5, r3
18fc: e7d2 b.n 18a4 <system_gclk_gen_set_config+0x4c>
18fe: 46c0 nop ; (mov r8, r8)
1900: 40000c00 .word 0x40000c00
1904: 00001559 .word 0x00001559
1908: 40000c08 .word 0x40000c08
190c: 00001599 .word 0x00001599
00001910 <system_gclk_gen_enable>:
*
* \param[in] generator Generic Clock Generator index to enable
*/
void system_gclk_gen_enable(
const uint8_t generator)
{
1910: b510 push {r4, lr}
1912: 0004 movs r4, r0
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
1914: 4a0b ldr r2, [pc, #44] ; (1944 <system_gclk_gen_enable+0x34>)
1916: 7853 ldrb r3, [r2, #1]
while (system_gclk_is_syncing()) {
1918: b25b sxtb r3, r3
191a: 2b00 cmp r3, #0
191c: dbfb blt.n 1916 <system_gclk_gen_enable+0x6>
cpu_irq_enter_critical();
191e: 4b0a ldr r3, [pc, #40] ; (1948 <system_gclk_gen_enable+0x38>)
1920: 4798 blx r3
};
system_interrupt_enter_critical_section();
/* Select the requested generator */
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
1922: 4b0a ldr r3, [pc, #40] ; (194c <system_gclk_gen_enable+0x3c>)
1924: 701c strb r4, [r3, #0]
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
1926: 4a07 ldr r2, [pc, #28] ; (1944 <system_gclk_gen_enable+0x34>)
1928: 7853 ldrb r3, [r2, #1]
while (system_gclk_is_syncing()) {
192a: b25b sxtb r3, r3
192c: 2b00 cmp r3, #0
192e: dbfb blt.n 1928 <system_gclk_gen_enable+0x18>
/* Wait for synchronization */
};
/* Enable generator */
GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
1930: 4a04 ldr r2, [pc, #16] ; (1944 <system_gclk_gen_enable+0x34>)
1932: 6851 ldr r1, [r2, #4]
1934: 2380 movs r3, #128 ; 0x80
1936: 025b lsls r3, r3, #9
1938: 430b orrs r3, r1
193a: 6053 str r3, [r2, #4]
cpu_irq_leave_critical();
193c: 4b04 ldr r3, [pc, #16] ; (1950 <system_gclk_gen_enable+0x40>)
193e: 4798 blx r3
system_interrupt_leave_critical_section();
}
1940: bd10 pop {r4, pc}
1942: 46c0 nop ; (mov r8, r8)
1944: 40000c00 .word 0x40000c00
1948: 00001559 .word 0x00001559
194c: 40000c04 .word 0x40000c04
1950: 00001599 .word 0x00001599
00001954 <system_gclk_gen_get_hz>:
*
* \return The frequency of the generic clock generator, in Hz.
*/
uint32_t system_gclk_gen_get_hz(
const uint8_t generator)
{
1954: b570 push {r4, r5, r6, lr}
1956: 0004 movs r4, r0
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
1958: 4a1a ldr r2, [pc, #104] ; (19c4 <system_gclk_gen_get_hz+0x70>)
195a: 7853 ldrb r3, [r2, #1]
while (system_gclk_is_syncing()) {
195c: b25b sxtb r3, r3
195e: 2b00 cmp r3, #0
1960: dbfb blt.n 195a <system_gclk_gen_get_hz+0x6>
cpu_irq_enter_critical();
1962: 4b19 ldr r3, [pc, #100] ; (19c8 <system_gclk_gen_get_hz+0x74>)
1964: 4798 blx r3
};
system_interrupt_enter_critical_section();
/* Select the appropriate generator */
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
1966: 4b19 ldr r3, [pc, #100] ; (19cc <system_gclk_gen_get_hz+0x78>)
1968: 701c strb r4, [r3, #0]
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
196a: 4a16 ldr r2, [pc, #88] ; (19c4 <system_gclk_gen_get_hz+0x70>)
196c: 7853 ldrb r3, [r2, #1]
while (system_gclk_is_syncing()) {
196e: b25b sxtb r3, r3
1970: 2b00 cmp r3, #0
1972: dbfb blt.n 196c <system_gclk_gen_get_hz+0x18>
/* Wait for synchronization */
};
/* Get the frequency of the source connected to the GCLK generator */
uint32_t gen_input_hz = system_clock_source_get_hz(
(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
1974: 4e13 ldr r6, [pc, #76] ; (19c4 <system_gclk_gen_get_hz+0x70>)
1976: 6870 ldr r0, [r6, #4]
1978: 04c0 lsls r0, r0, #19
197a: 0ec0 lsrs r0, r0, #27
uint32_t gen_input_hz = system_clock_source_get_hz(
197c: 4b14 ldr r3, [pc, #80] ; (19d0 <system_gclk_gen_get_hz+0x7c>)
197e: 4798 blx r3
1980: 0005 movs r5, r0
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
1982: 4b12 ldr r3, [pc, #72] ; (19cc <system_gclk_gen_get_hz+0x78>)
1984: 701c strb r4, [r3, #0]
uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
1986: 6876 ldr r6, [r6, #4]
1988: 02f6 lsls r6, r6, #11
198a: 0ff6 lsrs r6, r6, #31
/* Select the appropriate generator division register */
*((uint8_t*)&GCLK->GENDIV.reg) = generator;
198c: 4b11 ldr r3, [pc, #68] ; (19d4 <system_gclk_gen_get_hz+0x80>)
198e: 701c strb r4, [r3, #0]
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
1990: 4a0c ldr r2, [pc, #48] ; (19c4 <system_gclk_gen_get_hz+0x70>)
1992: 7853 ldrb r3, [r2, #1]
while (system_gclk_is_syncing()) {
1994: b25b sxtb r3, r3
1996: 2b00 cmp r3, #0
1998: dbfb blt.n 1992 <system_gclk_gen_get_hz+0x3e>
/* Wait for synchronization */
};
uint32_t divider = GCLK->GENDIV.bit.DIV;
199a: 4b0a ldr r3, [pc, #40] ; (19c4 <system_gclk_gen_get_hz+0x70>)
199c: 689c ldr r4, [r3, #8]
199e: 0224 lsls r4, r4, #8
19a0: 0c24 lsrs r4, r4, #16
cpu_irq_leave_critical();
19a2: 4b0d ldr r3, [pc, #52] ; (19d8 <system_gclk_gen_get_hz+0x84>)
19a4: 4798 blx r3
system_interrupt_leave_critical_section();
/* Check if the generator is using fractional or binary division */
if (!divsel && divider > 1) {
19a6: 2e00 cmp r6, #0
19a8: d107 bne.n 19ba <system_gclk_gen_get_hz+0x66>
19aa: 2c01 cmp r4, #1
19ac: d907 bls.n 19be <system_gclk_gen_get_hz+0x6a>
gen_input_hz /= divider;
19ae: 0021 movs r1, r4
19b0: 0028 movs r0, r5
19b2: 4b0a ldr r3, [pc, #40] ; (19dc <system_gclk_gen_get_hz+0x88>)
19b4: 4798 blx r3
19b6: 0005 movs r5, r0
19b8: e001 b.n 19be <system_gclk_gen_get_hz+0x6a>
} else if (divsel) {
gen_input_hz >>= (divider+1);
19ba: 3401 adds r4, #1
19bc: 40e5 lsrs r5, r4
}
return gen_input_hz;
}
19be: 0028 movs r0, r5
19c0: bd70 pop {r4, r5, r6, pc}
19c2: 46c0 nop ; (mov r8, r8)
19c4: 40000c00 .word 0x40000c00
19c8: 00001559 .word 0x00001559
19cc: 40000c04 .word 0x40000c04
19d0: 00001625 .word 0x00001625
19d4: 40000c08 .word 0x40000c08
19d8: 00001599 .word 0x00001599
19dc: 00001d45 .word 0x00001d45
000019e0 <system_gclk_chan_enable>:
*
* \param[in] channel Generic Clock channel to enable
*/
void system_gclk_chan_enable(
const uint8_t channel)
{
19e0: b510 push {r4, lr}
19e2: 0004 movs r4, r0
cpu_irq_enter_critical();
19e4: 4b06 ldr r3, [pc, #24] ; (1a00 <system_gclk_chan_enable+0x20>)
19e6: 4798 blx r3
system_interrupt_enter_critical_section();
/* Select the requested generator channel */
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
19e8: 4b06 ldr r3, [pc, #24] ; (1a04 <system_gclk_chan_enable+0x24>)
19ea: 701c strb r4, [r3, #0]
/* Enable the generic clock */
GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
19ec: 4a06 ldr r2, [pc, #24] ; (1a08 <system_gclk_chan_enable+0x28>)
19ee: 8853 ldrh r3, [r2, #2]
19f0: 2180 movs r1, #128 ; 0x80
19f2: 01c9 lsls r1, r1, #7
19f4: 430b orrs r3, r1
19f6: 8053 strh r3, [r2, #2]
cpu_irq_leave_critical();
19f8: 4b04 ldr r3, [pc, #16] ; (1a0c <system_gclk_chan_enable+0x2c>)
19fa: 4798 blx r3
system_interrupt_leave_critical_section();
}
19fc: bd10 pop {r4, pc}
19fe: 46c0 nop ; (mov r8, r8)
1a00: 00001559 .word 0x00001559
1a04: 40000c02 .word 0x40000c02
1a08: 40000c00 .word 0x40000c00
1a0c: 00001599 .word 0x00001599
00001a10 <system_gclk_chan_disable>:
*
* \param[in] channel Generic Clock channel to disable
*/
void system_gclk_chan_disable(
const uint8_t channel)
{
1a10: b510 push {r4, lr}
1a12: 0004 movs r4, r0
cpu_irq_enter_critical();
1a14: 4b0f ldr r3, [pc, #60] ; (1a54 <system_gclk_chan_disable+0x44>)
1a16: 4798 blx r3
system_interrupt_enter_critical_section();
/* Select the requested generator channel */
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
1a18: 4b0f ldr r3, [pc, #60] ; (1a58 <system_gclk_chan_disable+0x48>)
1a1a: 701c strb r4, [r3, #0]
/* Sanity check WRTLOCK */
Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
/* Switch to known-working source so that the channel can be disabled */
uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
1a1c: 4a0f ldr r2, [pc, #60] ; (1a5c <system_gclk_chan_disable+0x4c>)
1a1e: 8853 ldrh r3, [r2, #2]
1a20: 051b lsls r3, r3, #20
1a22: 0f18 lsrs r0, r3, #28
GCLK->CLKCTRL.bit.GEN = 0;
1a24: 8853 ldrh r3, [r2, #2]
1a26: 490e ldr r1, [pc, #56] ; (1a60 <system_gclk_chan_disable+0x50>)
1a28: 400b ands r3, r1
1a2a: 8053 strh r3, [r2, #2]
/* Disable the generic clock */
GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
1a2c: 8853 ldrh r3, [r2, #2]
1a2e: 490d ldr r1, [pc, #52] ; (1a64 <system_gclk_chan_disable+0x54>)
1a30: 400b ands r3, r1
1a32: 8053 strh r3, [r2, #2]
while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
1a34: 0011 movs r1, r2
1a36: 2280 movs r2, #128 ; 0x80
1a38: 01d2 lsls r2, r2, #7
1a3a: 884b ldrh r3, [r1, #2]
1a3c: 4213 tst r3, r2
1a3e: d1fc bne.n 1a3a <system_gclk_chan_disable+0x2a>
/* Wait for clock to become disabled */
}
/* Restore previous configured clock generator */
GCLK->CLKCTRL.bit.GEN = prev_gen_id;
1a40: 4906 ldr r1, [pc, #24] ; (1a5c <system_gclk_chan_disable+0x4c>)
1a42: 884a ldrh r2, [r1, #2]
1a44: 0203 lsls r3, r0, #8
1a46: 4806 ldr r0, [pc, #24] ; (1a60 <system_gclk_chan_disable+0x50>)
1a48: 4002 ands r2, r0
1a4a: 4313 orrs r3, r2
1a4c: 804b strh r3, [r1, #2]
cpu_irq_leave_critical();
1a4e: 4b06 ldr r3, [pc, #24] ; (1a68 <system_gclk_chan_disable+0x58>)
1a50: 4798 blx r3
system_interrupt_leave_critical_section();
}
1a52: bd10 pop {r4, pc}
1a54: 00001559 .word 0x00001559
1a58: 40000c02 .word 0x40000c02
1a5c: 40000c00 .word 0x40000c00
1a60: fffff0ff .word 0xfffff0ff
1a64: ffffbfff .word 0xffffbfff
1a68: 00001599 .word 0x00001599
00001a6c <system_gclk_chan_set_config>:
{
1a6c: b510 push {r4, lr}
new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
1a6e: 780c ldrb r4, [r1, #0]
1a70: 0224 lsls r4, r4, #8
1a72: 4304 orrs r4, r0
system_gclk_chan_disable(channel);
1a74: 4b02 ldr r3, [pc, #8] ; (1a80 <system_gclk_chan_set_config+0x14>)
1a76: 4798 blx r3
GCLK->CLKCTRL.reg = new_clkctrl_config;
1a78: b2a4 uxth r4, r4
1a7a: 4b02 ldr r3, [pc, #8] ; (1a84 <system_gclk_chan_set_config+0x18>)
1a7c: 805c strh r4, [r3, #2]
}
1a7e: bd10 pop {r4, pc}
1a80: 00001a11 .word 0x00001a11
1a84: 40000c00 .word 0x40000c00
00001a88 <system_gclk_chan_get_hz>:
*
* \return The frequency of the generic clock channel, in Hz.
*/
uint32_t system_gclk_chan_get_hz(
const uint8_t channel)
{
1a88: b510 push {r4, lr}
1a8a: 0004 movs r4, r0
cpu_irq_enter_critical();
1a8c: 4b06 ldr r3, [pc, #24] ; (1aa8 <system_gclk_chan_get_hz+0x20>)
1a8e: 4798 blx r3
uint8_t gen_id;
system_interrupt_enter_critical_section();
/* Select the requested generic clock channel */
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
1a90: 4b06 ldr r3, [pc, #24] ; (1aac <system_gclk_chan_get_hz+0x24>)
1a92: 701c strb r4, [r3, #0]
gen_id = GCLK->CLKCTRL.bit.GEN;
1a94: 4b06 ldr r3, [pc, #24] ; (1ab0 <system_gclk_chan_get_hz+0x28>)
1a96: 885c ldrh r4, [r3, #2]
1a98: 0524 lsls r4, r4, #20
1a9a: 0f24 lsrs r4, r4, #28
cpu_irq_leave_critical();
1a9c: 4b05 ldr r3, [pc, #20] ; (1ab4 <system_gclk_chan_get_hz+0x2c>)
1a9e: 4798 blx r3
system_interrupt_leave_critical_section();
/* Return the clock speed of the associated GCLK generator */
return system_gclk_gen_get_hz(gen_id);
1aa0: 0020 movs r0, r4
1aa2: 4b05 ldr r3, [pc, #20] ; (1ab8 <system_gclk_chan_get_hz+0x30>)
1aa4: 4798 blx r3
}
1aa6: bd10 pop {r4, pc}
1aa8: 00001559 .word 0x00001559
1aac: 40000c02 .word 0x40000c02
1ab0: 40000c00 .word 0x40000c00
1ab4: 00001599 .word 0x00001599
1ab8: 00001955 .word 0x00001955
00001abc <_system_pinmux_config>:
*/
static void _system_pinmux_config(
PortGroup *const port,
const uint32_t pin_mask,
const struct system_pinmux_config *const config)
{
1abc: b530 push {r4, r5, lr}
/* Track the configuration bits into a temporary variable before writing */
uint32_t pin_cfg = 0;
/* Enabled powersave mode, don't create configuration */
if (!config->powersave) {
1abe: 78d3 ldrb r3, [r2, #3]
1ac0: 2b00 cmp r3, #0
1ac2: d135 bne.n 1b30 <_system_pinmux_config+0x74>
/* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
* be written later) and store the new MUX mask */
if (config->mux_position != SYSTEM_PINMUX_GPIO) {
1ac4: 7813 ldrb r3, [r2, #0]
1ac6: 2b80 cmp r3, #128 ; 0x80
1ac8: d029 beq.n 1b1e <_system_pinmux_config+0x62>
pin_cfg |= PORT_WRCONFIG_PMUXEN;
pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
1aca: 061b lsls r3, r3, #24
1acc: 2480 movs r4, #128 ; 0x80
1ace: 0264 lsls r4, r4, #9
1ad0: 4323 orrs r3, r4
}
/* Check if the user has requested that the input buffer be enabled */
if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
1ad2: 7854 ldrb r4, [r2, #1]
1ad4: 2502 movs r5, #2
1ad6: 43ac bics r4, r5
1ad8: d106 bne.n 1ae8 <_system_pinmux_config+0x2c>
(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
/* Enable input buffer flag */
pin_cfg |= PORT_WRCONFIG_INEN;
/* Enable pull-up/pull-down control flag if requested */
if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
1ada: 7894 ldrb r4, [r2, #2]
1adc: 2c00 cmp r4, #0
1ade: d120 bne.n 1b22 <_system_pinmux_config+0x66>
pin_cfg |= PORT_WRCONFIG_INEN;
1ae0: 2480 movs r4, #128 ; 0x80
1ae2: 02a4 lsls r4, r4, #10
1ae4: 4323 orrs r3, r4
pin_cfg |= PORT_WRCONFIG_PULLEN;
}
/* Clear the port DIR bits to disable the output buffer */
port->DIRCLR.reg = pin_mask;
1ae6: 6041 str r1, [r0, #4]
}
/* Check if the user has requested that the output buffer be enabled */
if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
1ae8: 7854 ldrb r4, [r2, #1]
1aea: 3c01 subs r4, #1
1aec: 2c01 cmp r4, #1
1aee: d91c bls.n 1b2a <_system_pinmux_config+0x6e>
port->DIRCLR.reg = pin_mask;
}
/* The Write Configuration register (WRCONFIG) requires the
* pins to to grouped into two 16-bit half-words - split them out here */
uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
1af0: 040d lsls r5, r1, #16
1af2: 0c2d lsrs r5, r5, #16
/* Configure the lower 16-bits of the port to the desired configuration,
* including the pin peripheral multiplexer just in case it is enabled */
port->WRCONFIG.reg
= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
1af4: 24a0 movs r4, #160 ; 0xa0
1af6: 05e4 lsls r4, r4, #23
1af8: 432c orrs r4, r5
1afa: 431c orrs r4, r3
= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
1afc: 6284 str r4, [r0, #40] ; 0x28
uint32_t upper_pin_mask = (pin_mask >> 16);
1afe: 0c0d lsrs r5, r1, #16
/* Configure the upper 16-bits of the port to the desired configuration,
* including the pin peripheral multiplexer just in case it is enabled */
port->WRCONFIG.reg
= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
1b00: 24d0 movs r4, #208 ; 0xd0
1b02: 0624 lsls r4, r4, #24
1b04: 432c orrs r4, r5
1b06: 431c orrs r4, r3
= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
1b08: 6284 str r4, [r0, #40] ; 0x28
PORT_WRCONFIG_HWSEL;
if(!config->powersave) {
1b0a: 78d4 ldrb r4, [r2, #3]
1b0c: 2c00 cmp r4, #0
1b0e: d122 bne.n 1b56 <_system_pinmux_config+0x9a>
/* Set the pull-up state once the port pins are configured if one was
* requested and it does not violate the valid set of port
* configurations */
if (pin_cfg & PORT_WRCONFIG_PULLEN) {
1b10: 035b lsls r3, r3, #13
1b12: d51c bpl.n 1b4e <_system_pinmux_config+0x92>
/* Set the OUT register bits to enable the pull-up if requested,
* clear to enable pull-down */
if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
1b14: 7893 ldrb r3, [r2, #2]
1b16: 2b01 cmp r3, #1
1b18: d01e beq.n 1b58 <_system_pinmux_config+0x9c>
port->OUTSET.reg = pin_mask;
} else {
port->OUTCLR.reg = pin_mask;
1b1a: 6141 str r1, [r0, #20]
1b1c: e017 b.n 1b4e <_system_pinmux_config+0x92>
uint32_t pin_cfg = 0;
1b1e: 2300 movs r3, #0
1b20: e7d7 b.n 1ad2 <_system_pinmux_config+0x16>
pin_cfg |= PORT_WRCONFIG_PULLEN;
1b22: 24c0 movs r4, #192 ; 0xc0
1b24: 02e4 lsls r4, r4, #11
1b26: 4323 orrs r3, r4
1b28: e7dd b.n 1ae6 <_system_pinmux_config+0x2a>
pin_cfg &= ~PORT_WRCONFIG_PULLEN;
1b2a: 4c0d ldr r4, [pc, #52] ; (1b60 <_system_pinmux_config+0xa4>)
1b2c: 4023 ands r3, r4
1b2e: e7df b.n 1af0 <_system_pinmux_config+0x34>
port->DIRCLR.reg = pin_mask;
1b30: 6041 str r1, [r0, #4]
uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
1b32: 040c lsls r4, r1, #16
1b34: 0c24 lsrs r4, r4, #16
pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
1b36: 23a0 movs r3, #160 ; 0xa0
1b38: 05db lsls r3, r3, #23
1b3a: 4323 orrs r3, r4
= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
1b3c: 6283 str r3, [r0, #40] ; 0x28
uint32_t upper_pin_mask = (pin_mask >> 16);
1b3e: 0c0c lsrs r4, r1, #16
pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
1b40: 23d0 movs r3, #208 ; 0xd0
1b42: 061b lsls r3, r3, #24
1b44: 4323 orrs r3, r4
= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
1b46: 6283 str r3, [r0, #40] ; 0x28
if(!config->powersave) {
1b48: 78d3 ldrb r3, [r2, #3]
1b4a: 2b00 cmp r3, #0
1b4c: d103 bne.n 1b56 <_system_pinmux_config+0x9a>
}
}
/* Check if the user has requested that the output buffer be enabled */
if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
1b4e: 7853 ldrb r3, [r2, #1]
1b50: 3b01 subs r3, #1
1b52: 2b01 cmp r3, #1
1b54: d902 bls.n 1b5c <_system_pinmux_config+0xa0>
(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
/* Set the port DIR bits to enable the output buffer */
port->DIRSET.reg = pin_mask;
}
}
}
1b56: bd30 pop {r4, r5, pc}
port->OUTSET.reg = pin_mask;
1b58: 6181 str r1, [r0, #24]
1b5a: e7f8 b.n 1b4e <_system_pinmux_config+0x92>
port->DIRSET.reg = pin_mask;
1b5c: 6081 str r1, [r0, #8]
}
1b5e: e7fa b.n 1b56 <_system_pinmux_config+0x9a>
1b60: fffbffff .word 0xfffbffff
00001b64 <system_pinmux_pin_set_config>:
* \param[in] config Configuration settings for the pin
*/
void system_pinmux_pin_set_config(
const uint8_t gpio_pin,
const struct system_pinmux_config *const config)
{
1b64: b510 push {r4, lr}
1b66: 000a movs r2, r1
uint8_t group_index = (gpio_pin / 32);
/* Array of available ports */
Port *const ports[PORT_INST_NUM] = PORT_INSTS;
if (port_index < PORT_INST_NUM) {
1b68: 09c1 lsrs r1, r0, #7
return &(ports[port_index]->Group[group_index]);
} else {
Assert(false);
return NULL;
1b6a: 2300 movs r3, #0
if (port_index < PORT_INST_NUM) {
1b6c: 2900 cmp r1, #0
1b6e: d104 bne.n 1b7a <system_pinmux_pin_set_config+0x16>
return &(ports[port_index]->Group[group_index]);
1b70: 0943 lsrs r3, r0, #5
1b72: 01db lsls r3, r3, #7
1b74: 4905 ldr r1, [pc, #20] ; (1b8c <system_pinmux_pin_set_config+0x28>)
1b76: 468c mov ip, r1
1b78: 4463 add r3, ip
PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
1b7a: 241f movs r4, #31
1b7c: 4020 ands r0, r4
1b7e: 2101 movs r1, #1
1b80: 4081 lsls r1, r0
_system_pinmux_config(port, pin_mask, config);
1b82: 0018 movs r0, r3
1b84: 4b02 ldr r3, [pc, #8] ; (1b90 <system_pinmux_pin_set_config+0x2c>)
1b86: 4798 blx r3
}
1b88: bd10 pop {r4, pc}
1b8a: 46c0 nop ; (mov r8, r8)
1b8c: 41004400 .word 0x41004400
1b90: 00001abd .word 0x00001abd
00001b94 <_system_dummy_init>:
*/
void _system_dummy_init(void);
void _system_dummy_init(void)
{
return;
}
1b94: 4770 bx lr
...
00001b98 <system_init>:
* - Board hardware initialization (via the Board module)
* - Event system driver initialization (via the EVSYS module)
* - External Interrupt driver initialization (via the EXTINT module)
*/
void system_init(void)
{
1b98: b510 push {r4, lr}
/* Configure GCLK and clock sources according to conf_clocks.h */
system_clock_init();
1b9a: 4b05 ldr r3, [pc, #20] ; (1bb0 <system_init+0x18>)
1b9c: 4798 blx r3
/* Initialize board hardware */
system_board_init();
1b9e: 4b05 ldr r3, [pc, #20] ; (1bb4 <system_init+0x1c>)
1ba0: 4798 blx r3
/* Initialize EVSYS hardware */
_system_events_init();
1ba2: 4b05 ldr r3, [pc, #20] ; (1bb8 <system_init+0x20>)
1ba4: 4798 blx r3
/* Initialize External hardware */
_system_extint_init();
1ba6: 4b05 ldr r3, [pc, #20] ; (1bbc <system_init+0x24>)
1ba8: 4798 blx r3
/* Initialize DIVAS hardware */
_system_divas_init();
1baa: 4b05 ldr r3, [pc, #20] ; (1bc0 <system_init+0x28>)
1bac: 4798 blx r3
}
1bae: bd10 pop {r4, pc}
1bb0: 0000179d .word 0x0000179d
1bb4: 000015c9 .word 0x000015c9
1bb8: 00001b95 .word 0x00001b95
1bbc: 00001b95 .word 0x00001b95
1bc0: 00001b95 .word 0x00001b95
00001bc4 <Dummy_Handler>:
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
1bc4: e7fe b.n 1bc4 <Dummy_Handler>
...
00001bc8 <Reset_Handler>:
{
1bc8: b5f8 push {r3, r4, r5, r6, r7, lr}
if (pSrc != pDest) {
1bca: 4a2a ldr r2, [pc, #168] ; (1c74 <Reset_Handler+0xac>)
1bcc: 4b2a ldr r3, [pc, #168] ; (1c78 <Reset_Handler+0xb0>)
1bce: 429a cmp r2, r3
1bd0: d011 beq.n 1bf6 <Reset_Handler+0x2e>
for (; pDest < &_erelocate;) {
1bd2: 001a movs r2, r3
1bd4: 4b29 ldr r3, [pc, #164] ; (1c7c <Reset_Handler+0xb4>)
1bd6: 429a cmp r2, r3
1bd8: d20d bcs.n 1bf6 <Reset_Handler+0x2e>
1bda: 4a29 ldr r2, [pc, #164] ; (1c80 <Reset_Handler+0xb8>)
1bdc: 3303 adds r3, #3
1bde: 1a9b subs r3, r3, r2
1be0: 089b lsrs r3, r3, #2
1be2: 3301 adds r3, #1
1be4: 009b lsls r3, r3, #2
1be6: 2200 movs r2, #0
*pDest++ = *pSrc++;
1be8: 4823 ldr r0, [pc, #140] ; (1c78 <Reset_Handler+0xb0>)
1bea: 4922 ldr r1, [pc, #136] ; (1c74 <Reset_Handler+0xac>)
1bec: 588c ldr r4, [r1, r2]
1bee: 5084 str r4, [r0, r2]
1bf0: 3204 adds r2, #4
for (; pDest < &_erelocate;) {
1bf2: 429a cmp r2, r3
1bf4: d1fa bne.n 1bec <Reset_Handler+0x24>
for (pDest = &_szero; pDest < &_ezero;) {
1bf6: 4a23 ldr r2, [pc, #140] ; (1c84 <Reset_Handler+0xbc>)
1bf8: 4b23 ldr r3, [pc, #140] ; (1c88 <Reset_Handler+0xc0>)
1bfa: 429a cmp r2, r3
1bfc: d20a bcs.n 1c14 <Reset_Handler+0x4c>
1bfe: 43d3 mvns r3, r2
1c00: 4921 ldr r1, [pc, #132] ; (1c88 <Reset_Handler+0xc0>)
1c02: 185b adds r3, r3, r1
1c04: 2103 movs r1, #3
1c06: 438b bics r3, r1
1c08: 3304 adds r3, #4
1c0a: 189b adds r3, r3, r2
*pDest++ = 0;
1c0c: 2100 movs r1, #0
1c0e: c202 stmia r2!, {r1}
for (pDest = &_szero; pDest < &_ezero;) {
1c10: 4293 cmp r3, r2
1c12: d1fc bne.n 1c0e <Reset_Handler+0x46>
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
1c14: 4a1d ldr r2, [pc, #116] ; (1c8c <Reset_Handler+0xc4>)
1c16: 21ff movs r1, #255 ; 0xff
1c18: 4b1d ldr r3, [pc, #116] ; (1c90 <Reset_Handler+0xc8>)
1c1a: 438b bics r3, r1
1c1c: 6093 str r3, [r2, #8]
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
1c1e: 39fd subs r1, #253 ; 0xfd
1c20: 2390 movs r3, #144 ; 0x90
1c22: 005b lsls r3, r3, #1
1c24: 4a1b ldr r2, [pc, #108] ; (1c94 <Reset_Handler+0xcc>)
1c26: 50d1 str r1, [r2, r3]
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
1c28: 4a1b ldr r2, [pc, #108] ; (1c98 <Reset_Handler+0xd0>)
1c2a: 78d3 ldrb r3, [r2, #3]
1c2c: 2503 movs r5, #3
1c2e: 43ab bics r3, r5
1c30: 2402 movs r4, #2
1c32: 4323 orrs r3, r4
1c34: 70d3 strb r3, [r2, #3]
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
1c36: 78d3 ldrb r3, [r2, #3]
1c38: 270c movs r7, #12
1c3a: 43bb bics r3, r7
1c3c: 2608 movs r6, #8
1c3e: 4333 orrs r3, r6
1c40: 70d3 strb r3, [r2, #3]
DMAC->QOSCTRL.bit.DQOS = 2;
1c42: 4b16 ldr r3, [pc, #88] ; (1c9c <Reset_Handler+0xd4>)
1c44: 7b98 ldrb r0, [r3, #14]
1c46: 2230 movs r2, #48 ; 0x30
1c48: 4390 bics r0, r2
1c4a: 2220 movs r2, #32
1c4c: 4310 orrs r0, r2
1c4e: 7398 strb r0, [r3, #14]
DMAC->QOSCTRL.bit.FQOS = 2;
1c50: 7b99 ldrb r1, [r3, #14]
1c52: 43b9 bics r1, r7
1c54: 4331 orrs r1, r6
1c56: 7399 strb r1, [r3, #14]
DMAC->QOSCTRL.bit.WRBQOS = 2;
1c58: 7b9a ldrb r2, [r3, #14]
1c5a: 43aa bics r2, r5
1c5c: 4322 orrs r2, r4
1c5e: 739a strb r2, [r3, #14]
NVMCTRL->CTRLB.bit.MANW = 1;
1c60: 4a0f ldr r2, [pc, #60] ; (1ca0 <Reset_Handler+0xd8>)
1c62: 6853 ldr r3, [r2, #4]
1c64: 2180 movs r1, #128 ; 0x80
1c66: 430b orrs r3, r1
1c68: 6053 str r3, [r2, #4]
__libc_init_array();
1c6a: 4b0e ldr r3, [pc, #56] ; (1ca4 <Reset_Handler+0xdc>)
1c6c: 4798 blx r3
main();
1c6e: 4b0e ldr r3, [pc, #56] ; (1ca8 <Reset_Handler+0xe0>)
1c70: 4798 blx r3
1c72: e7fe b.n 1c72 <Reset_Handler+0xaa>
1c74: 00004a40 .word 0x00004a40
1c78: 20000000 .word 0x20000000
1c7c: 20000068 .word 0x20000068
1c80: 20000004 .word 0x20000004
1c84: 20000068 .word 0x20000068
1c88: 20000260 .word 0x20000260
1c8c: e000ed00 .word 0xe000ed00
1c90: 00000000 .word 0x00000000
1c94: 41007000 .word 0x41007000
1c98: 41005000 .word 0x41005000
1c9c: 41004800 .word 0x41004800
1ca0: 41004000 .word 0x41004000
1ca4: 00003779 .word 0x00003779
1ca8: 00001ce9 .word 0x00001ce9
00001cac <_sbrk>:
extern void _exit(int status);
extern void _kill(int pid, int sig);
extern int _getpid(void);
extern caddr_t _sbrk(int incr)
{
1cac: 0003 movs r3, r0
static unsigned char *heap = NULL;
unsigned char *prev_heap;
if (heap == NULL) {
1cae: 4a06 ldr r2, [pc, #24] ; (1cc8 <_sbrk+0x1c>)
1cb0: 6812 ldr r2, [r2, #0]
1cb2: 2a00 cmp r2, #0
1cb4: d004 beq.n 1cc0 <_sbrk+0x14>
heap = (unsigned char *)&_end;
}
prev_heap = heap;
1cb6: 4a04 ldr r2, [pc, #16] ; (1cc8 <_sbrk+0x1c>)
1cb8: 6810 ldr r0, [r2, #0]
heap += incr;
1cba: 18c3 adds r3, r0, r3
1cbc: 6013 str r3, [r2, #0]
return (caddr_t) prev_heap;
}
1cbe: 4770 bx lr
heap = (unsigned char *)&_end;
1cc0: 4902 ldr r1, [pc, #8] ; (1ccc <_sbrk+0x20>)
1cc2: 4a01 ldr r2, [pc, #4] ; (1cc8 <_sbrk+0x1c>)
1cc4: 6011 str r1, [r2, #0]
1cc6: e7f6 b.n 1cb6 <_sbrk+0xa>
1cc8: 200000c4 .word 0x200000c4
1ccc: 20002260 .word 0x20002260
00001cd0 <_close>:
}
extern int _close(int file)
{
return -1;
}
1cd0: 2001 movs r0, #1
1cd2: 4240 negs r0, r0
1cd4: 4770 bx lr
00001cd6 <_fstat>:
extern int _fstat(int file, struct stat *st)
{
st->st_mode = S_IFCHR;
1cd6: 2380 movs r3, #128 ; 0x80
1cd8: 019b lsls r3, r3, #6
1cda: 604b str r3, [r1, #4]
return 0;
}
1cdc: 2000 movs r0, #0
1cde: 4770 bx lr
00001ce0 <_isatty>:
extern int _isatty(int file)
{
return 1;
}
1ce0: 2001 movs r0, #1
1ce2: 4770 bx lr
00001ce4 <_lseek>:
extern int _lseek(int file, int ptr, int dir)
{
return 0;
}
1ce4: 2000 movs r0, #0
1ce6: 4770 bx lr
00001ce8 <main>:
*/
#include <asf.h>
#include "p_usart.h"
#include "p_i2c.h"
int main (void)
{
1ce8: b570 push {r4, r5, r6, lr}
1cea: b084 sub sp, #16
system_init();
1cec: 4b0f ldr r3, [pc, #60] ; (1d2c <main+0x44>)
1cee: 4798 blx r3
p_usart_init();
1cf0: 4b0f ldr r3, [pc, #60] ; (1d30 <main+0x48>)
1cf2: 4798 blx r3
p_i2c_master_bus_init();
1cf4: 4b0f ldr r3, [pc, #60] ; (1d34 <main+0x4c>)
1cf6: 4798 blx r3
/* Insert application code here, after the board has been initialized. */
uint8_t stuff = 0;
1cf8: 230f movs r3, #15
1cfa: 446b add r3, sp
1cfc: 2200 movs r2, #0
1cfe: 701a strb r2, [r3, #0]
i2c_device generic_i2c_dev;
generic_i2c_dev.addr = 0x00;
generic_i2c_dev.buffer = &stuff;
1d00: 9301 str r3, [sp, #4]
for(int ind = 0; ind < 119; ind++)
1d02: 2400 movs r4, #0
{
generic_i2c_dev.addr = ind;
if(p_i2c_write_byte(&generic_i2c_dev, 0x00, true) == 0)
1d04: 4d0c ldr r5, [pc, #48] ; (1d38 <main+0x50>)
{
printf("I2C address 0x%02x\n", ind);
1d06: 4e0d ldr r6, [pc, #52] ; (1d3c <main+0x54>)
1d08: e002 b.n 1d10 <main+0x28>
for(int ind = 0; ind < 119; ind++)
1d0a: 3401 adds r4, #1
1d0c: 2c77 cmp r4, #119 ; 0x77
1d0e: d00b beq.n 1d28 <main+0x40>
generic_i2c_dev.addr = ind;
1d10: 466b mov r3, sp
1d12: 701c strb r4, [r3, #0]
if(p_i2c_write_byte(&generic_i2c_dev, 0x00, true) == 0)
1d14: 2201 movs r2, #1
1d16: 2100 movs r1, #0
1d18: 4668 mov r0, sp
1d1a: 47a8 blx r5
1d1c: 2800 cmp r0, #0
1d1e: d1f4 bne.n 1d0a <main+0x22>
printf("I2C address 0x%02x\n", ind);
1d20: 0021 movs r1, r4
1d22: 4807 ldr r0, [pc, #28] ; (1d40 <main+0x58>)
1d24: 47b0 blx r6
1d26: e7f0 b.n 1d0a <main+0x22>
1d28: e7fe b.n 1d28 <main+0x40>
1d2a: 46c0 nop ; (mov r8, r8)
1d2c: 00001b99 .word 0x00001b99
1d30: 00000ab1 .word 0x00000ab1
1d34: 000009a9 .word 0x000009a9
1d38: 00000921 .word 0x00000921
1d3c: 000037d1 .word 0x000037d1
1d40: 000048f4 .word 0x000048f4
00001d44 <__udivsi3>:
1d44: 2200 movs r2, #0
1d46: 0843 lsrs r3, r0, #1
1d48: 428b cmp r3, r1
1d4a: d374 bcc.n 1e36 <__udivsi3+0xf2>
1d4c: 0903 lsrs r3, r0, #4
1d4e: 428b cmp r3, r1
1d50: d35f bcc.n 1e12 <__udivsi3+0xce>
1d52: 0a03 lsrs r3, r0, #8
1d54: 428b cmp r3, r1
1d56: d344 bcc.n 1de2 <__udivsi3+0x9e>
1d58: 0b03 lsrs r3, r0, #12
1d5a: 428b cmp r3, r1
1d5c: d328 bcc.n 1db0 <__udivsi3+0x6c>
1d5e: 0c03 lsrs r3, r0, #16
1d60: 428b cmp r3, r1
1d62: d30d bcc.n 1d80 <__udivsi3+0x3c>
1d64: 22ff movs r2, #255 ; 0xff
1d66: 0209 lsls r1, r1, #8
1d68: ba12 rev r2, r2
1d6a: 0c03 lsrs r3, r0, #16
1d6c: 428b cmp r3, r1
1d6e: d302 bcc.n 1d76 <__udivsi3+0x32>
1d70: 1212 asrs r2, r2, #8
1d72: 0209 lsls r1, r1, #8
1d74: d065 beq.n 1e42 <__udivsi3+0xfe>
1d76: 0b03 lsrs r3, r0, #12
1d78: 428b cmp r3, r1
1d7a: d319 bcc.n 1db0 <__udivsi3+0x6c>
1d7c: e000 b.n 1d80 <__udivsi3+0x3c>
1d7e: 0a09 lsrs r1, r1, #8
1d80: 0bc3 lsrs r3, r0, #15
1d82: 428b cmp r3, r1
1d84: d301 bcc.n 1d8a <__udivsi3+0x46>
1d86: 03cb lsls r3, r1, #15
1d88: 1ac0 subs r0, r0, r3
1d8a: 4152 adcs r2, r2
1d8c: 0b83 lsrs r3, r0, #14
1d8e: 428b cmp r3, r1
1d90: d301 bcc.n 1d96 <__udivsi3+0x52>
1d92: 038b lsls r3, r1, #14
1d94: 1ac0 subs r0, r0, r3
1d96: 4152 adcs r2, r2
1d98: 0b43 lsrs r3, r0, #13
1d9a: 428b cmp r3, r1
1d9c: d301 bcc.n 1da2 <__udivsi3+0x5e>
1d9e: 034b lsls r3, r1, #13
1da0: 1ac0 subs r0, r0, r3
1da2: 4152 adcs r2, r2
1da4: 0b03 lsrs r3, r0, #12
1da6: 428b cmp r3, r1
1da8: d301 bcc.n 1dae <__udivsi3+0x6a>
1daa: 030b lsls r3, r1, #12
1dac: 1ac0 subs r0, r0, r3
1dae: 4152 adcs r2, r2
1db0: 0ac3 lsrs r3, r0, #11
1db2: 428b cmp r3, r1
1db4: d301 bcc.n 1dba <__udivsi3+0x76>
1db6: 02cb lsls r3, r1, #11
1db8: 1ac0 subs r0, r0, r3
1dba: 4152 adcs r2, r2
1dbc: 0a83 lsrs r3, r0, #10
1dbe: 428b cmp r3, r1
1dc0: d301 bcc.n 1dc6 <__udivsi3+0x82>
1dc2: 028b lsls r3, r1, #10
1dc4: 1ac0 subs r0, r0, r3
1dc6: 4152 adcs r2, r2
1dc8: 0a43 lsrs r3, r0, #9
1dca: 428b cmp r3, r1
1dcc: d301 bcc.n 1dd2 <__udivsi3+0x8e>
1dce: 024b lsls r3, r1, #9
1dd0: 1ac0 subs r0, r0, r3
1dd2: 4152 adcs r2, r2
1dd4: 0a03 lsrs r3, r0, #8
1dd6: 428b cmp r3, r1
1dd8: d301 bcc.n 1dde <__udivsi3+0x9a>
1dda: 020b lsls r3, r1, #8
1ddc: 1ac0 subs r0, r0, r3
1dde: 4152 adcs r2, r2
1de0: d2cd bcs.n 1d7e <__udivsi3+0x3a>
1de2: 09c3 lsrs r3, r0, #7
1de4: 428b cmp r3, r1
1de6: d301 bcc.n 1dec <__udivsi3+0xa8>
1de8: 01cb lsls r3, r1, #7
1dea: 1ac0 subs r0, r0, r3
1dec: 4152 adcs r2, r2
1dee: 0983 lsrs r3, r0, #6
1df0: 428b cmp r3, r1
1df2: d301 bcc.n 1df8 <__udivsi3+0xb4>
1df4: 018b lsls r3, r1, #6
1df6: 1ac0 subs r0, r0, r3
1df8: 4152 adcs r2, r2
1dfa: 0943 lsrs r3, r0, #5
1dfc: 428b cmp r3, r1
1dfe: d301 bcc.n 1e04 <__udivsi3+0xc0>
1e00: 014b lsls r3, r1, #5
1e02: 1ac0 subs r0, r0, r3
1e04: 4152 adcs r2, r2
1e06: 0903 lsrs r3, r0, #4
1e08: 428b cmp r3, r1
1e0a: d301 bcc.n 1e10 <__udivsi3+0xcc>
1e0c: 010b lsls r3, r1, #4
1e0e: 1ac0 subs r0, r0, r3
1e10: 4152 adcs r2, r2
1e12: 08c3 lsrs r3, r0, #3
1e14: 428b cmp r3, r1
1e16: d301 bcc.n 1e1c <__udivsi3+0xd8>
1e18: 00cb lsls r3, r1, #3
1e1a: 1ac0 subs r0, r0, r3
1e1c: 4152 adcs r2, r2
1e1e: 0883 lsrs r3, r0, #2
1e20: 428b cmp r3, r1
1e22: d301 bcc.n 1e28 <__udivsi3+0xe4>
1e24: 008b lsls r3, r1, #2
1e26: 1ac0 subs r0, r0, r3
1e28: 4152 adcs r2, r2
1e2a: 0843 lsrs r3, r0, #1
1e2c: 428b cmp r3, r1
1e2e: d301 bcc.n 1e34 <__udivsi3+0xf0>
1e30: 004b lsls r3, r1, #1
1e32: 1ac0 subs r0, r0, r3
1e34: 4152 adcs r2, r2
1e36: 1a41 subs r1, r0, r1
1e38: d200 bcs.n 1e3c <__udivsi3+0xf8>
1e3a: 4601 mov r1, r0
1e3c: 4152 adcs r2, r2
1e3e: 4610 mov r0, r2
1e40: 4770 bx lr
1e42: e7ff b.n 1e44 <__udivsi3+0x100>
1e44: b501 push {r0, lr}
1e46: 2000 movs r0, #0
1e48: f000 f806 bl 1e58 <__aeabi_idiv0>
1e4c: bd02 pop {r1, pc}
1e4e: 46c0 nop ; (mov r8, r8)
00001e50 <__aeabi_uidivmod>:
1e50: 2900 cmp r1, #0
1e52: d0f7 beq.n 1e44 <__udivsi3+0x100>
1e54: e776 b.n 1d44 <__udivsi3>
1e56: 4770 bx lr
00001e58 <__aeabi_idiv0>:
1e58: 4770 bx lr
1e5a: 46c0 nop ; (mov r8, r8)
00001e5c <__aeabi_lmul>:
1e5c: b5f0 push {r4, r5, r6, r7, lr}
1e5e: 46ce mov lr, r9
1e60: 4647 mov r7, r8
1e62: 0415 lsls r5, r2, #16
1e64: 0c2d lsrs r5, r5, #16
1e66: 002e movs r6, r5
1e68: b580 push {r7, lr}
1e6a: 0407 lsls r7, r0, #16
1e6c: 0c14 lsrs r4, r2, #16
1e6e: 0c3f lsrs r7, r7, #16
1e70: 4699 mov r9, r3
1e72: 0c03 lsrs r3, r0, #16
1e74: 437e muls r6, r7
1e76: 435d muls r5, r3
1e78: 4367 muls r7, r4
1e7a: 4363 muls r3, r4
1e7c: 197f adds r7, r7, r5
1e7e: 0c34 lsrs r4, r6, #16
1e80: 19e4 adds r4, r4, r7
1e82: 469c mov ip, r3
1e84: 42a5 cmp r5, r4
1e86: d903 bls.n 1e90 <__aeabi_lmul+0x34>
1e88: 2380 movs r3, #128 ; 0x80
1e8a: 025b lsls r3, r3, #9
1e8c: 4698 mov r8, r3
1e8e: 44c4 add ip, r8
1e90: 464b mov r3, r9
1e92: 4351 muls r1, r2
1e94: 4343 muls r3, r0
1e96: 0436 lsls r6, r6, #16
1e98: 0c36 lsrs r6, r6, #16
1e9a: 0c25 lsrs r5, r4, #16
1e9c: 0424 lsls r4, r4, #16
1e9e: 4465 add r5, ip
1ea0: 19a4 adds r4, r4, r6
1ea2: 1859 adds r1, r3, r1
1ea4: 1949 adds r1, r1, r5
1ea6: 0020 movs r0, r4
1ea8: bc0c pop {r2, r3}
1eaa: 4690 mov r8, r2
1eac: 4699 mov r9, r3
1eae: bdf0 pop {r4, r5, r6, r7, pc}
00001eb0 <__aeabi_dadd>:
1eb0: b5f8 push {r3, r4, r5, r6, r7, lr}
1eb2: 4645 mov r5, r8
1eb4: 46de mov lr, fp
1eb6: 4657 mov r7, sl
1eb8: 464e mov r6, r9
1eba: 030c lsls r4, r1, #12
1ebc: b5e0 push {r5, r6, r7, lr}
1ebe: 004e lsls r6, r1, #1
1ec0: 0fc9 lsrs r1, r1, #31
1ec2: 4688 mov r8, r1
1ec4: 000d movs r5, r1
1ec6: 0a61 lsrs r1, r4, #9
1ec8: 0f44 lsrs r4, r0, #29
1eca: 430c orrs r4, r1
1ecc: 00c7 lsls r7, r0, #3
1ece: 0319 lsls r1, r3, #12
1ed0: 0058 lsls r0, r3, #1
1ed2: 0fdb lsrs r3, r3, #31
1ed4: 469b mov fp, r3
1ed6: 0a4b lsrs r3, r1, #9
1ed8: 0f51 lsrs r1, r2, #29
1eda: 430b orrs r3, r1
1edc: 0d76 lsrs r6, r6, #21
1ede: 0d40 lsrs r0, r0, #21
1ee0: 0019 movs r1, r3
1ee2: 00d2 lsls r2, r2, #3
1ee4: 45d8 cmp r8, fp
1ee6: d100 bne.n 1eea <__aeabi_dadd+0x3a>
1ee8: e0ae b.n 2048 <STACK_SIZE+0x48>
1eea: 1a35 subs r5, r6, r0
1eec: 2d00 cmp r5, #0
1eee: dc00 bgt.n 1ef2 <__aeabi_dadd+0x42>
1ef0: e0f6 b.n 20e0 <STACK_SIZE+0xe0>
1ef2: 2800 cmp r0, #0
1ef4: d10f bne.n 1f16 <__aeabi_dadd+0x66>
1ef6: 4313 orrs r3, r2
1ef8: d100 bne.n 1efc <__aeabi_dadd+0x4c>
1efa: e0db b.n 20b4 <STACK_SIZE+0xb4>
1efc: 1e6b subs r3, r5, #1
1efe: 2b00 cmp r3, #0
1f00: d000 beq.n 1f04 <__aeabi_dadd+0x54>
1f02: e137 b.n 2174 <STACK_SIZE+0x174>
1f04: 1aba subs r2, r7, r2
1f06: 4297 cmp r7, r2
1f08: 41bf sbcs r7, r7
1f0a: 1a64 subs r4, r4, r1
1f0c: 427f negs r7, r7
1f0e: 1be4 subs r4, r4, r7
1f10: 2601 movs r6, #1
1f12: 0017 movs r7, r2
1f14: e024 b.n 1f60 <__aeabi_dadd+0xb0>
1f16: 4bc6 ldr r3, [pc, #792] ; (2230 <STACK_SIZE+0x230>)
1f18: 429e cmp r6, r3
1f1a: d04d beq.n 1fb8 <__aeabi_dadd+0x108>
1f1c: 2380 movs r3, #128 ; 0x80
1f1e: 041b lsls r3, r3, #16
1f20: 4319 orrs r1, r3
1f22: 2d38 cmp r5, #56 ; 0x38
1f24: dd00 ble.n 1f28 <__aeabi_dadd+0x78>
1f26: e107 b.n 2138 <STACK_SIZE+0x138>
1f28: 2d1f cmp r5, #31
1f2a: dd00 ble.n 1f2e <__aeabi_dadd+0x7e>
1f2c: e138 b.n 21a0 <STACK_SIZE+0x1a0>
1f2e: 2020 movs r0, #32
1f30: 1b43 subs r3, r0, r5
1f32: 469a mov sl, r3
1f34: 000b movs r3, r1
1f36: 4650 mov r0, sl
1f38: 4083 lsls r3, r0
1f3a: 4699 mov r9, r3
1f3c: 0013 movs r3, r2
1f3e: 4648 mov r0, r9
1f40: 40eb lsrs r3, r5
1f42: 4318 orrs r0, r3
1f44: 0003 movs r3, r0
1f46: 4650 mov r0, sl
1f48: 4082 lsls r2, r0
1f4a: 1e50 subs r0, r2, #1
1f4c: 4182 sbcs r2, r0
1f4e: 40e9 lsrs r1, r5
1f50: 431a orrs r2, r3
1f52: 1aba subs r2, r7, r2
1f54: 1a61 subs r1, r4, r1
1f56: 4297 cmp r7, r2
1f58: 41a4 sbcs r4, r4
1f5a: 0017 movs r7, r2
1f5c: 4264 negs r4, r4
1f5e: 1b0c subs r4, r1, r4
1f60: 0223 lsls r3, r4, #8
1f62: d562 bpl.n 202a <STACK_SIZE+0x2a>
1f64: 0264 lsls r4, r4, #9
1f66: 0a65 lsrs r5, r4, #9
1f68: 2d00 cmp r5, #0
1f6a: d100 bne.n 1f6e <__aeabi_dadd+0xbe>
1f6c: e0df b.n 212e <STACK_SIZE+0x12e>
1f6e: 0028 movs r0, r5
1f70: f001 fbe4 bl 373c <__clzsi2>
1f74: 0003 movs r3, r0
1f76: 3b08 subs r3, #8
1f78: 2b1f cmp r3, #31
1f7a: dd00 ble.n 1f7e <__aeabi_dadd+0xce>
1f7c: e0d2 b.n 2124 <STACK_SIZE+0x124>
1f7e: 2220 movs r2, #32
1f80: 003c movs r4, r7
1f82: 1ad2 subs r2, r2, r3
1f84: 409d lsls r5, r3
1f86: 40d4 lsrs r4, r2
1f88: 409f lsls r7, r3
1f8a: 4325 orrs r5, r4
1f8c: 429e cmp r6, r3
1f8e: dd00 ble.n 1f92 <__aeabi_dadd+0xe2>
1f90: e0c4 b.n 211c <STACK_SIZE+0x11c>
1f92: 1b9e subs r6, r3, r6
1f94: 1c73 adds r3, r6, #1
1f96: 2b1f cmp r3, #31
1f98: dd00 ble.n 1f9c <__aeabi_dadd+0xec>
1f9a: e0f1 b.n 2180 <STACK_SIZE+0x180>
1f9c: 2220 movs r2, #32
1f9e: 0038 movs r0, r7
1fa0: 0029 movs r1, r5
1fa2: 1ad2 subs r2, r2, r3
1fa4: 40d8 lsrs r0, r3
1fa6: 4091 lsls r1, r2
1fa8: 4097 lsls r7, r2
1faa: 002c movs r4, r5
1fac: 4301 orrs r1, r0
1fae: 1e78 subs r0, r7, #1
1fb0: 4187 sbcs r7, r0
1fb2: 40dc lsrs r4, r3
1fb4: 2600 movs r6, #0
1fb6: 430f orrs r7, r1
1fb8: 077b lsls r3, r7, #29
1fba: d009 beq.n 1fd0 <__aeabi_dadd+0x120>
1fbc: 230f movs r3, #15
1fbe: 403b ands r3, r7
1fc0: 2b04 cmp r3, #4
1fc2: d005 beq.n 1fd0 <__aeabi_dadd+0x120>
1fc4: 1d3b adds r3, r7, #4
1fc6: 42bb cmp r3, r7
1fc8: 41bf sbcs r7, r7
1fca: 427f negs r7, r7
1fcc: 19e4 adds r4, r4, r7
1fce: 001f movs r7, r3
1fd0: 0223 lsls r3, r4, #8
1fd2: d52c bpl.n 202e <STACK_SIZE+0x2e>
1fd4: 4b96 ldr r3, [pc, #600] ; (2230 <STACK_SIZE+0x230>)
1fd6: 3601 adds r6, #1
1fd8: 429e cmp r6, r3
1fda: d100 bne.n 1fde <__aeabi_dadd+0x12e>
1fdc: e09a b.n 2114 <STACK_SIZE+0x114>
1fde: 4645 mov r5, r8
1fe0: 4b94 ldr r3, [pc, #592] ; (2234 <STACK_SIZE+0x234>)
1fe2: 08ff lsrs r7, r7, #3
1fe4: 401c ands r4, r3
1fe6: 0760 lsls r0, r4, #29
1fe8: 0576 lsls r6, r6, #21
1fea: 0264 lsls r4, r4, #9
1fec: 4307 orrs r7, r0
1fee: 0b24 lsrs r4, r4, #12
1ff0: 0d76 lsrs r6, r6, #21
1ff2: 2100 movs r1, #0
1ff4: 0324 lsls r4, r4, #12
1ff6: 0b23 lsrs r3, r4, #12
1ff8: 0d0c lsrs r4, r1, #20
1ffa: 4a8f ldr r2, [pc, #572] ; (2238 <STACK_SIZE+0x238>)
1ffc: 0524 lsls r4, r4, #20
1ffe: 431c orrs r4, r3
2000: 4014 ands r4, r2
2002: 0533 lsls r3, r6, #20
2004: 4323 orrs r3, r4
2006: 005b lsls r3, r3, #1
2008: 07ed lsls r5, r5, #31
200a: 085b lsrs r3, r3, #1
200c: 432b orrs r3, r5
200e: 0038 movs r0, r7
2010: 0019 movs r1, r3
2012: bc3c pop {r2, r3, r4, r5}
2014: 4690 mov r8, r2
2016: 4699 mov r9, r3
2018: 46a2 mov sl, r4
201a: 46ab mov fp, r5
201c: bdf8 pop {r3, r4, r5, r6, r7, pc}
201e: 4664 mov r4, ip
2020: 4304 orrs r4, r0
2022: d100 bne.n 2026 <STACK_SIZE+0x26>
2024: e211 b.n 244a <STACK_SIZE+0x44a>
2026: 0004 movs r4, r0
2028: 4667 mov r7, ip
202a: 077b lsls r3, r7, #29
202c: d1c6 bne.n 1fbc <__aeabi_dadd+0x10c>
202e: 4645 mov r5, r8
2030: 0760 lsls r0, r4, #29
2032: 08ff lsrs r7, r7, #3
2034: 4307 orrs r7, r0
2036: 08e4 lsrs r4, r4, #3
2038: 4b7d ldr r3, [pc, #500] ; (2230 <STACK_SIZE+0x230>)
203a: 429e cmp r6, r3
203c: d030 beq.n 20a0 <STACK_SIZE+0xa0>
203e: 0324 lsls r4, r4, #12
2040: 0576 lsls r6, r6, #21
2042: 0b24 lsrs r4, r4, #12
2044: 0d76 lsrs r6, r6, #21
2046: e7d4 b.n 1ff2 <__aeabi_dadd+0x142>
2048: 1a33 subs r3, r6, r0
204a: 469a mov sl, r3
204c: 2b00 cmp r3, #0
204e: dd78 ble.n 2142 <STACK_SIZE+0x142>
2050: 2800 cmp r0, #0
2052: d031 beq.n 20b8 <STACK_SIZE+0xb8>
2054: 4876 ldr r0, [pc, #472] ; (2230 <STACK_SIZE+0x230>)
2056: 4286 cmp r6, r0
2058: d0ae beq.n 1fb8 <__aeabi_dadd+0x108>
205a: 2080 movs r0, #128 ; 0x80
205c: 0400 lsls r0, r0, #16
205e: 4301 orrs r1, r0
2060: 4653 mov r3, sl
2062: 2b38 cmp r3, #56 ; 0x38
2064: dc00 bgt.n 2068 <STACK_SIZE+0x68>
2066: e0e9 b.n 223c <STACK_SIZE+0x23c>
2068: 430a orrs r2, r1
206a: 1e51 subs r1, r2, #1
206c: 418a sbcs r2, r1
206e: 2100 movs r1, #0
2070: 19d2 adds r2, r2, r7
2072: 42ba cmp r2, r7
2074: 41bf sbcs r7, r7
2076: 1909 adds r1, r1, r4
2078: 427c negs r4, r7
207a: 0017 movs r7, r2
207c: 190c adds r4, r1, r4
207e: 0223 lsls r3, r4, #8
2080: d5d3 bpl.n 202a <STACK_SIZE+0x2a>
2082: 4b6b ldr r3, [pc, #428] ; (2230 <STACK_SIZE+0x230>)
2084: 3601 adds r6, #1
2086: 429e cmp r6, r3
2088: d100 bne.n 208c <STACK_SIZE+0x8c>
208a: e13a b.n 2302 <STACK_SIZE+0x302>
208c: 2001 movs r0, #1
208e: 4b69 ldr r3, [pc, #420] ; (2234 <STACK_SIZE+0x234>)
2090: 401c ands r4, r3
2092: 087b lsrs r3, r7, #1
2094: 4007 ands r7, r0
2096: 431f orrs r7, r3
2098: 07e0 lsls r0, r4, #31
209a: 4307 orrs r7, r0
209c: 0864 lsrs r4, r4, #1
209e: e78b b.n 1fb8 <__aeabi_dadd+0x108>
20a0: 0023 movs r3, r4
20a2: 433b orrs r3, r7
20a4: d100 bne.n 20a8 <STACK_SIZE+0xa8>
20a6: e1cb b.n 2440 <STACK_SIZE+0x440>
20a8: 2280 movs r2, #128 ; 0x80
20aa: 0312 lsls r2, r2, #12
20ac: 4314 orrs r4, r2
20ae: 0324 lsls r4, r4, #12
20b0: 0b24 lsrs r4, r4, #12
20b2: e79e b.n 1ff2 <__aeabi_dadd+0x142>
20b4: 002e movs r6, r5
20b6: e77f b.n 1fb8 <__aeabi_dadd+0x108>
20b8: 0008 movs r0, r1
20ba: 4310 orrs r0, r2
20bc: d100 bne.n 20c0 <STACK_SIZE+0xc0>
20be: e0b4 b.n 222a <STACK_SIZE+0x22a>
20c0: 1e58 subs r0, r3, #1
20c2: 2800 cmp r0, #0
20c4: d000 beq.n 20c8 <STACK_SIZE+0xc8>
20c6: e0de b.n 2286 <STACK_SIZE+0x286>
20c8: 18ba adds r2, r7, r2
20ca: 42ba cmp r2, r7
20cc: 419b sbcs r3, r3
20ce: 1864 adds r4, r4, r1
20d0: 425b negs r3, r3
20d2: 18e4 adds r4, r4, r3
20d4: 0017 movs r7, r2
20d6: 2601 movs r6, #1
20d8: 0223 lsls r3, r4, #8
20da: d5a6 bpl.n 202a <STACK_SIZE+0x2a>
20dc: 2602 movs r6, #2
20de: e7d5 b.n 208c <STACK_SIZE+0x8c>
20e0: 2d00 cmp r5, #0
20e2: d16e bne.n 21c2 <STACK_SIZE+0x1c2>
20e4: 1c70 adds r0, r6, #1
20e6: 0540 lsls r0, r0, #21
20e8: 0d40 lsrs r0, r0, #21
20ea: 2801 cmp r0, #1
20ec: dc00 bgt.n 20f0 <STACK_SIZE+0xf0>
20ee: e0f9 b.n 22e4 <STACK_SIZE+0x2e4>
20f0: 1ab8 subs r0, r7, r2
20f2: 4684 mov ip, r0
20f4: 4287 cmp r7, r0
20f6: 4180 sbcs r0, r0
20f8: 1ae5 subs r5, r4, r3
20fa: 4240 negs r0, r0
20fc: 1a2d subs r5, r5, r0
20fe: 0228 lsls r0, r5, #8
2100: d400 bmi.n 2104 <STACK_SIZE+0x104>
2102: e089 b.n 2218 <STACK_SIZE+0x218>
2104: 1bd7 subs r7, r2, r7
2106: 42ba cmp r2, r7
2108: 4192 sbcs r2, r2
210a: 1b1c subs r4, r3, r4
210c: 4252 negs r2, r2
210e: 1aa5 subs r5, r4, r2
2110: 46d8 mov r8, fp
2112: e729 b.n 1f68 <__aeabi_dadd+0xb8>
2114: 4645 mov r5, r8
2116: 2400 movs r4, #0
2118: 2700 movs r7, #0
211a: e76a b.n 1ff2 <__aeabi_dadd+0x142>
211c: 4c45 ldr r4, [pc, #276] ; (2234 <STACK_SIZE+0x234>)
211e: 1af6 subs r6, r6, r3
2120: 402c ands r4, r5
2122: e749 b.n 1fb8 <__aeabi_dadd+0x108>
2124: 003d movs r5, r7
2126: 3828 subs r0, #40 ; 0x28
2128: 4085 lsls r5, r0
212a: 2700 movs r7, #0
212c: e72e b.n 1f8c <__aeabi_dadd+0xdc>
212e: 0038 movs r0, r7
2130: f001 fb04 bl 373c <__clzsi2>
2134: 3020 adds r0, #32
2136: e71d b.n 1f74 <__aeabi_dadd+0xc4>
2138: 430a orrs r2, r1
213a: 1e51 subs r1, r2, #1
213c: 418a sbcs r2, r1
213e: 2100 movs r1, #0
2140: e707 b.n 1f52 <__aeabi_dadd+0xa2>
2142: 2b00 cmp r3, #0
2144: d000 beq.n 2148 <STACK_SIZE+0x148>
2146: e0f3 b.n 2330 <STACK_SIZE+0x330>
2148: 1c70 adds r0, r6, #1
214a: 0543 lsls r3, r0, #21
214c: 0d5b lsrs r3, r3, #21
214e: 2b01 cmp r3, #1
2150: dc00 bgt.n 2154 <STACK_SIZE+0x154>
2152: e0ad b.n 22b0 <STACK_SIZE+0x2b0>
2154: 4b36 ldr r3, [pc, #216] ; (2230 <STACK_SIZE+0x230>)
2156: 4298 cmp r0, r3
2158: d100 bne.n 215c <STACK_SIZE+0x15c>
215a: e0d1 b.n 2300 <STACK_SIZE+0x300>
215c: 18ba adds r2, r7, r2
215e: 42ba cmp r2, r7
2160: 41bf sbcs r7, r7
2162: 1864 adds r4, r4, r1
2164: 427f negs r7, r7
2166: 19e4 adds r4, r4, r7
2168: 07e7 lsls r7, r4, #31
216a: 0852 lsrs r2, r2, #1
216c: 4317 orrs r7, r2
216e: 0864 lsrs r4, r4, #1
2170: 0006 movs r6, r0
2172: e721 b.n 1fb8 <__aeabi_dadd+0x108>
2174: 482e ldr r0, [pc, #184] ; (2230 <STACK_SIZE+0x230>)
2176: 4285 cmp r5, r0
2178: d100 bne.n 217c <STACK_SIZE+0x17c>
217a: e093 b.n 22a4 <STACK_SIZE+0x2a4>
217c: 001d movs r5, r3
217e: e6d0 b.n 1f22 <__aeabi_dadd+0x72>
2180: 0029 movs r1, r5
2182: 3e1f subs r6, #31
2184: 40f1 lsrs r1, r6
2186: 2b20 cmp r3, #32
2188: d100 bne.n 218c <STACK_SIZE+0x18c>
218a: e08d b.n 22a8 <STACK_SIZE+0x2a8>
218c: 2240 movs r2, #64 ; 0x40
218e: 1ad3 subs r3, r2, r3
2190: 409d lsls r5, r3
2192: 432f orrs r7, r5
2194: 1e7d subs r5, r7, #1
2196: 41af sbcs r7, r5
2198: 2400 movs r4, #0
219a: 430f orrs r7, r1
219c: 2600 movs r6, #0
219e: e744 b.n 202a <STACK_SIZE+0x2a>
21a0: 002b movs r3, r5
21a2: 0008 movs r0, r1
21a4: 3b20 subs r3, #32
21a6: 40d8 lsrs r0, r3
21a8: 0003 movs r3, r0
21aa: 2d20 cmp r5, #32
21ac: d100 bne.n 21b0 <STACK_SIZE+0x1b0>
21ae: e07d b.n 22ac <STACK_SIZE+0x2ac>
21b0: 2040 movs r0, #64 ; 0x40
21b2: 1b45 subs r5, r0, r5
21b4: 40a9 lsls r1, r5
21b6: 430a orrs r2, r1
21b8: 1e51 subs r1, r2, #1
21ba: 418a sbcs r2, r1
21bc: 2100 movs r1, #0
21be: 431a orrs r2, r3
21c0: e6c7 b.n 1f52 <__aeabi_dadd+0xa2>
21c2: 2e00 cmp r6, #0
21c4: d050 beq.n 2268 <STACK_SIZE+0x268>
21c6: 4e1a ldr r6, [pc, #104] ; (2230 <STACK_SIZE+0x230>)
21c8: 42b0 cmp r0, r6
21ca: d057 beq.n 227c <STACK_SIZE+0x27c>
21cc: 2680 movs r6, #128 ; 0x80
21ce: 426b negs r3, r5
21d0: 4699 mov r9, r3
21d2: 0436 lsls r6, r6, #16
21d4: 4334 orrs r4, r6
21d6: 464b mov r3, r9
21d8: 2b38 cmp r3, #56 ; 0x38
21da: dd00 ble.n 21de <STACK_SIZE+0x1de>
21dc: e0d6 b.n 238c <STACK_SIZE+0x38c>
21de: 2b1f cmp r3, #31
21e0: dd00 ble.n 21e4 <STACK_SIZE+0x1e4>
21e2: e135 b.n 2450 <STACK_SIZE+0x450>
21e4: 2620 movs r6, #32
21e6: 1af5 subs r5, r6, r3
21e8: 0026 movs r6, r4
21ea: 40ae lsls r6, r5
21ec: 46b2 mov sl, r6
21ee: 003e movs r6, r7
21f0: 40de lsrs r6, r3
21f2: 46ac mov ip, r5
21f4: 0035 movs r5, r6
21f6: 4656 mov r6, sl
21f8: 432e orrs r6, r5
21fa: 4665 mov r5, ip
21fc: 40af lsls r7, r5
21fe: 1e7d subs r5, r7, #1
2200: 41af sbcs r7, r5
2202: 40dc lsrs r4, r3
2204: 4337 orrs r7, r6
2206: 1bd7 subs r7, r2, r7
2208: 42ba cmp r2, r7
220a: 4192 sbcs r2, r2
220c: 1b0c subs r4, r1, r4
220e: 4252 negs r2, r2
2210: 1aa4 subs r4, r4, r2
2212: 0006 movs r6, r0
2214: 46d8 mov r8, fp
2216: e6a3 b.n 1f60 <__aeabi_dadd+0xb0>
2218: 4664 mov r4, ip
221a: 4667 mov r7, ip
221c: 432c orrs r4, r5
221e: d000 beq.n 2222 <STACK_SIZE+0x222>
2220: e6a2 b.n 1f68 <__aeabi_dadd+0xb8>
2222: 2500 movs r5, #0
2224: 2600 movs r6, #0
2226: 2700 movs r7, #0
2228: e706 b.n 2038 <STACK_SIZE+0x38>
222a: 001e movs r6, r3
222c: e6c4 b.n 1fb8 <__aeabi_dadd+0x108>
222e: 46c0 nop ; (mov r8, r8)
2230: 000007ff .word 0x000007ff
2234: ff7fffff .word 0xff7fffff
2238: 800fffff .word 0x800fffff
223c: 2b1f cmp r3, #31
223e: dc63 bgt.n 2308 <STACK_SIZE+0x308>
2240: 2020 movs r0, #32
2242: 1ac3 subs r3, r0, r3
2244: 0008 movs r0, r1
2246: 4098 lsls r0, r3
2248: 469c mov ip, r3
224a: 4683 mov fp, r0
224c: 4653 mov r3, sl
224e: 0010 movs r0, r2
2250: 40d8 lsrs r0, r3
2252: 0003 movs r3, r0
2254: 4658 mov r0, fp
2256: 4318 orrs r0, r3
2258: 4663 mov r3, ip
225a: 409a lsls r2, r3
225c: 1e53 subs r3, r2, #1
225e: 419a sbcs r2, r3
2260: 4653 mov r3, sl
2262: 4302 orrs r2, r0
2264: 40d9 lsrs r1, r3
2266: e703 b.n 2070 <STACK_SIZE+0x70>
2268: 0026 movs r6, r4
226a: 433e orrs r6, r7
226c: d006 beq.n 227c <STACK_SIZE+0x27c>
226e: 43eb mvns r3, r5
2270: 4699 mov r9, r3
2272: 2b00 cmp r3, #0
2274: d0c7 beq.n 2206 <STACK_SIZE+0x206>
2276: 4e94 ldr r6, [pc, #592] ; (24c8 <STACK_SIZE+0x4c8>)
2278: 42b0 cmp r0, r6
227a: d1ac bne.n 21d6 <STACK_SIZE+0x1d6>
227c: 000c movs r4, r1
227e: 0017 movs r7, r2
2280: 0006 movs r6, r0
2282: 46d8 mov r8, fp
2284: e698 b.n 1fb8 <__aeabi_dadd+0x108>
2286: 4b90 ldr r3, [pc, #576] ; (24c8 <STACK_SIZE+0x4c8>)
2288: 459a cmp sl, r3
228a: d00b beq.n 22a4 <STACK_SIZE+0x2a4>
228c: 4682 mov sl, r0
228e: e6e7 b.n 2060 <STACK_SIZE+0x60>
2290: 2800 cmp r0, #0
2292: d000 beq.n 2296 <STACK_SIZE+0x296>
2294: e09e b.n 23d4 <STACK_SIZE+0x3d4>
2296: 0018 movs r0, r3
2298: 4310 orrs r0, r2
229a: d100 bne.n 229e <STACK_SIZE+0x29e>
229c: e0e9 b.n 2472 <STACK_SIZE+0x472>
229e: 001c movs r4, r3
22a0: 0017 movs r7, r2
22a2: 46d8 mov r8, fp
22a4: 4e88 ldr r6, [pc, #544] ; (24c8 <STACK_SIZE+0x4c8>)
22a6: e687 b.n 1fb8 <__aeabi_dadd+0x108>
22a8: 2500 movs r5, #0
22aa: e772 b.n 2192 <STACK_SIZE+0x192>
22ac: 2100 movs r1, #0
22ae: e782 b.n 21b6 <STACK_SIZE+0x1b6>
22b0: 0023 movs r3, r4
22b2: 433b orrs r3, r7
22b4: 2e00 cmp r6, #0
22b6: d000 beq.n 22ba <STACK_SIZE+0x2ba>
22b8: e0ab b.n 2412 <STACK_SIZE+0x412>
22ba: 2b00 cmp r3, #0
22bc: d100 bne.n 22c0 <STACK_SIZE+0x2c0>
22be: e0e7 b.n 2490 <STACK_SIZE+0x490>
22c0: 000b movs r3, r1
22c2: 4313 orrs r3, r2
22c4: d100 bne.n 22c8 <STACK_SIZE+0x2c8>
22c6: e677 b.n 1fb8 <__aeabi_dadd+0x108>
22c8: 18ba adds r2, r7, r2
22ca: 42ba cmp r2, r7
22cc: 41bf sbcs r7, r7
22ce: 1864 adds r4, r4, r1
22d0: 427f negs r7, r7
22d2: 19e4 adds r4, r4, r7
22d4: 0223 lsls r3, r4, #8
22d6: d400 bmi.n 22da <STACK_SIZE+0x2da>
22d8: e0f2 b.n 24c0 <STACK_SIZE+0x4c0>
22da: 4b7c ldr r3, [pc, #496] ; (24cc <STACK_SIZE+0x4cc>)
22dc: 0017 movs r7, r2
22de: 401c ands r4, r3
22e0: 0006 movs r6, r0
22e2: e669 b.n 1fb8 <__aeabi_dadd+0x108>
22e4: 0020 movs r0, r4
22e6: 4338 orrs r0, r7
22e8: 2e00 cmp r6, #0
22ea: d1d1 bne.n 2290 <STACK_SIZE+0x290>
22ec: 2800 cmp r0, #0
22ee: d15b bne.n 23a8 <STACK_SIZE+0x3a8>
22f0: 001c movs r4, r3
22f2: 4314 orrs r4, r2
22f4: d100 bne.n 22f8 <STACK_SIZE+0x2f8>
22f6: e0a8 b.n 244a <STACK_SIZE+0x44a>
22f8: 001c movs r4, r3
22fa: 0017 movs r7, r2
22fc: 46d8 mov r8, fp
22fe: e65b b.n 1fb8 <__aeabi_dadd+0x108>
2300: 0006 movs r6, r0
2302: 2400 movs r4, #0
2304: 2700 movs r7, #0
2306: e697 b.n 2038 <STACK_SIZE+0x38>
2308: 4650 mov r0, sl
230a: 000b movs r3, r1
230c: 3820 subs r0, #32
230e: 40c3 lsrs r3, r0
2310: 4699 mov r9, r3
2312: 4653 mov r3, sl
2314: 2b20 cmp r3, #32
2316: d100 bne.n 231a <STACK_SIZE+0x31a>
2318: e095 b.n 2446 <STACK_SIZE+0x446>
231a: 2340 movs r3, #64 ; 0x40
231c: 4650 mov r0, sl
231e: 1a1b subs r3, r3, r0
2320: 4099 lsls r1, r3
2322: 430a orrs r2, r1
2324: 1e51 subs r1, r2, #1
2326: 418a sbcs r2, r1
2328: 464b mov r3, r9
232a: 2100 movs r1, #0
232c: 431a orrs r2, r3
232e: e69f b.n 2070 <STACK_SIZE+0x70>
2330: 2e00 cmp r6, #0
2332: d130 bne.n 2396 <STACK_SIZE+0x396>
2334: 0026 movs r6, r4
2336: 433e orrs r6, r7
2338: d067 beq.n 240a <STACK_SIZE+0x40a>
233a: 43db mvns r3, r3
233c: 469a mov sl, r3
233e: 2b00 cmp r3, #0
2340: d01c beq.n 237c <STACK_SIZE+0x37c>
2342: 4e61 ldr r6, [pc, #388] ; (24c8 <STACK_SIZE+0x4c8>)
2344: 42b0 cmp r0, r6
2346: d060 beq.n 240a <STACK_SIZE+0x40a>
2348: 4653 mov r3, sl
234a: 2b38 cmp r3, #56 ; 0x38
234c: dd00 ble.n 2350 <STACK_SIZE+0x350>
234e: e096 b.n 247e <STACK_SIZE+0x47e>
2350: 2b1f cmp r3, #31
2352: dd00 ble.n 2356 <STACK_SIZE+0x356>
2354: e09f b.n 2496 <STACK_SIZE+0x496>
2356: 2620 movs r6, #32
2358: 1af3 subs r3, r6, r3
235a: 0026 movs r6, r4
235c: 409e lsls r6, r3
235e: 469c mov ip, r3
2360: 46b3 mov fp, r6
2362: 4653 mov r3, sl
2364: 003e movs r6, r7
2366: 40de lsrs r6, r3
2368: 0033 movs r3, r6
236a: 465e mov r6, fp
236c: 431e orrs r6, r3
236e: 4663 mov r3, ip
2370: 409f lsls r7, r3
2372: 1e7b subs r3, r7, #1
2374: 419f sbcs r7, r3
2376: 4653 mov r3, sl
2378: 40dc lsrs r4, r3
237a: 4337 orrs r7, r6
237c: 18bf adds r7, r7, r2
237e: 4297 cmp r7, r2
2380: 4192 sbcs r2, r2
2382: 1864 adds r4, r4, r1
2384: 4252 negs r2, r2
2386: 18a4 adds r4, r4, r2
2388: 0006 movs r6, r0
238a: e678 b.n 207e <STACK_SIZE+0x7e>
238c: 4327 orrs r7, r4
238e: 1e7c subs r4, r7, #1
2390: 41a7 sbcs r7, r4
2392: 2400 movs r4, #0
2394: e737 b.n 2206 <STACK_SIZE+0x206>
2396: 4e4c ldr r6, [pc, #304] ; (24c8 <STACK_SIZE+0x4c8>)
2398: 42b0 cmp r0, r6
239a: d036 beq.n 240a <STACK_SIZE+0x40a>
239c: 2680 movs r6, #128 ; 0x80
239e: 425b negs r3, r3
23a0: 0436 lsls r6, r6, #16
23a2: 469a mov sl, r3
23a4: 4334 orrs r4, r6
23a6: e7cf b.n 2348 <STACK_SIZE+0x348>
23a8: 0018 movs r0, r3
23aa: 4310 orrs r0, r2
23ac: d100 bne.n 23b0 <STACK_SIZE+0x3b0>
23ae: e603 b.n 1fb8 <__aeabi_dadd+0x108>
23b0: 1ab8 subs r0, r7, r2
23b2: 4684 mov ip, r0
23b4: 4567 cmp r7, ip
23b6: 41ad sbcs r5, r5
23b8: 1ae0 subs r0, r4, r3
23ba: 426d negs r5, r5
23bc: 1b40 subs r0, r0, r5
23be: 0205 lsls r5, r0, #8
23c0: d400 bmi.n 23c4 <STACK_SIZE+0x3c4>
23c2: e62c b.n 201e <STACK_SIZE+0x1e>
23c4: 1bd7 subs r7, r2, r7
23c6: 42ba cmp r2, r7
23c8: 4192 sbcs r2, r2
23ca: 1b1c subs r4, r3, r4
23cc: 4252 negs r2, r2
23ce: 1aa4 subs r4, r4, r2
23d0: 46d8 mov r8, fp
23d2: e5f1 b.n 1fb8 <__aeabi_dadd+0x108>
23d4: 0018 movs r0, r3
23d6: 4310 orrs r0, r2
23d8: d100 bne.n 23dc <STACK_SIZE+0x3dc>
23da: e763 b.n 22a4 <STACK_SIZE+0x2a4>
23dc: 08f8 lsrs r0, r7, #3
23de: 0767 lsls r7, r4, #29
23e0: 4307 orrs r7, r0
23e2: 2080 movs r0, #128 ; 0x80
23e4: 08e4 lsrs r4, r4, #3
23e6: 0300 lsls r0, r0, #12
23e8: 4204 tst r4, r0
23ea: d008 beq.n 23fe <STACK_SIZE+0x3fe>
23ec: 08dd lsrs r5, r3, #3
23ee: 4205 tst r5, r0
23f0: d105 bne.n 23fe <STACK_SIZE+0x3fe>
23f2: 08d2 lsrs r2, r2, #3
23f4: 0759 lsls r1, r3, #29
23f6: 4311 orrs r1, r2
23f8: 000f movs r7, r1
23fa: 002c movs r4, r5
23fc: 46d8 mov r8, fp
23fe: 0f7b lsrs r3, r7, #29
2400: 00e4 lsls r4, r4, #3
2402: 431c orrs r4, r3
2404: 00ff lsls r7, r7, #3
2406: 4e30 ldr r6, [pc, #192] ; (24c8 <STACK_SIZE+0x4c8>)
2408: e5d6 b.n 1fb8 <__aeabi_dadd+0x108>
240a: 000c movs r4, r1
240c: 0017 movs r7, r2
240e: 0006 movs r6, r0
2410: e5d2 b.n 1fb8 <__aeabi_dadd+0x108>
2412: 2b00 cmp r3, #0
2414: d038 beq.n 2488 <STACK_SIZE+0x488>
2416: 000b movs r3, r1
2418: 4313 orrs r3, r2
241a: d100 bne.n 241e <STACK_SIZE+0x41e>
241c: e742 b.n 22a4 <STACK_SIZE+0x2a4>
241e: 08f8 lsrs r0, r7, #3
2420: 0767 lsls r7, r4, #29
2422: 4307 orrs r7, r0
2424: 2080 movs r0, #128 ; 0x80
2426: 08e4 lsrs r4, r4, #3
2428: 0300 lsls r0, r0, #12
242a: 4204 tst r4, r0
242c: d0e7 beq.n 23fe <STACK_SIZE+0x3fe>
242e: 08cb lsrs r3, r1, #3
2430: 4203 tst r3, r0
2432: d1e4 bne.n 23fe <STACK_SIZE+0x3fe>
2434: 08d2 lsrs r2, r2, #3
2436: 0749 lsls r1, r1, #29
2438: 4311 orrs r1, r2
243a: 000f movs r7, r1
243c: 001c movs r4, r3
243e: e7de b.n 23fe <STACK_SIZE+0x3fe>
2440: 2700 movs r7, #0
2442: 2400 movs r4, #0
2444: e5d5 b.n 1ff2 <__aeabi_dadd+0x142>
2446: 2100 movs r1, #0
2448: e76b b.n 2322 <STACK_SIZE+0x322>
244a: 2500 movs r5, #0
244c: 2700 movs r7, #0
244e: e5f3 b.n 2038 <STACK_SIZE+0x38>
2450: 464e mov r6, r9
2452: 0025 movs r5, r4
2454: 3e20 subs r6, #32
2456: 40f5 lsrs r5, r6
2458: 464b mov r3, r9
245a: 002e movs r6, r5
245c: 2b20 cmp r3, #32
245e: d02d beq.n 24bc <STACK_SIZE+0x4bc>
2460: 2540 movs r5, #64 ; 0x40
2462: 1aed subs r5, r5, r3
2464: 40ac lsls r4, r5
2466: 4327 orrs r7, r4
2468: 1e7c subs r4, r7, #1
246a: 41a7 sbcs r7, r4
246c: 2400 movs r4, #0
246e: 4337 orrs r7, r6
2470: e6c9 b.n 2206 <STACK_SIZE+0x206>
2472: 2480 movs r4, #128 ; 0x80
2474: 2500 movs r5, #0
2476: 0324 lsls r4, r4, #12
2478: 4e13 ldr r6, [pc, #76] ; (24c8 <STACK_SIZE+0x4c8>)
247a: 2700 movs r7, #0
247c: e5dc b.n 2038 <STACK_SIZE+0x38>
247e: 4327 orrs r7, r4
2480: 1e7c subs r4, r7, #1
2482: 41a7 sbcs r7, r4
2484: 2400 movs r4, #0
2486: e779 b.n 237c <STACK_SIZE+0x37c>
2488: 000c movs r4, r1
248a: 0017 movs r7, r2
248c: 4e0e ldr r6, [pc, #56] ; (24c8 <STACK_SIZE+0x4c8>)
248e: e593 b.n 1fb8 <__aeabi_dadd+0x108>
2490: 000c movs r4, r1
2492: 0017 movs r7, r2
2494: e590 b.n 1fb8 <__aeabi_dadd+0x108>
2496: 4656 mov r6, sl
2498: 0023 movs r3, r4
249a: 3e20 subs r6, #32
249c: 40f3 lsrs r3, r6
249e: 4699 mov r9, r3
24a0: 4653 mov r3, sl
24a2: 2b20 cmp r3, #32
24a4: d00e beq.n 24c4 <STACK_SIZE+0x4c4>
24a6: 2340 movs r3, #64 ; 0x40
24a8: 4656 mov r6, sl
24aa: 1b9b subs r3, r3, r6
24ac: 409c lsls r4, r3
24ae: 4327 orrs r7, r4
24b0: 1e7c subs r4, r7, #1
24b2: 41a7 sbcs r7, r4
24b4: 464b mov r3, r9
24b6: 2400 movs r4, #0
24b8: 431f orrs r7, r3
24ba: e75f b.n 237c <STACK_SIZE+0x37c>
24bc: 2400 movs r4, #0
24be: e7d2 b.n 2466 <STACK_SIZE+0x466>
24c0: 0017 movs r7, r2
24c2: e5b2 b.n 202a <STACK_SIZE+0x2a>
24c4: 2400 movs r4, #0
24c6: e7f2 b.n 24ae <STACK_SIZE+0x4ae>
24c8: 000007ff .word 0x000007ff
24cc: ff7fffff .word 0xff7fffff
000024d0 <__aeabi_ddiv>:
24d0: b5f0 push {r4, r5, r6, r7, lr}
24d2: 4657 mov r7, sl
24d4: 4645 mov r5, r8
24d6: 46de mov lr, fp
24d8: 464e mov r6, r9
24da: b5e0 push {r5, r6, r7, lr}
24dc: 004c lsls r4, r1, #1
24de: 030e lsls r6, r1, #12
24e0: b087 sub sp, #28
24e2: 4683 mov fp, r0
24e4: 4692 mov sl, r2
24e6: 001d movs r5, r3
24e8: 4680 mov r8, r0
24ea: 0b36 lsrs r6, r6, #12
24ec: 0d64 lsrs r4, r4, #21
24ee: 0fcf lsrs r7, r1, #31
24f0: 2c00 cmp r4, #0
24f2: d04f beq.n 2594 <__aeabi_ddiv+0xc4>
24f4: 4b6f ldr r3, [pc, #444] ; (26b4 <__aeabi_ddiv+0x1e4>)
24f6: 429c cmp r4, r3
24f8: d035 beq.n 2566 <__aeabi_ddiv+0x96>
24fa: 2380 movs r3, #128 ; 0x80
24fc: 0f42 lsrs r2, r0, #29
24fe: 041b lsls r3, r3, #16
2500: 00f6 lsls r6, r6, #3
2502: 4313 orrs r3, r2
2504: 4333 orrs r3, r6
2506: 4699 mov r9, r3
2508: 00c3 lsls r3, r0, #3
250a: 4698 mov r8, r3
250c: 4b6a ldr r3, [pc, #424] ; (26b8 <__aeabi_ddiv+0x1e8>)
250e: 2600 movs r6, #0
2510: 469c mov ip, r3
2512: 2300 movs r3, #0
2514: 4464 add r4, ip
2516: 9303 str r3, [sp, #12]
2518: 032b lsls r3, r5, #12
251a: 0b1b lsrs r3, r3, #12
251c: 469b mov fp, r3
251e: 006b lsls r3, r5, #1
2520: 0fed lsrs r5, r5, #31
2522: 4650 mov r0, sl
2524: 0d5b lsrs r3, r3, #21
2526: 9501 str r5, [sp, #4]
2528: d05e beq.n 25e8 <__aeabi_ddiv+0x118>
252a: 4a62 ldr r2, [pc, #392] ; (26b4 <__aeabi_ddiv+0x1e4>)
252c: 4293 cmp r3, r2
252e: d053 beq.n 25d8 <__aeabi_ddiv+0x108>
2530: 465a mov r2, fp
2532: 00d1 lsls r1, r2, #3
2534: 2280 movs r2, #128 ; 0x80
2536: 0f40 lsrs r0, r0, #29
2538: 0412 lsls r2, r2, #16
253a: 4302 orrs r2, r0
253c: 430a orrs r2, r1
253e: 4693 mov fp, r2
2540: 4652 mov r2, sl
2542: 00d1 lsls r1, r2, #3
2544: 4a5c ldr r2, [pc, #368] ; (26b8 <__aeabi_ddiv+0x1e8>)
2546: 4694 mov ip, r2
2548: 2200 movs r2, #0
254a: 4463 add r3, ip
254c: 0038 movs r0, r7
254e: 4068 eors r0, r5
2550: 4684 mov ip, r0
2552: 9002 str r0, [sp, #8]
2554: 1ae4 subs r4, r4, r3
2556: 4316 orrs r6, r2
2558: 2e0f cmp r6, #15
255a: d900 bls.n 255e <__aeabi_ddiv+0x8e>
255c: e0b4 b.n 26c8 <__aeabi_ddiv+0x1f8>
255e: 4b57 ldr r3, [pc, #348] ; (26bc <__aeabi_ddiv+0x1ec>)
2560: 00b6 lsls r6, r6, #2
2562: 599b ldr r3, [r3, r6]
2564: 469f mov pc, r3
2566: 0003 movs r3, r0
2568: 4333 orrs r3, r6
256a: 4699 mov r9, r3
256c: d16c bne.n 2648 <__aeabi_ddiv+0x178>
256e: 2300 movs r3, #0
2570: 4698 mov r8, r3
2572: 3302 adds r3, #2
2574: 2608 movs r6, #8
2576: 9303 str r3, [sp, #12]
2578: e7ce b.n 2518 <__aeabi_ddiv+0x48>
257a: 46cb mov fp, r9
257c: 4641 mov r1, r8
257e: 9a03 ldr r2, [sp, #12]
2580: 9701 str r7, [sp, #4]
2582: 2a02 cmp r2, #2
2584: d165 bne.n 2652 <__aeabi_ddiv+0x182>
2586: 9b01 ldr r3, [sp, #4]
2588: 4c4a ldr r4, [pc, #296] ; (26b4 <__aeabi_ddiv+0x1e4>)
258a: 469c mov ip, r3
258c: 2300 movs r3, #0
258e: 2200 movs r2, #0
2590: 4698 mov r8, r3
2592: e06b b.n 266c <__aeabi_ddiv+0x19c>
2594: 0003 movs r3, r0
2596: 4333 orrs r3, r6
2598: 4699 mov r9, r3
259a: d04e beq.n 263a <__aeabi_ddiv+0x16a>
259c: 2e00 cmp r6, #0
259e: d100 bne.n 25a2 <__aeabi_ddiv+0xd2>
25a0: e1bc b.n 291c <__aeabi_ddiv+0x44c>
25a2: 0030 movs r0, r6
25a4: f001 f8ca bl 373c <__clzsi2>
25a8: 0003 movs r3, r0
25aa: 3b0b subs r3, #11
25ac: 2b1c cmp r3, #28
25ae: dd00 ble.n 25b2 <__aeabi_ddiv+0xe2>
25b0: e1ac b.n 290c <__aeabi_ddiv+0x43c>
25b2: 221d movs r2, #29
25b4: 1ad3 subs r3, r2, r3
25b6: 465a mov r2, fp
25b8: 0001 movs r1, r0
25ba: 40da lsrs r2, r3
25bc: 3908 subs r1, #8
25be: 408e lsls r6, r1
25c0: 0013 movs r3, r2
25c2: 4333 orrs r3, r6
25c4: 4699 mov r9, r3
25c6: 465b mov r3, fp
25c8: 408b lsls r3, r1
25ca: 4698 mov r8, r3
25cc: 2300 movs r3, #0
25ce: 4c3c ldr r4, [pc, #240] ; (26c0 <__aeabi_ddiv+0x1f0>)
25d0: 2600 movs r6, #0
25d2: 1a24 subs r4, r4, r0
25d4: 9303 str r3, [sp, #12]
25d6: e79f b.n 2518 <__aeabi_ddiv+0x48>
25d8: 4651 mov r1, sl
25da: 465a mov r2, fp
25dc: 4311 orrs r1, r2
25de: d129 bne.n 2634 <__aeabi_ddiv+0x164>
25e0: 2200 movs r2, #0
25e2: 4693 mov fp, r2
25e4: 3202 adds r2, #2
25e6: e7b1 b.n 254c <__aeabi_ddiv+0x7c>
25e8: 4659 mov r1, fp
25ea: 4301 orrs r1, r0
25ec: d01e beq.n 262c <__aeabi_ddiv+0x15c>
25ee: 465b mov r3, fp
25f0: 2b00 cmp r3, #0
25f2: d100 bne.n 25f6 <__aeabi_ddiv+0x126>
25f4: e19e b.n 2934 <__aeabi_ddiv+0x464>
25f6: 4658 mov r0, fp
25f8: f001 f8a0 bl 373c <__clzsi2>
25fc: 0003 movs r3, r0
25fe: 3b0b subs r3, #11
2600: 2b1c cmp r3, #28
2602: dd00 ble.n 2606 <__aeabi_ddiv+0x136>
2604: e18f b.n 2926 <__aeabi_ddiv+0x456>
2606: 0002 movs r2, r0
2608: 4659 mov r1, fp
260a: 3a08 subs r2, #8
260c: 4091 lsls r1, r2
260e: 468b mov fp, r1
2610: 211d movs r1, #29
2612: 1acb subs r3, r1, r3
2614: 4651 mov r1, sl
2616: 40d9 lsrs r1, r3
2618: 000b movs r3, r1
261a: 4659 mov r1, fp
261c: 430b orrs r3, r1
261e: 4651 mov r1, sl
2620: 469b mov fp, r3
2622: 4091 lsls r1, r2
2624: 4b26 ldr r3, [pc, #152] ; (26c0 <__aeabi_ddiv+0x1f0>)
2626: 2200 movs r2, #0
2628: 1a1b subs r3, r3, r0
262a: e78f b.n 254c <__aeabi_ddiv+0x7c>
262c: 2300 movs r3, #0
262e: 2201 movs r2, #1
2630: 469b mov fp, r3
2632: e78b b.n 254c <__aeabi_ddiv+0x7c>
2634: 4651 mov r1, sl
2636: 2203 movs r2, #3
2638: e788 b.n 254c <__aeabi_ddiv+0x7c>
263a: 2300 movs r3, #0
263c: 4698 mov r8, r3
263e: 3301 adds r3, #1
2640: 2604 movs r6, #4
2642: 2400 movs r4, #0
2644: 9303 str r3, [sp, #12]
2646: e767 b.n 2518 <__aeabi_ddiv+0x48>
2648: 2303 movs r3, #3
264a: 46b1 mov r9, r6
264c: 9303 str r3, [sp, #12]
264e: 260c movs r6, #12
2650: e762 b.n 2518 <__aeabi_ddiv+0x48>
2652: 2a03 cmp r2, #3
2654: d100 bne.n 2658 <__aeabi_ddiv+0x188>
2656: e25c b.n 2b12 <__aeabi_ddiv+0x642>
2658: 9b01 ldr r3, [sp, #4]
265a: 2a01 cmp r2, #1
265c: d000 beq.n 2660 <__aeabi_ddiv+0x190>
265e: e1e4 b.n 2a2a <__aeabi_ddiv+0x55a>
2660: 4013 ands r3, r2
2662: 469c mov ip, r3
2664: 2300 movs r3, #0
2666: 2400 movs r4, #0
2668: 2200 movs r2, #0
266a: 4698 mov r8, r3
266c: 2100 movs r1, #0
266e: 0312 lsls r2, r2, #12
2670: 0b13 lsrs r3, r2, #12
2672: 0d0a lsrs r2, r1, #20
2674: 0512 lsls r2, r2, #20
2676: 431a orrs r2, r3
2678: 0523 lsls r3, r4, #20
267a: 4c12 ldr r4, [pc, #72] ; (26c4 <__aeabi_ddiv+0x1f4>)
267c: 4640 mov r0, r8
267e: 4022 ands r2, r4
2680: 4313 orrs r3, r2
2682: 4662 mov r2, ip
2684: 005b lsls r3, r3, #1
2686: 07d2 lsls r2, r2, #31
2688: 085b lsrs r3, r3, #1
268a: 4313 orrs r3, r2
268c: 0019 movs r1, r3
268e: b007 add sp, #28
2690: bc3c pop {r2, r3, r4, r5}
2692: 4690 mov r8, r2
2694: 4699 mov r9, r3
2696: 46a2 mov sl, r4
2698: 46ab mov fp, r5
269a: bdf0 pop {r4, r5, r6, r7, pc}
269c: 2300 movs r3, #0
269e: 2280 movs r2, #128 ; 0x80
26a0: 469c mov ip, r3
26a2: 0312 lsls r2, r2, #12
26a4: 4698 mov r8, r3
26a6: 4c03 ldr r4, [pc, #12] ; (26b4 <__aeabi_ddiv+0x1e4>)
26a8: e7e0 b.n 266c <__aeabi_ddiv+0x19c>
26aa: 2300 movs r3, #0
26ac: 4c01 ldr r4, [pc, #4] ; (26b4 <__aeabi_ddiv+0x1e4>)
26ae: 2200 movs r2, #0
26b0: 4698 mov r8, r3
26b2: e7db b.n 266c <__aeabi_ddiv+0x19c>
26b4: 000007ff .word 0x000007ff
26b8: fffffc01 .word 0xfffffc01
26bc: 00004908 .word 0x00004908
26c0: fffffc0d .word 0xfffffc0d
26c4: 800fffff .word 0x800fffff
26c8: 45d9 cmp r9, fp
26ca: d900 bls.n 26ce <__aeabi_ddiv+0x1fe>
26cc: e139 b.n 2942 <__aeabi_ddiv+0x472>
26ce: d100 bne.n 26d2 <__aeabi_ddiv+0x202>
26d0: e134 b.n 293c <__aeabi_ddiv+0x46c>
26d2: 2300 movs r3, #0
26d4: 4646 mov r6, r8
26d6: 464d mov r5, r9
26d8: 469a mov sl, r3
26da: 3c01 subs r4, #1
26dc: 465b mov r3, fp
26de: 0e0a lsrs r2, r1, #24
26e0: 021b lsls r3, r3, #8
26e2: 431a orrs r2, r3
26e4: 020b lsls r3, r1, #8
26e6: 0c17 lsrs r7, r2, #16
26e8: 9303 str r3, [sp, #12]
26ea: 0413 lsls r3, r2, #16
26ec: 0c1b lsrs r3, r3, #16
26ee: 0039 movs r1, r7
26f0: 0028 movs r0, r5
26f2: 4690 mov r8, r2
26f4: 9301 str r3, [sp, #4]
26f6: f7ff fb25 bl 1d44 <__udivsi3>
26fa: 0002 movs r2, r0
26fc: 9b01 ldr r3, [sp, #4]
26fe: 4683 mov fp, r0
2700: 435a muls r2, r3
2702: 0028 movs r0, r5
2704: 0039 movs r1, r7
2706: 4691 mov r9, r2
2708: f7ff fba2 bl 1e50 <__aeabi_uidivmod>
270c: 0c35 lsrs r5, r6, #16
270e: 0409 lsls r1, r1, #16
2710: 430d orrs r5, r1
2712: 45a9 cmp r9, r5
2714: d90d bls.n 2732 <__aeabi_ddiv+0x262>
2716: 465b mov r3, fp
2718: 4445 add r5, r8
271a: 3b01 subs r3, #1
271c: 45a8 cmp r8, r5
271e: d900 bls.n 2722 <__aeabi_ddiv+0x252>
2720: e13a b.n 2998 <__aeabi_ddiv+0x4c8>
2722: 45a9 cmp r9, r5
2724: d800 bhi.n 2728 <__aeabi_ddiv+0x258>
2726: e137 b.n 2998 <__aeabi_ddiv+0x4c8>
2728: 2302 movs r3, #2
272a: 425b negs r3, r3
272c: 469c mov ip, r3
272e: 4445 add r5, r8
2730: 44e3 add fp, ip
2732: 464b mov r3, r9
2734: 1aeb subs r3, r5, r3
2736: 0039 movs r1, r7
2738: 0018 movs r0, r3
273a: 9304 str r3, [sp, #16]
273c: f7ff fb02 bl 1d44 <__udivsi3>
2740: 9b01 ldr r3, [sp, #4]
2742: 0005 movs r5, r0
2744: 4343 muls r3, r0
2746: 0039 movs r1, r7
2748: 9804 ldr r0, [sp, #16]
274a: 4699 mov r9, r3
274c: f7ff fb80 bl 1e50 <__aeabi_uidivmod>
2750: 0433 lsls r3, r6, #16
2752: 0409 lsls r1, r1, #16
2754: 0c1b lsrs r3, r3, #16
2756: 430b orrs r3, r1
2758: 4599 cmp r9, r3
275a: d909 bls.n 2770 <__aeabi_ddiv+0x2a0>
275c: 4443 add r3, r8
275e: 1e6a subs r2, r5, #1
2760: 4598 cmp r8, r3
2762: d900 bls.n 2766 <__aeabi_ddiv+0x296>
2764: e11a b.n 299c <__aeabi_ddiv+0x4cc>
2766: 4599 cmp r9, r3
2768: d800 bhi.n 276c <__aeabi_ddiv+0x29c>
276a: e117 b.n 299c <__aeabi_ddiv+0x4cc>
276c: 3d02 subs r5, #2
276e: 4443 add r3, r8
2770: 464a mov r2, r9
2772: 1a9b subs r3, r3, r2
2774: 465a mov r2, fp
2776: 0412 lsls r2, r2, #16
2778: 432a orrs r2, r5
277a: 9903 ldr r1, [sp, #12]
277c: 4693 mov fp, r2
277e: 0c10 lsrs r0, r2, #16
2780: 0c0a lsrs r2, r1, #16
2782: 4691 mov r9, r2
2784: 0409 lsls r1, r1, #16
2786: 465a mov r2, fp
2788: 0c09 lsrs r1, r1, #16
278a: 464e mov r6, r9
278c: 000d movs r5, r1
278e: 0412 lsls r2, r2, #16
2790: 0c12 lsrs r2, r2, #16
2792: 4345 muls r5, r0
2794: 9105 str r1, [sp, #20]
2796: 4351 muls r1, r2
2798: 4372 muls r2, r6
279a: 4370 muls r0, r6
279c: 1952 adds r2, r2, r5
279e: 0c0e lsrs r6, r1, #16
27a0: 18b2 adds r2, r6, r2
27a2: 4295 cmp r5, r2
27a4: d903 bls.n 27ae <__aeabi_ddiv+0x2de>
27a6: 2580 movs r5, #128 ; 0x80
27a8: 026d lsls r5, r5, #9
27aa: 46ac mov ip, r5
27ac: 4460 add r0, ip
27ae: 0c15 lsrs r5, r2, #16
27b0: 0409 lsls r1, r1, #16
27b2: 0412 lsls r2, r2, #16
27b4: 0c09 lsrs r1, r1, #16
27b6: 1828 adds r0, r5, r0
27b8: 1852 adds r2, r2, r1
27ba: 4283 cmp r3, r0
27bc: d200 bcs.n 27c0 <__aeabi_ddiv+0x2f0>
27be: e0ce b.n 295e <__aeabi_ddiv+0x48e>
27c0: d100 bne.n 27c4 <__aeabi_ddiv+0x2f4>
27c2: e0c8 b.n 2956 <__aeabi_ddiv+0x486>
27c4: 1a1d subs r5, r3, r0
27c6: 4653 mov r3, sl
27c8: 1a9e subs r6, r3, r2
27ca: 45b2 cmp sl, r6
27cc: 4192 sbcs r2, r2
27ce: 4252 negs r2, r2
27d0: 1aab subs r3, r5, r2
27d2: 469a mov sl, r3
27d4: 4598 cmp r8, r3
27d6: d100 bne.n 27da <__aeabi_ddiv+0x30a>
27d8: e117 b.n 2a0a <__aeabi_ddiv+0x53a>
27da: 0039 movs r1, r7
27dc: 0018 movs r0, r3
27de: f7ff fab1 bl 1d44 <__udivsi3>
27e2: 9b01 ldr r3, [sp, #4]
27e4: 0005 movs r5, r0
27e6: 4343 muls r3, r0
27e8: 0039 movs r1, r7
27ea: 4650 mov r0, sl
27ec: 9304 str r3, [sp, #16]
27ee: f7ff fb2f bl 1e50 <__aeabi_uidivmod>
27f2: 9804 ldr r0, [sp, #16]
27f4: 040b lsls r3, r1, #16
27f6: 0c31 lsrs r1, r6, #16
27f8: 4319 orrs r1, r3
27fa: 4288 cmp r0, r1
27fc: d909 bls.n 2812 <__aeabi_ddiv+0x342>
27fe: 4441 add r1, r8
2800: 1e6b subs r3, r5, #1
2802: 4588 cmp r8, r1
2804: d900 bls.n 2808 <__aeabi_ddiv+0x338>
2806: e107 b.n 2a18 <__aeabi_ddiv+0x548>
2808: 4288 cmp r0, r1
280a: d800 bhi.n 280e <__aeabi_ddiv+0x33e>
280c: e104 b.n 2a18 <__aeabi_ddiv+0x548>
280e: 3d02 subs r5, #2
2810: 4441 add r1, r8
2812: 9b04 ldr r3, [sp, #16]
2814: 1acb subs r3, r1, r3
2816: 0018 movs r0, r3
2818: 0039 movs r1, r7
281a: 9304 str r3, [sp, #16]
281c: f7ff fa92 bl 1d44 <__udivsi3>
2820: 9b01 ldr r3, [sp, #4]
2822: 4682 mov sl, r0
2824: 4343 muls r3, r0
2826: 0039 movs r1, r7
2828: 9804 ldr r0, [sp, #16]
282a: 9301 str r3, [sp, #4]
282c: f7ff fb10 bl 1e50 <__aeabi_uidivmod>
2830: 9801 ldr r0, [sp, #4]
2832: 040b lsls r3, r1, #16
2834: 0431 lsls r1, r6, #16
2836: 0c09 lsrs r1, r1, #16
2838: 4319 orrs r1, r3
283a: 4288 cmp r0, r1
283c: d90d bls.n 285a <__aeabi_ddiv+0x38a>
283e: 4653 mov r3, sl
2840: 4441 add r1, r8
2842: 3b01 subs r3, #1
2844: 4588 cmp r8, r1
2846: d900 bls.n 284a <__aeabi_ddiv+0x37a>
2848: e0e8 b.n 2a1c <__aeabi_ddiv+0x54c>
284a: 4288 cmp r0, r1
284c: d800 bhi.n 2850 <__aeabi_ddiv+0x380>
284e: e0e5 b.n 2a1c <__aeabi_ddiv+0x54c>
2850: 2302 movs r3, #2
2852: 425b negs r3, r3
2854: 469c mov ip, r3
2856: 4441 add r1, r8
2858: 44e2 add sl, ip
285a: 9b01 ldr r3, [sp, #4]
285c: 042d lsls r5, r5, #16
285e: 1ace subs r6, r1, r3
2860: 4651 mov r1, sl
2862: 4329 orrs r1, r5
2864: 9d05 ldr r5, [sp, #20]
2866: 464f mov r7, r9
2868: 002a movs r2, r5
286a: 040b lsls r3, r1, #16
286c: 0c08 lsrs r0, r1, #16
286e: 0c1b lsrs r3, r3, #16
2870: 435a muls r2, r3
2872: 4345 muls r5, r0
2874: 437b muls r3, r7
2876: 4378 muls r0, r7
2878: 195b adds r3, r3, r5
287a: 0c17 lsrs r7, r2, #16
287c: 18fb adds r3, r7, r3
287e: 429d cmp r5, r3
2880: d903 bls.n 288a <__aeabi_ddiv+0x3ba>
2882: 2580 movs r5, #128 ; 0x80
2884: 026d lsls r5, r5, #9
2886: 46ac mov ip, r5
2888: 4460 add r0, ip
288a: 0c1d lsrs r5, r3, #16
288c: 0412 lsls r2, r2, #16
288e: 041b lsls r3, r3, #16
2890: 0c12 lsrs r2, r2, #16
2892: 1828 adds r0, r5, r0
2894: 189b adds r3, r3, r2
2896: 4286 cmp r6, r0
2898: d200 bcs.n 289c <__aeabi_ddiv+0x3cc>
289a: e093 b.n 29c4 <__aeabi_ddiv+0x4f4>
289c: d100 bne.n 28a0 <__aeabi_ddiv+0x3d0>
289e: e08e b.n 29be <__aeabi_ddiv+0x4ee>
28a0: 2301 movs r3, #1
28a2: 4319 orrs r1, r3
28a4: 4ba0 ldr r3, [pc, #640] ; (2b28 <__aeabi_ddiv+0x658>)
28a6: 18e3 adds r3, r4, r3
28a8: 2b00 cmp r3, #0
28aa: dc00 bgt.n 28ae <__aeabi_ddiv+0x3de>
28ac: e099 b.n 29e2 <__aeabi_ddiv+0x512>
28ae: 074a lsls r2, r1, #29
28b0: d000 beq.n 28b4 <__aeabi_ddiv+0x3e4>
28b2: e09e b.n 29f2 <__aeabi_ddiv+0x522>
28b4: 465a mov r2, fp
28b6: 01d2 lsls r2, r2, #7
28b8: d506 bpl.n 28c8 <__aeabi_ddiv+0x3f8>
28ba: 465a mov r2, fp
28bc: 4b9b ldr r3, [pc, #620] ; (2b2c <__aeabi_ddiv+0x65c>)
28be: 401a ands r2, r3
28c0: 2380 movs r3, #128 ; 0x80
28c2: 4693 mov fp, r2
28c4: 00db lsls r3, r3, #3
28c6: 18e3 adds r3, r4, r3
28c8: 4a99 ldr r2, [pc, #612] ; (2b30 <__aeabi_ddiv+0x660>)
28ca: 4293 cmp r3, r2
28cc: dd68 ble.n 29a0 <__aeabi_ddiv+0x4d0>
28ce: 2301 movs r3, #1
28d0: 9a02 ldr r2, [sp, #8]
28d2: 4c98 ldr r4, [pc, #608] ; (2b34 <__aeabi_ddiv+0x664>)
28d4: 401a ands r2, r3
28d6: 2300 movs r3, #0
28d8: 4694 mov ip, r2
28da: 4698 mov r8, r3
28dc: 2200 movs r2, #0
28de: e6c5 b.n 266c <__aeabi_ddiv+0x19c>
28e0: 2280 movs r2, #128 ; 0x80
28e2: 464b mov r3, r9
28e4: 0312 lsls r2, r2, #12
28e6: 4213 tst r3, r2
28e8: d00a beq.n 2900 <__aeabi_ddiv+0x430>
28ea: 465b mov r3, fp
28ec: 4213 tst r3, r2
28ee: d106 bne.n 28fe <__aeabi_ddiv+0x42e>
28f0: 431a orrs r2, r3
28f2: 0312 lsls r2, r2, #12
28f4: 0b12 lsrs r2, r2, #12
28f6: 46ac mov ip, r5
28f8: 4688 mov r8, r1
28fa: 4c8e ldr r4, [pc, #568] ; (2b34 <__aeabi_ddiv+0x664>)
28fc: e6b6 b.n 266c <__aeabi_ddiv+0x19c>
28fe: 464b mov r3, r9
2900: 431a orrs r2, r3
2902: 0312 lsls r2, r2, #12
2904: 0b12 lsrs r2, r2, #12
2906: 46bc mov ip, r7
2908: 4c8a ldr r4, [pc, #552] ; (2b34 <__aeabi_ddiv+0x664>)
290a: e6af b.n 266c <__aeabi_ddiv+0x19c>
290c: 0003 movs r3, r0
290e: 465a mov r2, fp
2910: 3b28 subs r3, #40 ; 0x28
2912: 409a lsls r2, r3
2914: 2300 movs r3, #0
2916: 4691 mov r9, r2
2918: 4698 mov r8, r3
291a: e657 b.n 25cc <__aeabi_ddiv+0xfc>
291c: 4658 mov r0, fp
291e: f000 ff0d bl 373c <__clzsi2>
2922: 3020 adds r0, #32
2924: e640 b.n 25a8 <__aeabi_ddiv+0xd8>
2926: 0003 movs r3, r0
2928: 4652 mov r2, sl
292a: 3b28 subs r3, #40 ; 0x28
292c: 409a lsls r2, r3
292e: 2100 movs r1, #0
2930: 4693 mov fp, r2
2932: e677 b.n 2624 <__aeabi_ddiv+0x154>
2934: f000 ff02 bl 373c <__clzsi2>
2938: 3020 adds r0, #32
293a: e65f b.n 25fc <__aeabi_ddiv+0x12c>
293c: 4588 cmp r8, r1
293e: d200 bcs.n 2942 <__aeabi_ddiv+0x472>
2940: e6c7 b.n 26d2 <__aeabi_ddiv+0x202>
2942: 464b mov r3, r9
2944: 07de lsls r6, r3, #31
2946: 085d lsrs r5, r3, #1
2948: 4643 mov r3, r8
294a: 085b lsrs r3, r3, #1
294c: 431e orrs r6, r3
294e: 4643 mov r3, r8
2950: 07db lsls r3, r3, #31
2952: 469a mov sl, r3
2954: e6c2 b.n 26dc <__aeabi_ddiv+0x20c>
2956: 2500 movs r5, #0
2958: 4592 cmp sl, r2
295a: d300 bcc.n 295e <__aeabi_ddiv+0x48e>
295c: e733 b.n 27c6 <__aeabi_ddiv+0x2f6>
295e: 9e03 ldr r6, [sp, #12]
2960: 4659 mov r1, fp
2962: 46b4 mov ip, r6
2964: 44e2 add sl, ip
2966: 45b2 cmp sl, r6
2968: 41ad sbcs r5, r5
296a: 426d negs r5, r5
296c: 4445 add r5, r8
296e: 18eb adds r3, r5, r3
2970: 3901 subs r1, #1
2972: 4598 cmp r8, r3
2974: d207 bcs.n 2986 <__aeabi_ddiv+0x4b6>
2976: 4298 cmp r0, r3
2978: d900 bls.n 297c <__aeabi_ddiv+0x4ac>
297a: e07f b.n 2a7c <__aeabi_ddiv+0x5ac>
297c: d100 bne.n 2980 <__aeabi_ddiv+0x4b0>
297e: e0bc b.n 2afa <__aeabi_ddiv+0x62a>
2980: 1a1d subs r5, r3, r0
2982: 468b mov fp, r1
2984: e71f b.n 27c6 <__aeabi_ddiv+0x2f6>
2986: 4598 cmp r8, r3
2988: d1fa bne.n 2980 <__aeabi_ddiv+0x4b0>
298a: 9d03 ldr r5, [sp, #12]
298c: 4555 cmp r5, sl
298e: d9f2 bls.n 2976 <__aeabi_ddiv+0x4a6>
2990: 4643 mov r3, r8
2992: 468b mov fp, r1
2994: 1a1d subs r5, r3, r0
2996: e716 b.n 27c6 <__aeabi_ddiv+0x2f6>
2998: 469b mov fp, r3
299a: e6ca b.n 2732 <__aeabi_ddiv+0x262>
299c: 0015 movs r5, r2
299e: e6e7 b.n 2770 <__aeabi_ddiv+0x2a0>
29a0: 465a mov r2, fp
29a2: 08c9 lsrs r1, r1, #3
29a4: 0752 lsls r2, r2, #29
29a6: 430a orrs r2, r1
29a8: 055b lsls r3, r3, #21
29aa: 4690 mov r8, r2
29ac: 0d5c lsrs r4, r3, #21
29ae: 465a mov r2, fp
29b0: 2301 movs r3, #1
29b2: 9902 ldr r1, [sp, #8]
29b4: 0252 lsls r2, r2, #9
29b6: 4019 ands r1, r3
29b8: 0b12 lsrs r2, r2, #12
29ba: 468c mov ip, r1
29bc: e656 b.n 266c <__aeabi_ddiv+0x19c>
29be: 2b00 cmp r3, #0
29c0: d100 bne.n 29c4 <__aeabi_ddiv+0x4f4>
29c2: e76f b.n 28a4 <__aeabi_ddiv+0x3d4>
29c4: 4446 add r6, r8
29c6: 1e4a subs r2, r1, #1
29c8: 45b0 cmp r8, r6
29ca: d929 bls.n 2a20 <__aeabi_ddiv+0x550>
29cc: 0011 movs r1, r2
29ce: 4286 cmp r6, r0
29d0: d000 beq.n 29d4 <__aeabi_ddiv+0x504>
29d2: e765 b.n 28a0 <__aeabi_ddiv+0x3d0>
29d4: 9a03 ldr r2, [sp, #12]
29d6: 4293 cmp r3, r2
29d8: d000 beq.n 29dc <__aeabi_ddiv+0x50c>
29da: e761 b.n 28a0 <__aeabi_ddiv+0x3d0>
29dc: e762 b.n 28a4 <__aeabi_ddiv+0x3d4>
29de: 2101 movs r1, #1
29e0: 4249 negs r1, r1
29e2: 2001 movs r0, #1
29e4: 1ac2 subs r2, r0, r3
29e6: 2a38 cmp r2, #56 ; 0x38
29e8: dd21 ble.n 2a2e <__aeabi_ddiv+0x55e>
29ea: 9b02 ldr r3, [sp, #8]
29ec: 4003 ands r3, r0
29ee: 469c mov ip, r3
29f0: e638 b.n 2664 <__aeabi_ddiv+0x194>
29f2: 220f movs r2, #15
29f4: 400a ands r2, r1
29f6: 2a04 cmp r2, #4
29f8: d100 bne.n 29fc <__aeabi_ddiv+0x52c>
29fa: e75b b.n 28b4 <__aeabi_ddiv+0x3e4>
29fc: 000a movs r2, r1
29fe: 1d11 adds r1, r2, #4
2a00: 4291 cmp r1, r2
2a02: 4192 sbcs r2, r2
2a04: 4252 negs r2, r2
2a06: 4493 add fp, r2
2a08: e754 b.n 28b4 <__aeabi_ddiv+0x3e4>
2a0a: 4b47 ldr r3, [pc, #284] ; (2b28 <__aeabi_ddiv+0x658>)
2a0c: 18e3 adds r3, r4, r3
2a0e: 2b00 cmp r3, #0
2a10: dde5 ble.n 29de <__aeabi_ddiv+0x50e>
2a12: 2201 movs r2, #1
2a14: 4252 negs r2, r2
2a16: e7f2 b.n 29fe <__aeabi_ddiv+0x52e>
2a18: 001d movs r5, r3
2a1a: e6fa b.n 2812 <__aeabi_ddiv+0x342>
2a1c: 469a mov sl, r3
2a1e: e71c b.n 285a <__aeabi_ddiv+0x38a>
2a20: 42b0 cmp r0, r6
2a22: d839 bhi.n 2a98 <__aeabi_ddiv+0x5c8>
2a24: d06e beq.n 2b04 <__aeabi_ddiv+0x634>
2a26: 0011 movs r1, r2
2a28: e73a b.n 28a0 <__aeabi_ddiv+0x3d0>
2a2a: 9302 str r3, [sp, #8]
2a2c: e73a b.n 28a4 <__aeabi_ddiv+0x3d4>
2a2e: 2a1f cmp r2, #31
2a30: dc3c bgt.n 2aac <__aeabi_ddiv+0x5dc>
2a32: 2320 movs r3, #32
2a34: 1a9b subs r3, r3, r2
2a36: 000c movs r4, r1
2a38: 4658 mov r0, fp
2a3a: 4099 lsls r1, r3
2a3c: 4098 lsls r0, r3
2a3e: 1e4b subs r3, r1, #1
2a40: 4199 sbcs r1, r3
2a42: 465b mov r3, fp
2a44: 40d4 lsrs r4, r2
2a46: 40d3 lsrs r3, r2
2a48: 4320 orrs r0, r4
2a4a: 4308 orrs r0, r1
2a4c: 001a movs r2, r3
2a4e: 0743 lsls r3, r0, #29
2a50: d009 beq.n 2a66 <__aeabi_ddiv+0x596>
2a52: 230f movs r3, #15
2a54: 4003 ands r3, r0
2a56: 2b04 cmp r3, #4
2a58: d005 beq.n 2a66 <__aeabi_ddiv+0x596>
2a5a: 0001 movs r1, r0
2a5c: 1d08 adds r0, r1, #4
2a5e: 4288 cmp r0, r1
2a60: 419b sbcs r3, r3
2a62: 425b negs r3, r3
2a64: 18d2 adds r2, r2, r3
2a66: 0213 lsls r3, r2, #8
2a68: d53a bpl.n 2ae0 <__aeabi_ddiv+0x610>
2a6a: 2301 movs r3, #1
2a6c: 9a02 ldr r2, [sp, #8]
2a6e: 2401 movs r4, #1
2a70: 401a ands r2, r3
2a72: 2300 movs r3, #0
2a74: 4694 mov ip, r2
2a76: 4698 mov r8, r3
2a78: 2200 movs r2, #0
2a7a: e5f7 b.n 266c <__aeabi_ddiv+0x19c>
2a7c: 2102 movs r1, #2
2a7e: 4249 negs r1, r1
2a80: 468c mov ip, r1
2a82: 9d03 ldr r5, [sp, #12]
2a84: 44e3 add fp, ip
2a86: 46ac mov ip, r5
2a88: 44e2 add sl, ip
2a8a: 45aa cmp sl, r5
2a8c: 41ad sbcs r5, r5
2a8e: 426d negs r5, r5
2a90: 4445 add r5, r8
2a92: 18ed adds r5, r5, r3
2a94: 1a2d subs r5, r5, r0
2a96: e696 b.n 27c6 <__aeabi_ddiv+0x2f6>
2a98: 1e8a subs r2, r1, #2
2a9a: 9903 ldr r1, [sp, #12]
2a9c: 004d lsls r5, r1, #1
2a9e: 428d cmp r5, r1
2aa0: 4189 sbcs r1, r1
2aa2: 4249 negs r1, r1
2aa4: 4441 add r1, r8
2aa6: 1876 adds r6, r6, r1
2aa8: 9503 str r5, [sp, #12]
2aaa: e78f b.n 29cc <__aeabi_ddiv+0x4fc>
2aac: 201f movs r0, #31
2aae: 4240 negs r0, r0
2ab0: 1ac3 subs r3, r0, r3
2ab2: 4658 mov r0, fp
2ab4: 40d8 lsrs r0, r3
2ab6: 0003 movs r3, r0
2ab8: 2a20 cmp r2, #32
2aba: d028 beq.n 2b0e <__aeabi_ddiv+0x63e>
2abc: 2040 movs r0, #64 ; 0x40
2abe: 465d mov r5, fp
2ac0: 1a82 subs r2, r0, r2
2ac2: 4095 lsls r5, r2
2ac4: 4329 orrs r1, r5
2ac6: 1e4a subs r2, r1, #1
2ac8: 4191 sbcs r1, r2
2aca: 4319 orrs r1, r3
2acc: 2307 movs r3, #7
2ace: 2200 movs r2, #0
2ad0: 400b ands r3, r1
2ad2: d009 beq.n 2ae8 <__aeabi_ddiv+0x618>
2ad4: 230f movs r3, #15
2ad6: 2200 movs r2, #0
2ad8: 400b ands r3, r1
2ada: 0008 movs r0, r1
2adc: 2b04 cmp r3, #4
2ade: d1bd bne.n 2a5c <__aeabi_ddiv+0x58c>
2ae0: 0001 movs r1, r0
2ae2: 0753 lsls r3, r2, #29
2ae4: 0252 lsls r2, r2, #9
2ae6: 0b12 lsrs r2, r2, #12
2ae8: 08c9 lsrs r1, r1, #3
2aea: 4319 orrs r1, r3
2aec: 2301 movs r3, #1
2aee: 4688 mov r8, r1
2af0: 9902 ldr r1, [sp, #8]
2af2: 2400 movs r4, #0
2af4: 4019 ands r1, r3
2af6: 468c mov ip, r1
2af8: e5b8 b.n 266c <__aeabi_ddiv+0x19c>
2afa: 4552 cmp r2, sl
2afc: d8be bhi.n 2a7c <__aeabi_ddiv+0x5ac>
2afe: 468b mov fp, r1
2b00: 2500 movs r5, #0
2b02: e660 b.n 27c6 <__aeabi_ddiv+0x2f6>
2b04: 9d03 ldr r5, [sp, #12]
2b06: 429d cmp r5, r3
2b08: d3c6 bcc.n 2a98 <__aeabi_ddiv+0x5c8>
2b0a: 0011 movs r1, r2
2b0c: e762 b.n 29d4 <__aeabi_ddiv+0x504>
2b0e: 2500 movs r5, #0
2b10: e7d8 b.n 2ac4 <__aeabi_ddiv+0x5f4>
2b12: 2280 movs r2, #128 ; 0x80
2b14: 465b mov r3, fp
2b16: 0312 lsls r2, r2, #12
2b18: 431a orrs r2, r3
2b1a: 9b01 ldr r3, [sp, #4]
2b1c: 0312 lsls r2, r2, #12
2b1e: 0b12 lsrs r2, r2, #12
2b20: 469c mov ip, r3
2b22: 4688 mov r8, r1
2b24: 4c03 ldr r4, [pc, #12] ; (2b34 <__aeabi_ddiv+0x664>)
2b26: e5a1 b.n 266c <__aeabi_ddiv+0x19c>
2b28: 000003ff .word 0x000003ff
2b2c: feffffff .word 0xfeffffff
2b30: 000007fe .word 0x000007fe
2b34: 000007ff .word 0x000007ff
00002b38 <__aeabi_dmul>:
2b38: b5f0 push {r4, r5, r6, r7, lr}
2b3a: 4657 mov r7, sl
2b3c: 4645 mov r5, r8
2b3e: 46de mov lr, fp
2b40: 464e mov r6, r9
2b42: b5e0 push {r5, r6, r7, lr}
2b44: 030c lsls r4, r1, #12
2b46: 4698 mov r8, r3
2b48: 004e lsls r6, r1, #1
2b4a: 0b23 lsrs r3, r4, #12
2b4c: b087 sub sp, #28
2b4e: 0007 movs r7, r0
2b50: 4692 mov sl, r2
2b52: 469b mov fp, r3
2b54: 0d76 lsrs r6, r6, #21
2b56: 0fcd lsrs r5, r1, #31
2b58: 2e00 cmp r6, #0
2b5a: d06b beq.n 2c34 <__aeabi_dmul+0xfc>
2b5c: 4b6d ldr r3, [pc, #436] ; (2d14 <__aeabi_dmul+0x1dc>)
2b5e: 429e cmp r6, r3
2b60: d035 beq.n 2bce <__aeabi_dmul+0x96>
2b62: 2480 movs r4, #128 ; 0x80
2b64: 465b mov r3, fp
2b66: 0f42 lsrs r2, r0, #29
2b68: 0424 lsls r4, r4, #16
2b6a: 00db lsls r3, r3, #3
2b6c: 4314 orrs r4, r2
2b6e: 431c orrs r4, r3
2b70: 00c3 lsls r3, r0, #3
2b72: 4699 mov r9, r3
2b74: 4b68 ldr r3, [pc, #416] ; (2d18 <__aeabi_dmul+0x1e0>)
2b76: 46a3 mov fp, r4
2b78: 469c mov ip, r3
2b7a: 2300 movs r3, #0
2b7c: 2700 movs r7, #0
2b7e: 4466 add r6, ip
2b80: 9302 str r3, [sp, #8]
2b82: 4643 mov r3, r8
2b84: 031c lsls r4, r3, #12
2b86: 005a lsls r2, r3, #1
2b88: 0fdb lsrs r3, r3, #31
2b8a: 4650 mov r0, sl
2b8c: 0b24 lsrs r4, r4, #12
2b8e: 0d52 lsrs r2, r2, #21
2b90: 4698 mov r8, r3
2b92: d100 bne.n 2b96 <__aeabi_dmul+0x5e>
2b94: e076 b.n 2c84 <__aeabi_dmul+0x14c>
2b96: 4b5f ldr r3, [pc, #380] ; (2d14 <__aeabi_dmul+0x1dc>)
2b98: 429a cmp r2, r3
2b9a: d06d beq.n 2c78 <__aeabi_dmul+0x140>
2b9c: 2380 movs r3, #128 ; 0x80
2b9e: 0f41 lsrs r1, r0, #29
2ba0: 041b lsls r3, r3, #16
2ba2: 430b orrs r3, r1
2ba4: 495c ldr r1, [pc, #368] ; (2d18 <__aeabi_dmul+0x1e0>)
2ba6: 00e4 lsls r4, r4, #3
2ba8: 468c mov ip, r1
2baa: 431c orrs r4, r3
2bac: 00c3 lsls r3, r0, #3
2bae: 2000 movs r0, #0
2bb0: 4462 add r2, ip
2bb2: 4641 mov r1, r8
2bb4: 18b6 adds r6, r6, r2
2bb6: 4069 eors r1, r5
2bb8: 1c72 adds r2, r6, #1
2bba: 9101 str r1, [sp, #4]
2bbc: 4694 mov ip, r2
2bbe: 4307 orrs r7, r0
2bc0: 2f0f cmp r7, #15
2bc2: d900 bls.n 2bc6 <__aeabi_dmul+0x8e>
2bc4: e0b0 b.n 2d28 <__aeabi_dmul+0x1f0>
2bc6: 4a55 ldr r2, [pc, #340] ; (2d1c <__aeabi_dmul+0x1e4>)
2bc8: 00bf lsls r7, r7, #2
2bca: 59d2 ldr r2, [r2, r7]
2bcc: 4697 mov pc, r2
2bce: 465b mov r3, fp
2bd0: 4303 orrs r3, r0
2bd2: 4699 mov r9, r3
2bd4: d000 beq.n 2bd8 <__aeabi_dmul+0xa0>
2bd6: e087 b.n 2ce8 <__aeabi_dmul+0x1b0>
2bd8: 2300 movs r3, #0
2bda: 469b mov fp, r3
2bdc: 3302 adds r3, #2
2bde: 2708 movs r7, #8
2be0: 9302 str r3, [sp, #8]
2be2: e7ce b.n 2b82 <__aeabi_dmul+0x4a>
2be4: 4642 mov r2, r8
2be6: 9201 str r2, [sp, #4]
2be8: 2802 cmp r0, #2
2bea: d067 beq.n 2cbc <__aeabi_dmul+0x184>
2bec: 2803 cmp r0, #3
2bee: d100 bne.n 2bf2 <__aeabi_dmul+0xba>
2bf0: e20e b.n 3010 <__aeabi_dmul+0x4d8>
2bf2: 2801 cmp r0, #1
2bf4: d000 beq.n 2bf8 <__aeabi_dmul+0xc0>
2bf6: e162 b.n 2ebe <__aeabi_dmul+0x386>
2bf8: 2300 movs r3, #0
2bfa: 2400 movs r4, #0
2bfc: 2200 movs r2, #0
2bfe: 4699 mov r9, r3
2c00: 9901 ldr r1, [sp, #4]
2c02: 4001 ands r1, r0
2c04: b2cd uxtb r5, r1
2c06: 2100 movs r1, #0
2c08: 0312 lsls r2, r2, #12
2c0a: 0d0b lsrs r3, r1, #20
2c0c: 0b12 lsrs r2, r2, #12
2c0e: 051b lsls r3, r3, #20
2c10: 4313 orrs r3, r2
2c12: 4a43 ldr r2, [pc, #268] ; (2d20 <__aeabi_dmul+0x1e8>)
2c14: 0524 lsls r4, r4, #20
2c16: 4013 ands r3, r2
2c18: 431c orrs r4, r3
2c1a: 0064 lsls r4, r4, #1
2c1c: 07ed lsls r5, r5, #31
2c1e: 0864 lsrs r4, r4, #1
2c20: 432c orrs r4, r5
2c22: 4648 mov r0, r9
2c24: 0021 movs r1, r4
2c26: b007 add sp, #28
2c28: bc3c pop {r2, r3, r4, r5}
2c2a: 4690 mov r8, r2
2c2c: 4699 mov r9, r3
2c2e: 46a2 mov sl, r4
2c30: 46ab mov fp, r5
2c32: bdf0 pop {r4, r5, r6, r7, pc}
2c34: 4303 orrs r3, r0
2c36: 4699 mov r9, r3
2c38: d04f beq.n 2cda <__aeabi_dmul+0x1a2>
2c3a: 465b mov r3, fp
2c3c: 2b00 cmp r3, #0
2c3e: d100 bne.n 2c42 <__aeabi_dmul+0x10a>
2c40: e189 b.n 2f56 <__aeabi_dmul+0x41e>
2c42: 4658 mov r0, fp
2c44: f000 fd7a bl 373c <__clzsi2>
2c48: 0003 movs r3, r0
2c4a: 3b0b subs r3, #11
2c4c: 2b1c cmp r3, #28
2c4e: dd00 ble.n 2c52 <__aeabi_dmul+0x11a>
2c50: e17a b.n 2f48 <__aeabi_dmul+0x410>
2c52: 221d movs r2, #29
2c54: 1ad3 subs r3, r2, r3
2c56: 003a movs r2, r7
2c58: 0001 movs r1, r0
2c5a: 465c mov r4, fp
2c5c: 40da lsrs r2, r3
2c5e: 3908 subs r1, #8
2c60: 408c lsls r4, r1
2c62: 0013 movs r3, r2
2c64: 408f lsls r7, r1
2c66: 4323 orrs r3, r4
2c68: 469b mov fp, r3
2c6a: 46b9 mov r9, r7
2c6c: 2300 movs r3, #0
2c6e: 4e2d ldr r6, [pc, #180] ; (2d24 <__aeabi_dmul+0x1ec>)
2c70: 2700 movs r7, #0
2c72: 1a36 subs r6, r6, r0
2c74: 9302 str r3, [sp, #8]
2c76: e784 b.n 2b82 <__aeabi_dmul+0x4a>
2c78: 4653 mov r3, sl
2c7a: 4323 orrs r3, r4
2c7c: d12a bne.n 2cd4 <__aeabi_dmul+0x19c>
2c7e: 2400 movs r4, #0
2c80: 2002 movs r0, #2
2c82: e796 b.n 2bb2 <__aeabi_dmul+0x7a>
2c84: 4653 mov r3, sl
2c86: 4323 orrs r3, r4
2c88: d020 beq.n 2ccc <__aeabi_dmul+0x194>
2c8a: 2c00 cmp r4, #0
2c8c: d100 bne.n 2c90 <__aeabi_dmul+0x158>
2c8e: e157 b.n 2f40 <__aeabi_dmul+0x408>
2c90: 0020 movs r0, r4
2c92: f000 fd53 bl 373c <__clzsi2>
2c96: 0003 movs r3, r0
2c98: 3b0b subs r3, #11
2c9a: 2b1c cmp r3, #28
2c9c: dd00 ble.n 2ca0 <__aeabi_dmul+0x168>
2c9e: e149 b.n 2f34 <__aeabi_dmul+0x3fc>
2ca0: 211d movs r1, #29
2ca2: 1acb subs r3, r1, r3
2ca4: 4651 mov r1, sl
2ca6: 0002 movs r2, r0
2ca8: 40d9 lsrs r1, r3
2caa: 4653 mov r3, sl
2cac: 3a08 subs r2, #8
2cae: 4094 lsls r4, r2
2cb0: 4093 lsls r3, r2
2cb2: 430c orrs r4, r1
2cb4: 4a1b ldr r2, [pc, #108] ; (2d24 <__aeabi_dmul+0x1ec>)
2cb6: 1a12 subs r2, r2, r0
2cb8: 2000 movs r0, #0
2cba: e77a b.n 2bb2 <__aeabi_dmul+0x7a>
2cbc: 2501 movs r5, #1
2cbe: 9b01 ldr r3, [sp, #4]
2cc0: 4c14 ldr r4, [pc, #80] ; (2d14 <__aeabi_dmul+0x1dc>)
2cc2: 401d ands r5, r3
2cc4: 2300 movs r3, #0
2cc6: 2200 movs r2, #0
2cc8: 4699 mov r9, r3
2cca: e79c b.n 2c06 <__aeabi_dmul+0xce>
2ccc: 2400 movs r4, #0
2cce: 2200 movs r2, #0
2cd0: 2001 movs r0, #1
2cd2: e76e b.n 2bb2 <__aeabi_dmul+0x7a>
2cd4: 4653 mov r3, sl
2cd6: 2003 movs r0, #3
2cd8: e76b b.n 2bb2 <__aeabi_dmul+0x7a>
2cda: 2300 movs r3, #0
2cdc: 469b mov fp, r3
2cde: 3301 adds r3, #1
2ce0: 2704 movs r7, #4
2ce2: 2600 movs r6, #0
2ce4: 9302 str r3, [sp, #8]
2ce6: e74c b.n 2b82 <__aeabi_dmul+0x4a>
2ce8: 2303 movs r3, #3
2cea: 4681 mov r9, r0
2cec: 270c movs r7, #12
2cee: 9302 str r3, [sp, #8]
2cf0: e747 b.n 2b82 <__aeabi_dmul+0x4a>
2cf2: 2280 movs r2, #128 ; 0x80
2cf4: 2300 movs r3, #0
2cf6: 2500 movs r5, #0
2cf8: 0312 lsls r2, r2, #12
2cfa: 4699 mov r9, r3
2cfc: 4c05 ldr r4, [pc, #20] ; (2d14 <__aeabi_dmul+0x1dc>)
2cfe: e782 b.n 2c06 <__aeabi_dmul+0xce>
2d00: 465c mov r4, fp
2d02: 464b mov r3, r9
2d04: 9802 ldr r0, [sp, #8]
2d06: e76f b.n 2be8 <__aeabi_dmul+0xb0>
2d08: 465c mov r4, fp
2d0a: 464b mov r3, r9
2d0c: 9501 str r5, [sp, #4]
2d0e: 9802 ldr r0, [sp, #8]
2d10: e76a b.n 2be8 <__aeabi_dmul+0xb0>
2d12: 46c0 nop ; (mov r8, r8)
2d14: 000007ff .word 0x000007ff
2d18: fffffc01 .word 0xfffffc01
2d1c: 00004948 .word 0x00004948
2d20: 800fffff .word 0x800fffff
2d24: fffffc0d .word 0xfffffc0d
2d28: 464a mov r2, r9
2d2a: 4649 mov r1, r9
2d2c: 0c17 lsrs r7, r2, #16
2d2e: 0c1a lsrs r2, r3, #16
2d30: 041b lsls r3, r3, #16
2d32: 0c1b lsrs r3, r3, #16
2d34: 0408 lsls r0, r1, #16
2d36: 0019 movs r1, r3
2d38: 0c00 lsrs r0, r0, #16
2d3a: 4341 muls r1, r0
2d3c: 0015 movs r5, r2
2d3e: 4688 mov r8, r1
2d40: 0019 movs r1, r3
2d42: 437d muls r5, r7
2d44: 4379 muls r1, r7
2d46: 9503 str r5, [sp, #12]
2d48: 4689 mov r9, r1
2d4a: 0029 movs r1, r5
2d4c: 0015 movs r5, r2
2d4e: 4345 muls r5, r0
2d50: 444d add r5, r9
2d52: 9502 str r5, [sp, #8]
2d54: 4645 mov r5, r8
2d56: 0c2d lsrs r5, r5, #16
2d58: 46aa mov sl, r5
2d5a: 9d02 ldr r5, [sp, #8]
2d5c: 4455 add r5, sl
2d5e: 45a9 cmp r9, r5
2d60: d906 bls.n 2d70 <__aeabi_dmul+0x238>
2d62: 468a mov sl, r1
2d64: 2180 movs r1, #128 ; 0x80
2d66: 0249 lsls r1, r1, #9
2d68: 4689 mov r9, r1
2d6a: 44ca add sl, r9
2d6c: 4651 mov r1, sl
2d6e: 9103 str r1, [sp, #12]
2d70: 0c29 lsrs r1, r5, #16
2d72: 9104 str r1, [sp, #16]
2d74: 4641 mov r1, r8
2d76: 0409 lsls r1, r1, #16
2d78: 042d lsls r5, r5, #16
2d7a: 0c09 lsrs r1, r1, #16
2d7c: 4688 mov r8, r1
2d7e: 0029 movs r1, r5
2d80: 0c25 lsrs r5, r4, #16
2d82: 0424 lsls r4, r4, #16
2d84: 4441 add r1, r8
2d86: 0c24 lsrs r4, r4, #16
2d88: 9105 str r1, [sp, #20]
2d8a: 0021 movs r1, r4
2d8c: 4341 muls r1, r0
2d8e: 4688 mov r8, r1
2d90: 0021 movs r1, r4
2d92: 4379 muls r1, r7
2d94: 468a mov sl, r1
2d96: 4368 muls r0, r5
2d98: 4641 mov r1, r8
2d9a: 4450 add r0, sl
2d9c: 4681 mov r9, r0
2d9e: 0c08 lsrs r0, r1, #16
2da0: 4448 add r0, r9
2da2: 436f muls r7, r5
2da4: 4582 cmp sl, r0
2da6: d903 bls.n 2db0 <__aeabi_dmul+0x278>
2da8: 2180 movs r1, #128 ; 0x80
2daa: 0249 lsls r1, r1, #9
2dac: 4689 mov r9, r1
2dae: 444f add r7, r9
2db0: 0c01 lsrs r1, r0, #16
2db2: 4689 mov r9, r1
2db4: 0039 movs r1, r7
2db6: 4449 add r1, r9
2db8: 9102 str r1, [sp, #8]
2dba: 4641 mov r1, r8
2dbc: 040f lsls r7, r1, #16
2dbe: 9904 ldr r1, [sp, #16]
2dc0: 0c3f lsrs r7, r7, #16
2dc2: 4688 mov r8, r1
2dc4: 0400 lsls r0, r0, #16
2dc6: 19c0 adds r0, r0, r7
2dc8: 4480 add r8, r0
2dca: 4641 mov r1, r8
2dcc: 9104 str r1, [sp, #16]
2dce: 4659 mov r1, fp
2dd0: 0c0f lsrs r7, r1, #16
2dd2: 0409 lsls r1, r1, #16
2dd4: 0c09 lsrs r1, r1, #16
2dd6: 4688 mov r8, r1
2dd8: 4359 muls r1, r3
2dda: 468a mov sl, r1
2ddc: 0039 movs r1, r7
2dde: 4351 muls r1, r2
2de0: 4689 mov r9, r1
2de2: 4641 mov r1, r8
2de4: 434a muls r2, r1
2de6: 4651 mov r1, sl
2de8: 0c09 lsrs r1, r1, #16
2dea: 468b mov fp, r1
2dec: 437b muls r3, r7
2dee: 18d2 adds r2, r2, r3
2df0: 445a add r2, fp
2df2: 4293 cmp r3, r2
2df4: d903 bls.n 2dfe <__aeabi_dmul+0x2c6>
2df6: 2380 movs r3, #128 ; 0x80
2df8: 025b lsls r3, r3, #9
2dfa: 469b mov fp, r3
2dfc: 44d9 add r9, fp
2dfe: 4651 mov r1, sl
2e00: 0409 lsls r1, r1, #16
2e02: 0c09 lsrs r1, r1, #16
2e04: 468a mov sl, r1
2e06: 4641 mov r1, r8
2e08: 4361 muls r1, r4
2e0a: 437c muls r4, r7
2e0c: 0c13 lsrs r3, r2, #16
2e0e: 0412 lsls r2, r2, #16
2e10: 444b add r3, r9
2e12: 4452 add r2, sl
2e14: 46a1 mov r9, r4
2e16: 468a mov sl, r1
2e18: 003c movs r4, r7
2e1a: 4641 mov r1, r8
2e1c: 436c muls r4, r5
2e1e: 434d muls r5, r1
2e20: 4651 mov r1, sl
2e22: 444d add r5, r9
2e24: 0c0f lsrs r7, r1, #16
2e26: 197d adds r5, r7, r5
2e28: 45a9 cmp r9, r5
2e2a: d903 bls.n 2e34 <__aeabi_dmul+0x2fc>
2e2c: 2180 movs r1, #128 ; 0x80
2e2e: 0249 lsls r1, r1, #9
2e30: 4688 mov r8, r1
2e32: 4444 add r4, r8
2e34: 9f04 ldr r7, [sp, #16]
2e36: 9903 ldr r1, [sp, #12]
2e38: 46b8 mov r8, r7
2e3a: 4441 add r1, r8
2e3c: 468b mov fp, r1
2e3e: 4583 cmp fp, r0
2e40: 4180 sbcs r0, r0
2e42: 4241 negs r1, r0
2e44: 4688 mov r8, r1
2e46: 4651 mov r1, sl
2e48: 0408 lsls r0, r1, #16
2e4a: 042f lsls r7, r5, #16
2e4c: 0c00 lsrs r0, r0, #16
2e4e: 183f adds r7, r7, r0
2e50: 4658 mov r0, fp
2e52: 9902 ldr r1, [sp, #8]
2e54: 1810 adds r0, r2, r0
2e56: 4689 mov r9, r1
2e58: 4290 cmp r0, r2
2e5a: 4192 sbcs r2, r2
2e5c: 444f add r7, r9
2e5e: 46ba mov sl, r7
2e60: 4252 negs r2, r2
2e62: 4699 mov r9, r3
2e64: 4693 mov fp, r2
2e66: 44c2 add sl, r8
2e68: 44d1 add r9, sl
2e6a: 44cb add fp, r9
2e6c: 428f cmp r7, r1
2e6e: 41bf sbcs r7, r7
2e70: 45c2 cmp sl, r8
2e72: 4189 sbcs r1, r1
2e74: 4599 cmp r9, r3
2e76: 419b sbcs r3, r3
2e78: 4593 cmp fp, r2
2e7a: 4192 sbcs r2, r2
2e7c: 427f negs r7, r7
2e7e: 4249 negs r1, r1
2e80: 0c2d lsrs r5, r5, #16
2e82: 4252 negs r2, r2
2e84: 430f orrs r7, r1
2e86: 425b negs r3, r3
2e88: 4313 orrs r3, r2
2e8a: 197f adds r7, r7, r5
2e8c: 18ff adds r7, r7, r3
2e8e: 465b mov r3, fp
2e90: 193c adds r4, r7, r4
2e92: 0ddb lsrs r3, r3, #23
2e94: 9a05 ldr r2, [sp, #20]
2e96: 0264 lsls r4, r4, #9
2e98: 431c orrs r4, r3
2e9a: 0243 lsls r3, r0, #9
2e9c: 4313 orrs r3, r2
2e9e: 1e5d subs r5, r3, #1
2ea0: 41ab sbcs r3, r5
2ea2: 465a mov r2, fp
2ea4: 0dc0 lsrs r0, r0, #23
2ea6: 4303 orrs r3, r0
2ea8: 0252 lsls r2, r2, #9
2eaa: 4313 orrs r3, r2
2eac: 01e2 lsls r2, r4, #7
2eae: d556 bpl.n 2f5e <__aeabi_dmul+0x426>
2eb0: 2001 movs r0, #1
2eb2: 085a lsrs r2, r3, #1
2eb4: 4003 ands r3, r0
2eb6: 4313 orrs r3, r2
2eb8: 07e2 lsls r2, r4, #31
2eba: 4313 orrs r3, r2
2ebc: 0864 lsrs r4, r4, #1
2ebe: 485a ldr r0, [pc, #360] ; (3028 <__aeabi_dmul+0x4f0>)
2ec0: 4460 add r0, ip
2ec2: 2800 cmp r0, #0
2ec4: dd4d ble.n 2f62 <__aeabi_dmul+0x42a>
2ec6: 075a lsls r2, r3, #29
2ec8: d009 beq.n 2ede <__aeabi_dmul+0x3a6>
2eca: 220f movs r2, #15
2ecc: 401a ands r2, r3
2ece: 2a04 cmp r2, #4
2ed0: d005 beq.n 2ede <__aeabi_dmul+0x3a6>
2ed2: 1d1a adds r2, r3, #4
2ed4: 429a cmp r2, r3
2ed6: 419b sbcs r3, r3
2ed8: 425b negs r3, r3
2eda: 18e4 adds r4, r4, r3
2edc: 0013 movs r3, r2
2ede: 01e2 lsls r2, r4, #7
2ee0: d504 bpl.n 2eec <__aeabi_dmul+0x3b4>
2ee2: 2080 movs r0, #128 ; 0x80
2ee4: 4a51 ldr r2, [pc, #324] ; (302c <__aeabi_dmul+0x4f4>)
2ee6: 00c0 lsls r0, r0, #3
2ee8: 4014 ands r4, r2
2eea: 4460 add r0, ip
2eec: 4a50 ldr r2, [pc, #320] ; (3030 <__aeabi_dmul+0x4f8>)
2eee: 4290 cmp r0, r2
2ef0: dd00 ble.n 2ef4 <__aeabi_dmul+0x3bc>
2ef2: e6e3 b.n 2cbc <__aeabi_dmul+0x184>
2ef4: 2501 movs r5, #1
2ef6: 08db lsrs r3, r3, #3
2ef8: 0762 lsls r2, r4, #29
2efa: 431a orrs r2, r3
2efc: 0264 lsls r4, r4, #9
2efe: 9b01 ldr r3, [sp, #4]
2f00: 4691 mov r9, r2
2f02: 0b22 lsrs r2, r4, #12
2f04: 0544 lsls r4, r0, #21
2f06: 0d64 lsrs r4, r4, #21
2f08: 401d ands r5, r3
2f0a: e67c b.n 2c06 <__aeabi_dmul+0xce>
2f0c: 2280 movs r2, #128 ; 0x80
2f0e: 4659 mov r1, fp
2f10: 0312 lsls r2, r2, #12
2f12: 4211 tst r1, r2
2f14: d008 beq.n 2f28 <__aeabi_dmul+0x3f0>
2f16: 4214 tst r4, r2
2f18: d106 bne.n 2f28 <__aeabi_dmul+0x3f0>
2f1a: 4322 orrs r2, r4
2f1c: 0312 lsls r2, r2, #12
2f1e: 0b12 lsrs r2, r2, #12
2f20: 4645 mov r5, r8
2f22: 4699 mov r9, r3
2f24: 4c43 ldr r4, [pc, #268] ; (3034 <__aeabi_dmul+0x4fc>)
2f26: e66e b.n 2c06 <__aeabi_dmul+0xce>
2f28: 465b mov r3, fp
2f2a: 431a orrs r2, r3
2f2c: 0312 lsls r2, r2, #12
2f2e: 0b12 lsrs r2, r2, #12
2f30: 4c40 ldr r4, [pc, #256] ; (3034 <__aeabi_dmul+0x4fc>)
2f32: e668 b.n 2c06 <__aeabi_dmul+0xce>
2f34: 0003 movs r3, r0
2f36: 4654 mov r4, sl
2f38: 3b28 subs r3, #40 ; 0x28
2f3a: 409c lsls r4, r3
2f3c: 2300 movs r3, #0
2f3e: e6b9 b.n 2cb4 <__aeabi_dmul+0x17c>
2f40: f000 fbfc bl 373c <__clzsi2>
2f44: 3020 adds r0, #32
2f46: e6a6 b.n 2c96 <__aeabi_dmul+0x15e>
2f48: 0003 movs r3, r0
2f4a: 3b28 subs r3, #40 ; 0x28
2f4c: 409f lsls r7, r3
2f4e: 2300 movs r3, #0
2f50: 46bb mov fp, r7
2f52: 4699 mov r9, r3
2f54: e68a b.n 2c6c <__aeabi_dmul+0x134>
2f56: f000 fbf1 bl 373c <__clzsi2>
2f5a: 3020 adds r0, #32
2f5c: e674 b.n 2c48 <__aeabi_dmul+0x110>
2f5e: 46b4 mov ip, r6
2f60: e7ad b.n 2ebe <__aeabi_dmul+0x386>
2f62: 2501 movs r5, #1
2f64: 1a2a subs r2, r5, r0
2f66: 2a38 cmp r2, #56 ; 0x38
2f68: dd06 ble.n 2f78 <__aeabi_dmul+0x440>
2f6a: 9b01 ldr r3, [sp, #4]
2f6c: 2400 movs r4, #0
2f6e: 401d ands r5, r3
2f70: 2300 movs r3, #0
2f72: 2200 movs r2, #0
2f74: 4699 mov r9, r3
2f76: e646 b.n 2c06 <__aeabi_dmul+0xce>
2f78: 2a1f cmp r2, #31
2f7a: dc21 bgt.n 2fc0 <__aeabi_dmul+0x488>
2f7c: 2520 movs r5, #32
2f7e: 0020 movs r0, r4
2f80: 1aad subs r5, r5, r2
2f82: 001e movs r6, r3
2f84: 40ab lsls r3, r5
2f86: 40a8 lsls r0, r5
2f88: 40d6 lsrs r6, r2
2f8a: 1e5d subs r5, r3, #1
2f8c: 41ab sbcs r3, r5
2f8e: 4330 orrs r0, r6
2f90: 4318 orrs r0, r3
2f92: 40d4 lsrs r4, r2
2f94: 0743 lsls r3, r0, #29
2f96: d009 beq.n 2fac <__aeabi_dmul+0x474>
2f98: 230f movs r3, #15
2f9a: 4003 ands r3, r0
2f9c: 2b04 cmp r3, #4
2f9e: d005 beq.n 2fac <__aeabi_dmul+0x474>
2fa0: 0003 movs r3, r0
2fa2: 1d18 adds r0, r3, #4
2fa4: 4298 cmp r0, r3
2fa6: 419b sbcs r3, r3
2fa8: 425b negs r3, r3
2faa: 18e4 adds r4, r4, r3
2fac: 0223 lsls r3, r4, #8
2fae: d521 bpl.n 2ff4 <__aeabi_dmul+0x4bc>
2fb0: 2501 movs r5, #1
2fb2: 9b01 ldr r3, [sp, #4]
2fb4: 2401 movs r4, #1
2fb6: 401d ands r5, r3
2fb8: 2300 movs r3, #0
2fba: 2200 movs r2, #0
2fbc: 4699 mov r9, r3
2fbe: e622 b.n 2c06 <__aeabi_dmul+0xce>
2fc0: 251f movs r5, #31
2fc2: 0021 movs r1, r4
2fc4: 426d negs r5, r5
2fc6: 1a28 subs r0, r5, r0
2fc8: 40c1 lsrs r1, r0
2fca: 0008 movs r0, r1
2fcc: 2a20 cmp r2, #32
2fce: d01d beq.n 300c <__aeabi_dmul+0x4d4>
2fd0: 355f adds r5, #95 ; 0x5f
2fd2: 1aaa subs r2, r5, r2
2fd4: 4094 lsls r4, r2
2fd6: 4323 orrs r3, r4
2fd8: 1e5c subs r4, r3, #1
2fda: 41a3 sbcs r3, r4
2fdc: 2507 movs r5, #7
2fde: 4303 orrs r3, r0
2fe0: 401d ands r5, r3
2fe2: 2200 movs r2, #0
2fe4: 2d00 cmp r5, #0
2fe6: d009 beq.n 2ffc <__aeabi_dmul+0x4c4>
2fe8: 220f movs r2, #15
2fea: 2400 movs r4, #0
2fec: 401a ands r2, r3
2fee: 0018 movs r0, r3
2ff0: 2a04 cmp r2, #4
2ff2: d1d6 bne.n 2fa2 <__aeabi_dmul+0x46a>
2ff4: 0003 movs r3, r0
2ff6: 0765 lsls r5, r4, #29
2ff8: 0264 lsls r4, r4, #9
2ffa: 0b22 lsrs r2, r4, #12
2ffc: 08db lsrs r3, r3, #3
2ffe: 432b orrs r3, r5
3000: 2501 movs r5, #1
3002: 4699 mov r9, r3
3004: 9b01 ldr r3, [sp, #4]
3006: 2400 movs r4, #0
3008: 401d ands r5, r3
300a: e5fc b.n 2c06 <__aeabi_dmul+0xce>
300c: 2400 movs r4, #0
300e: e7e2 b.n 2fd6 <__aeabi_dmul+0x49e>
3010: 2280 movs r2, #128 ; 0x80
3012: 2501 movs r5, #1
3014: 0312 lsls r2, r2, #12
3016: 4322 orrs r2, r4
3018: 9901 ldr r1, [sp, #4]
301a: 0312 lsls r2, r2, #12
301c: 0b12 lsrs r2, r2, #12
301e: 400d ands r5, r1
3020: 4699 mov r9, r3
3022: 4c04 ldr r4, [pc, #16] ; (3034 <__aeabi_dmul+0x4fc>)
3024: e5ef b.n 2c06 <__aeabi_dmul+0xce>
3026: 46c0 nop ; (mov r8, r8)
3028: 000003ff .word 0x000003ff
302c: feffffff .word 0xfeffffff
3030: 000007fe .word 0x000007fe
3034: 000007ff .word 0x000007ff
00003038 <__aeabi_dsub>:
3038: b5f0 push {r4, r5, r6, r7, lr}
303a: 4646 mov r6, r8
303c: 46d6 mov lr, sl
303e: 464f mov r7, r9
3040: 030c lsls r4, r1, #12
3042: b5c0 push {r6, r7, lr}
3044: 0fcd lsrs r5, r1, #31
3046: 004e lsls r6, r1, #1
3048: 0a61 lsrs r1, r4, #9
304a: 0f44 lsrs r4, r0, #29
304c: 430c orrs r4, r1
304e: 00c1 lsls r1, r0, #3
3050: 0058 lsls r0, r3, #1
3052: 0d40 lsrs r0, r0, #21
3054: 4684 mov ip, r0
3056: 468a mov sl, r1
3058: 000f movs r7, r1
305a: 0319 lsls r1, r3, #12
305c: 0f50 lsrs r0, r2, #29
305e: 0a49 lsrs r1, r1, #9
3060: 4301 orrs r1, r0
3062: 48c6 ldr r0, [pc, #792] ; (337c <__aeabi_dsub+0x344>)
3064: 0d76 lsrs r6, r6, #21
3066: 46a8 mov r8, r5
3068: 0fdb lsrs r3, r3, #31
306a: 00d2 lsls r2, r2, #3
306c: 4584 cmp ip, r0
306e: d100 bne.n 3072 <__aeabi_dsub+0x3a>
3070: e0d8 b.n 3224 <__aeabi_dsub+0x1ec>
3072: 2001 movs r0, #1
3074: 4043 eors r3, r0
3076: 42ab cmp r3, r5
3078: d100 bne.n 307c <__aeabi_dsub+0x44>
307a: e0a6 b.n 31ca <__aeabi_dsub+0x192>
307c: 4660 mov r0, ip
307e: 1a35 subs r5, r6, r0
3080: 2d00 cmp r5, #0
3082: dc00 bgt.n 3086 <__aeabi_dsub+0x4e>
3084: e105 b.n 3292 <__aeabi_dsub+0x25a>
3086: 2800 cmp r0, #0
3088: d110 bne.n 30ac <__aeabi_dsub+0x74>
308a: 000b movs r3, r1
308c: 4313 orrs r3, r2
308e: d100 bne.n 3092 <__aeabi_dsub+0x5a>
3090: e0d7 b.n 3242 <__aeabi_dsub+0x20a>
3092: 1e6b subs r3, r5, #1
3094: 2b00 cmp r3, #0
3096: d000 beq.n 309a <__aeabi_dsub+0x62>
3098: e14b b.n 3332 <__aeabi_dsub+0x2fa>
309a: 4653 mov r3, sl
309c: 1a9f subs r7, r3, r2
309e: 45ba cmp sl, r7
30a0: 4180 sbcs r0, r0
30a2: 1a64 subs r4, r4, r1
30a4: 4240 negs r0, r0
30a6: 1a24 subs r4, r4, r0
30a8: 2601 movs r6, #1
30aa: e01e b.n 30ea <__aeabi_dsub+0xb2>
30ac: 4bb3 ldr r3, [pc, #716] ; (337c <__aeabi_dsub+0x344>)
30ae: 429e cmp r6, r3
30b0: d048 beq.n 3144 <__aeabi_dsub+0x10c>
30b2: 2380 movs r3, #128 ; 0x80
30b4: 041b lsls r3, r3, #16
30b6: 4319 orrs r1, r3
30b8: 2d38 cmp r5, #56 ; 0x38
30ba: dd00 ble.n 30be <__aeabi_dsub+0x86>
30bc: e119 b.n 32f2 <__aeabi_dsub+0x2ba>
30be: 2d1f cmp r5, #31
30c0: dd00 ble.n 30c4 <__aeabi_dsub+0x8c>
30c2: e14c b.n 335e <__aeabi_dsub+0x326>
30c4: 2320 movs r3, #32
30c6: 000f movs r7, r1
30c8: 1b5b subs r3, r3, r5
30ca: 0010 movs r0, r2
30cc: 409a lsls r2, r3
30ce: 409f lsls r7, r3
30d0: 40e8 lsrs r0, r5
30d2: 1e53 subs r3, r2, #1
30d4: 419a sbcs r2, r3
30d6: 40e9 lsrs r1, r5
30d8: 4307 orrs r7, r0
30da: 4317 orrs r7, r2
30dc: 4653 mov r3, sl
30de: 1bdf subs r7, r3, r7
30e0: 1a61 subs r1, r4, r1
30e2: 45ba cmp sl, r7
30e4: 41a4 sbcs r4, r4
30e6: 4264 negs r4, r4
30e8: 1b0c subs r4, r1, r4
30ea: 0223 lsls r3, r4, #8
30ec: d400 bmi.n 30f0 <__aeabi_dsub+0xb8>
30ee: e0c5 b.n 327c <__aeabi_dsub+0x244>
30f0: 0264 lsls r4, r4, #9
30f2: 0a65 lsrs r5, r4, #9
30f4: 2d00 cmp r5, #0
30f6: d100 bne.n 30fa <__aeabi_dsub+0xc2>
30f8: e0f6 b.n 32e8 <__aeabi_dsub+0x2b0>
30fa: 0028 movs r0, r5
30fc: f000 fb1e bl 373c <__clzsi2>
3100: 0003 movs r3, r0
3102: 3b08 subs r3, #8
3104: 2b1f cmp r3, #31
3106: dd00 ble.n 310a <__aeabi_dsub+0xd2>
3108: e0e9 b.n 32de <__aeabi_dsub+0x2a6>
310a: 2220 movs r2, #32
310c: 003c movs r4, r7
310e: 1ad2 subs r2, r2, r3
3110: 409d lsls r5, r3
3112: 40d4 lsrs r4, r2
3114: 409f lsls r7, r3
3116: 4325 orrs r5, r4
3118: 429e cmp r6, r3
311a: dd00 ble.n 311e <__aeabi_dsub+0xe6>
311c: e0db b.n 32d6 <__aeabi_dsub+0x29e>
311e: 1b9e subs r6, r3, r6
3120: 1c73 adds r3, r6, #1
3122: 2b1f cmp r3, #31
3124: dd00 ble.n 3128 <__aeabi_dsub+0xf0>
3126: e10a b.n 333e <__aeabi_dsub+0x306>
3128: 2220 movs r2, #32
312a: 0038 movs r0, r7
312c: 1ad2 subs r2, r2, r3
312e: 0029 movs r1, r5
3130: 4097 lsls r7, r2
3132: 002c movs r4, r5
3134: 4091 lsls r1, r2
3136: 40d8 lsrs r0, r3
3138: 1e7a subs r2, r7, #1
313a: 4197 sbcs r7, r2
313c: 40dc lsrs r4, r3
313e: 2600 movs r6, #0
3140: 4301 orrs r1, r0
3142: 430f orrs r7, r1
3144: 077b lsls r3, r7, #29
3146: d009 beq.n 315c <__aeabi_dsub+0x124>
3148: 230f movs r3, #15
314a: 403b ands r3, r7
314c: 2b04 cmp r3, #4
314e: d005 beq.n 315c <__aeabi_dsub+0x124>
3150: 1d3b adds r3, r7, #4
3152: 42bb cmp r3, r7
3154: 41bf sbcs r7, r7
3156: 427f negs r7, r7
3158: 19e4 adds r4, r4, r7
315a: 001f movs r7, r3
315c: 0223 lsls r3, r4, #8
315e: d525 bpl.n 31ac <__aeabi_dsub+0x174>
3160: 4b86 ldr r3, [pc, #536] ; (337c <__aeabi_dsub+0x344>)
3162: 3601 adds r6, #1
3164: 429e cmp r6, r3
3166: d100 bne.n 316a <__aeabi_dsub+0x132>
3168: e0af b.n 32ca <__aeabi_dsub+0x292>
316a: 4b85 ldr r3, [pc, #532] ; (3380 <__aeabi_dsub+0x348>)
316c: 2501 movs r5, #1
316e: 401c ands r4, r3
3170: 4643 mov r3, r8
3172: 0762 lsls r2, r4, #29
3174: 08ff lsrs r7, r7, #3
3176: 0264 lsls r4, r4, #9
3178: 0576 lsls r6, r6, #21
317a: 4317 orrs r7, r2
317c: 0b24 lsrs r4, r4, #12
317e: 0d76 lsrs r6, r6, #21
3180: 401d ands r5, r3
3182: 2100 movs r1, #0
3184: 0324 lsls r4, r4, #12
3186: 0b23 lsrs r3, r4, #12
3188: 0d0c lsrs r4, r1, #20
318a: 4a7e ldr r2, [pc, #504] ; (3384 <__aeabi_dsub+0x34c>)
318c: 0524 lsls r4, r4, #20
318e: 431c orrs r4, r3
3190: 4014 ands r4, r2
3192: 0533 lsls r3, r6, #20
3194: 4323 orrs r3, r4
3196: 005b lsls r3, r3, #1
3198: 07ed lsls r5, r5, #31
319a: 085b lsrs r3, r3, #1
319c: 432b orrs r3, r5
319e: 0038 movs r0, r7
31a0: 0019 movs r1, r3
31a2: bc1c pop {r2, r3, r4}
31a4: 4690 mov r8, r2
31a6: 4699 mov r9, r3
31a8: 46a2 mov sl, r4
31aa: bdf0 pop {r4, r5, r6, r7, pc}
31ac: 2501 movs r5, #1
31ae: 4643 mov r3, r8
31b0: 0762 lsls r2, r4, #29
31b2: 08ff lsrs r7, r7, #3
31b4: 4317 orrs r7, r2
31b6: 08e4 lsrs r4, r4, #3
31b8: 401d ands r5, r3
31ba: 4b70 ldr r3, [pc, #448] ; (337c <__aeabi_dsub+0x344>)
31bc: 429e cmp r6, r3
31be: d036 beq.n 322e <__aeabi_dsub+0x1f6>
31c0: 0324 lsls r4, r4, #12
31c2: 0576 lsls r6, r6, #21
31c4: 0b24 lsrs r4, r4, #12
31c6: 0d76 lsrs r6, r6, #21
31c8: e7db b.n 3182 <__aeabi_dsub+0x14a>
31ca: 4663 mov r3, ip
31cc: 1af3 subs r3, r6, r3
31ce: 2b00 cmp r3, #0
31d0: dc00 bgt.n 31d4 <__aeabi_dsub+0x19c>
31d2: e094 b.n 32fe <__aeabi_dsub+0x2c6>
31d4: 4660 mov r0, ip
31d6: 2800 cmp r0, #0
31d8: d035 beq.n 3246 <__aeabi_dsub+0x20e>
31da: 4868 ldr r0, [pc, #416] ; (337c <__aeabi_dsub+0x344>)
31dc: 4286 cmp r6, r0
31de: d0b1 beq.n 3144 <__aeabi_dsub+0x10c>
31e0: 2780 movs r7, #128 ; 0x80
31e2: 043f lsls r7, r7, #16
31e4: 4339 orrs r1, r7
31e6: 2b38 cmp r3, #56 ; 0x38
31e8: dc00 bgt.n 31ec <__aeabi_dsub+0x1b4>
31ea: e0fd b.n 33e8 <__aeabi_dsub+0x3b0>
31ec: 430a orrs r2, r1
31ee: 0017 movs r7, r2
31f0: 2100 movs r1, #0
31f2: 1e7a subs r2, r7, #1
31f4: 4197 sbcs r7, r2
31f6: 4457 add r7, sl
31f8: 4557 cmp r7, sl
31fa: 4180 sbcs r0, r0
31fc: 1909 adds r1, r1, r4
31fe: 4244 negs r4, r0
3200: 190c adds r4, r1, r4
3202: 0223 lsls r3, r4, #8
3204: d53a bpl.n 327c <__aeabi_dsub+0x244>
3206: 4b5d ldr r3, [pc, #372] ; (337c <__aeabi_dsub+0x344>)
3208: 3601 adds r6, #1
320a: 429e cmp r6, r3
320c: d100 bne.n 3210 <__aeabi_dsub+0x1d8>
320e: e14b b.n 34a8 <__aeabi_dsub+0x470>
3210: 2201 movs r2, #1
3212: 4b5b ldr r3, [pc, #364] ; (3380 <__aeabi_dsub+0x348>)
3214: 401c ands r4, r3
3216: 087b lsrs r3, r7, #1
3218: 4017 ands r7, r2
321a: 431f orrs r7, r3
321c: 07e2 lsls r2, r4, #31
321e: 4317 orrs r7, r2
3220: 0864 lsrs r4, r4, #1
3222: e78f b.n 3144 <__aeabi_dsub+0x10c>
3224: 0008 movs r0, r1
3226: 4310 orrs r0, r2
3228: d000 beq.n 322c <__aeabi_dsub+0x1f4>
322a: e724 b.n 3076 <__aeabi_dsub+0x3e>
322c: e721 b.n 3072 <__aeabi_dsub+0x3a>
322e: 0023 movs r3, r4
3230: 433b orrs r3, r7
3232: d100 bne.n 3236 <__aeabi_dsub+0x1fe>
3234: e1b9 b.n 35aa <__aeabi_dsub+0x572>
3236: 2280 movs r2, #128 ; 0x80
3238: 0312 lsls r2, r2, #12
323a: 4314 orrs r4, r2
323c: 0324 lsls r4, r4, #12
323e: 0b24 lsrs r4, r4, #12
3240: e79f b.n 3182 <__aeabi_dsub+0x14a>
3242: 002e movs r6, r5
3244: e77e b.n 3144 <__aeabi_dsub+0x10c>
3246: 0008 movs r0, r1
3248: 4310 orrs r0, r2
324a: d100 bne.n 324e <__aeabi_dsub+0x216>
324c: e0ca b.n 33e4 <__aeabi_dsub+0x3ac>
324e: 1e58 subs r0, r3, #1
3250: 4684 mov ip, r0
3252: 2800 cmp r0, #0
3254: d000 beq.n 3258 <__aeabi_dsub+0x220>
3256: e0e7 b.n 3428 <__aeabi_dsub+0x3f0>
3258: 4452 add r2, sl
325a: 4552 cmp r2, sl
325c: 4180 sbcs r0, r0
325e: 1864 adds r4, r4, r1
3260: 4240 negs r0, r0
3262: 1824 adds r4, r4, r0
3264: 0017 movs r7, r2
3266: 2601 movs r6, #1
3268: 0223 lsls r3, r4, #8
326a: d507 bpl.n 327c <__aeabi_dsub+0x244>
326c: 2602 movs r6, #2
326e: e7cf b.n 3210 <__aeabi_dsub+0x1d8>
3270: 4664 mov r4, ip
3272: 432c orrs r4, r5
3274: d100 bne.n 3278 <__aeabi_dsub+0x240>
3276: e1b3 b.n 35e0 <__aeabi_dsub+0x5a8>
3278: 002c movs r4, r5
327a: 4667 mov r7, ip
327c: 077b lsls r3, r7, #29
327e: d000 beq.n 3282 <__aeabi_dsub+0x24a>
3280: e762 b.n 3148 <__aeabi_dsub+0x110>
3282: 0763 lsls r3, r4, #29
3284: 08ff lsrs r7, r7, #3
3286: 431f orrs r7, r3
3288: 2501 movs r5, #1
328a: 4643 mov r3, r8
328c: 08e4 lsrs r4, r4, #3
328e: 401d ands r5, r3
3290: e793 b.n 31ba <__aeabi_dsub+0x182>
3292: 2d00 cmp r5, #0
3294: d178 bne.n 3388 <__aeabi_dsub+0x350>
3296: 1c75 adds r5, r6, #1
3298: 056d lsls r5, r5, #21
329a: 0d6d lsrs r5, r5, #21
329c: 2d01 cmp r5, #1
329e: dc00 bgt.n 32a2 <__aeabi_dsub+0x26a>
32a0: e0f2 b.n 3488 <__aeabi_dsub+0x450>
32a2: 4650 mov r0, sl
32a4: 1a80 subs r0, r0, r2
32a6: 4582 cmp sl, r0
32a8: 41bf sbcs r7, r7
32aa: 1a65 subs r5, r4, r1
32ac: 427f negs r7, r7
32ae: 1bed subs r5, r5, r7
32b0: 4684 mov ip, r0
32b2: 0228 lsls r0, r5, #8
32b4: d400 bmi.n 32b8 <__aeabi_dsub+0x280>
32b6: e08c b.n 33d2 <__aeabi_dsub+0x39a>
32b8: 4650 mov r0, sl
32ba: 1a17 subs r7, r2, r0
32bc: 42ba cmp r2, r7
32be: 4192 sbcs r2, r2
32c0: 1b0c subs r4, r1, r4
32c2: 4255 negs r5, r2
32c4: 1b65 subs r5, r4, r5
32c6: 4698 mov r8, r3
32c8: e714 b.n 30f4 <__aeabi_dsub+0xbc>
32ca: 2501 movs r5, #1
32cc: 4643 mov r3, r8
32ce: 2400 movs r4, #0
32d0: 401d ands r5, r3
32d2: 2700 movs r7, #0
32d4: e755 b.n 3182 <__aeabi_dsub+0x14a>
32d6: 4c2a ldr r4, [pc, #168] ; (3380 <__aeabi_dsub+0x348>)
32d8: 1af6 subs r6, r6, r3
32da: 402c ands r4, r5
32dc: e732 b.n 3144 <__aeabi_dsub+0x10c>
32de: 003d movs r5, r7
32e0: 3828 subs r0, #40 ; 0x28
32e2: 4085 lsls r5, r0
32e4: 2700 movs r7, #0
32e6: e717 b.n 3118 <__aeabi_dsub+0xe0>
32e8: 0038 movs r0, r7
32ea: f000 fa27 bl 373c <__clzsi2>
32ee: 3020 adds r0, #32
32f0: e706 b.n 3100 <__aeabi_dsub+0xc8>
32f2: 430a orrs r2, r1
32f4: 0017 movs r7, r2
32f6: 2100 movs r1, #0
32f8: 1e7a subs r2, r7, #1
32fa: 4197 sbcs r7, r2
32fc: e6ee b.n 30dc <__aeabi_dsub+0xa4>
32fe: 2b00 cmp r3, #0
3300: d000 beq.n 3304 <__aeabi_dsub+0x2cc>
3302: e0e5 b.n 34d0 <__aeabi_dsub+0x498>
3304: 1c73 adds r3, r6, #1
3306: 469c mov ip, r3
3308: 055b lsls r3, r3, #21
330a: 0d5b lsrs r3, r3, #21
330c: 2b01 cmp r3, #1
330e: dc00 bgt.n 3312 <__aeabi_dsub+0x2da>
3310: e09f b.n 3452 <__aeabi_dsub+0x41a>
3312: 4b1a ldr r3, [pc, #104] ; (337c <__aeabi_dsub+0x344>)
3314: 459c cmp ip, r3
3316: d100 bne.n 331a <__aeabi_dsub+0x2e2>
3318: e0c5 b.n 34a6 <__aeabi_dsub+0x46e>
331a: 4452 add r2, sl
331c: 4552 cmp r2, sl
331e: 4180 sbcs r0, r0
3320: 1864 adds r4, r4, r1
3322: 4240 negs r0, r0
3324: 1824 adds r4, r4, r0
3326: 07e7 lsls r7, r4, #31
3328: 0852 lsrs r2, r2, #1
332a: 4317 orrs r7, r2
332c: 0864 lsrs r4, r4, #1
332e: 4666 mov r6, ip
3330: e708 b.n 3144 <__aeabi_dsub+0x10c>
3332: 4812 ldr r0, [pc, #72] ; (337c <__aeabi_dsub+0x344>)
3334: 4285 cmp r5, r0
3336: d100 bne.n 333a <__aeabi_dsub+0x302>
3338: e085 b.n 3446 <__aeabi_dsub+0x40e>
333a: 001d movs r5, r3
333c: e6bc b.n 30b8 <__aeabi_dsub+0x80>
333e: 0029 movs r1, r5
3340: 3e1f subs r6, #31
3342: 40f1 lsrs r1, r6
3344: 2b20 cmp r3, #32
3346: d100 bne.n 334a <__aeabi_dsub+0x312>
3348: e07f b.n 344a <__aeabi_dsub+0x412>
334a: 2240 movs r2, #64 ; 0x40
334c: 1ad3 subs r3, r2, r3
334e: 409d lsls r5, r3
3350: 432f orrs r7, r5
3352: 1e7d subs r5, r7, #1
3354: 41af sbcs r7, r5
3356: 2400 movs r4, #0
3358: 430f orrs r7, r1
335a: 2600 movs r6, #0
335c: e78e b.n 327c <__aeabi_dsub+0x244>
335e: 002b movs r3, r5
3360: 000f movs r7, r1
3362: 3b20 subs r3, #32
3364: 40df lsrs r7, r3
3366: 2d20 cmp r5, #32
3368: d071 beq.n 344e <__aeabi_dsub+0x416>
336a: 2340 movs r3, #64 ; 0x40
336c: 1b5d subs r5, r3, r5
336e: 40a9 lsls r1, r5
3370: 430a orrs r2, r1
3372: 1e51 subs r1, r2, #1
3374: 418a sbcs r2, r1
3376: 2100 movs r1, #0
3378: 4317 orrs r7, r2
337a: e6af b.n 30dc <__aeabi_dsub+0xa4>
337c: 000007ff .word 0x000007ff
3380: ff7fffff .word 0xff7fffff
3384: 800fffff .word 0x800fffff
3388: 2e00 cmp r6, #0
338a: d03e beq.n 340a <__aeabi_dsub+0x3d2>
338c: 4eb3 ldr r6, [pc, #716] ; (365c <__aeabi_dsub+0x624>)
338e: 45b4 cmp ip, r6
3390: d045 beq.n 341e <__aeabi_dsub+0x3e6>
3392: 2680 movs r6, #128 ; 0x80
3394: 0436 lsls r6, r6, #16
3396: 426d negs r5, r5
3398: 4334 orrs r4, r6
339a: 2d38 cmp r5, #56 ; 0x38
339c: dd00 ble.n 33a0 <__aeabi_dsub+0x368>
339e: e0a8 b.n 34f2 <__aeabi_dsub+0x4ba>
33a0: 2d1f cmp r5, #31
33a2: dd00 ble.n 33a6 <__aeabi_dsub+0x36e>
33a4: e11f b.n 35e6 <__aeabi_dsub+0x5ae>
33a6: 2620 movs r6, #32
33a8: 0027 movs r7, r4
33aa: 4650 mov r0, sl
33ac: 1b76 subs r6, r6, r5
33ae: 40b7 lsls r7, r6
33b0: 40e8 lsrs r0, r5
33b2: 4307 orrs r7, r0
33b4: 4650 mov r0, sl
33b6: 40b0 lsls r0, r6
33b8: 1e46 subs r6, r0, #1
33ba: 41b0 sbcs r0, r6
33bc: 40ec lsrs r4, r5
33be: 4338 orrs r0, r7
33c0: 1a17 subs r7, r2, r0
33c2: 42ba cmp r2, r7
33c4: 4192 sbcs r2, r2
33c6: 1b0c subs r4, r1, r4
33c8: 4252 negs r2, r2
33ca: 1aa4 subs r4, r4, r2
33cc: 4666 mov r6, ip
33ce: 4698 mov r8, r3
33d0: e68b b.n 30ea <__aeabi_dsub+0xb2>
33d2: 4664 mov r4, ip
33d4: 4667 mov r7, ip
33d6: 432c orrs r4, r5
33d8: d000 beq.n 33dc <__aeabi_dsub+0x3a4>
33da: e68b b.n 30f4 <__aeabi_dsub+0xbc>
33dc: 2500 movs r5, #0
33de: 2600 movs r6, #0
33e0: 2700 movs r7, #0
33e2: e6ea b.n 31ba <__aeabi_dsub+0x182>
33e4: 001e movs r6, r3
33e6: e6ad b.n 3144 <__aeabi_dsub+0x10c>
33e8: 2b1f cmp r3, #31
33ea: dc60 bgt.n 34ae <__aeabi_dsub+0x476>
33ec: 2720 movs r7, #32
33ee: 1af8 subs r0, r7, r3
33f0: 000f movs r7, r1
33f2: 4684 mov ip, r0
33f4: 4087 lsls r7, r0
33f6: 0010 movs r0, r2
33f8: 40d8 lsrs r0, r3
33fa: 4307 orrs r7, r0
33fc: 4660 mov r0, ip
33fe: 4082 lsls r2, r0
3400: 1e50 subs r0, r2, #1
3402: 4182 sbcs r2, r0
3404: 40d9 lsrs r1, r3
3406: 4317 orrs r7, r2
3408: e6f5 b.n 31f6 <__aeabi_dsub+0x1be>
340a: 0026 movs r6, r4
340c: 4650 mov r0, sl
340e: 4306 orrs r6, r0
3410: d005 beq.n 341e <__aeabi_dsub+0x3e6>
3412: 43ed mvns r5, r5
3414: 2d00 cmp r5, #0
3416: d0d3 beq.n 33c0 <__aeabi_dsub+0x388>
3418: 4e90 ldr r6, [pc, #576] ; (365c <__aeabi_dsub+0x624>)
341a: 45b4 cmp ip, r6
341c: d1bd bne.n 339a <__aeabi_dsub+0x362>
341e: 000c movs r4, r1
3420: 0017 movs r7, r2
3422: 4666 mov r6, ip
3424: 4698 mov r8, r3
3426: e68d b.n 3144 <__aeabi_dsub+0x10c>
3428: 488c ldr r0, [pc, #560] ; (365c <__aeabi_dsub+0x624>)
342a: 4283 cmp r3, r0
342c: d00b beq.n 3446 <__aeabi_dsub+0x40e>
342e: 4663 mov r3, ip
3430: e6d9 b.n 31e6 <__aeabi_dsub+0x1ae>
3432: 2d00 cmp r5, #0
3434: d000 beq.n 3438 <__aeabi_dsub+0x400>
3436: e096 b.n 3566 <__aeabi_dsub+0x52e>
3438: 0008 movs r0, r1
343a: 4310 orrs r0, r2
343c: d100 bne.n 3440 <__aeabi_dsub+0x408>
343e: e0e2 b.n 3606 <__aeabi_dsub+0x5ce>
3440: 000c movs r4, r1
3442: 0017 movs r7, r2
3444: 4698 mov r8, r3
3446: 4e85 ldr r6, [pc, #532] ; (365c <__aeabi_dsub+0x624>)
3448: e67c b.n 3144 <__aeabi_dsub+0x10c>
344a: 2500 movs r5, #0
344c: e780 b.n 3350 <__aeabi_dsub+0x318>
344e: 2100 movs r1, #0
3450: e78e b.n 3370 <__aeabi_dsub+0x338>
3452: 0023 movs r3, r4
3454: 4650 mov r0, sl
3456: 4303 orrs r3, r0
3458: 2e00 cmp r6, #0
345a: d000 beq.n 345e <__aeabi_dsub+0x426>
345c: e0a8 b.n 35b0 <__aeabi_dsub+0x578>
345e: 2b00 cmp r3, #0
3460: d100 bne.n 3464 <__aeabi_dsub+0x42c>
3462: e0de b.n 3622 <__aeabi_dsub+0x5ea>
3464: 000b movs r3, r1
3466: 4313 orrs r3, r2
3468: d100 bne.n 346c <__aeabi_dsub+0x434>
346a: e66b b.n 3144 <__aeabi_dsub+0x10c>
346c: 4452 add r2, sl
346e: 4552 cmp r2, sl
3470: 4180 sbcs r0, r0
3472: 1864 adds r4, r4, r1
3474: 4240 negs r0, r0
3476: 1824 adds r4, r4, r0
3478: 0017 movs r7, r2
347a: 0223 lsls r3, r4, #8
347c: d400 bmi.n 3480 <__aeabi_dsub+0x448>
347e: e6fd b.n 327c <__aeabi_dsub+0x244>
3480: 4b77 ldr r3, [pc, #476] ; (3660 <__aeabi_dsub+0x628>)
3482: 4666 mov r6, ip
3484: 401c ands r4, r3
3486: e65d b.n 3144 <__aeabi_dsub+0x10c>
3488: 0025 movs r5, r4
348a: 4650 mov r0, sl
348c: 4305 orrs r5, r0
348e: 2e00 cmp r6, #0
3490: d1cf bne.n 3432 <__aeabi_dsub+0x3fa>
3492: 2d00 cmp r5, #0
3494: d14f bne.n 3536 <__aeabi_dsub+0x4fe>
3496: 000c movs r4, r1
3498: 4314 orrs r4, r2
349a: d100 bne.n 349e <__aeabi_dsub+0x466>
349c: e0a0 b.n 35e0 <__aeabi_dsub+0x5a8>
349e: 000c movs r4, r1
34a0: 0017 movs r7, r2
34a2: 4698 mov r8, r3
34a4: e64e b.n 3144 <__aeabi_dsub+0x10c>
34a6: 4666 mov r6, ip
34a8: 2400 movs r4, #0
34aa: 2700 movs r7, #0
34ac: e685 b.n 31ba <__aeabi_dsub+0x182>
34ae: 001f movs r7, r3
34b0: 0008 movs r0, r1
34b2: 3f20 subs r7, #32
34b4: 40f8 lsrs r0, r7
34b6: 0007 movs r7, r0
34b8: 2b20 cmp r3, #32
34ba: d100 bne.n 34be <__aeabi_dsub+0x486>
34bc: e08e b.n 35dc <__aeabi_dsub+0x5a4>
34be: 2040 movs r0, #64 ; 0x40
34c0: 1ac3 subs r3, r0, r3
34c2: 4099 lsls r1, r3
34c4: 430a orrs r2, r1
34c6: 1e51 subs r1, r2, #1
34c8: 418a sbcs r2, r1
34ca: 2100 movs r1, #0
34cc: 4317 orrs r7, r2
34ce: e692 b.n 31f6 <__aeabi_dsub+0x1be>
34d0: 2e00 cmp r6, #0
34d2: d114 bne.n 34fe <__aeabi_dsub+0x4c6>
34d4: 0026 movs r6, r4
34d6: 4650 mov r0, sl
34d8: 4306 orrs r6, r0
34da: d062 beq.n 35a2 <__aeabi_dsub+0x56a>
34dc: 43db mvns r3, r3
34de: 2b00 cmp r3, #0
34e0: d15c bne.n 359c <__aeabi_dsub+0x564>
34e2: 1887 adds r7, r0, r2
34e4: 4297 cmp r7, r2
34e6: 4192 sbcs r2, r2
34e8: 1864 adds r4, r4, r1
34ea: 4252 negs r2, r2
34ec: 18a4 adds r4, r4, r2
34ee: 4666 mov r6, ip
34f0: e687 b.n 3202 <__aeabi_dsub+0x1ca>
34f2: 4650 mov r0, sl
34f4: 4320 orrs r0, r4
34f6: 1e44 subs r4, r0, #1
34f8: 41a0 sbcs r0, r4
34fa: 2400 movs r4, #0
34fc: e760 b.n 33c0 <__aeabi_dsub+0x388>
34fe: 4e57 ldr r6, [pc, #348] ; (365c <__aeabi_dsub+0x624>)
3500: 45b4 cmp ip, r6
3502: d04e beq.n 35a2 <__aeabi_dsub+0x56a>
3504: 2680 movs r6, #128 ; 0x80
3506: 0436 lsls r6, r6, #16
3508: 425b negs r3, r3
350a: 4334 orrs r4, r6
350c: 2b38 cmp r3, #56 ; 0x38
350e: dd00 ble.n 3512 <__aeabi_dsub+0x4da>
3510: e07f b.n 3612 <__aeabi_dsub+0x5da>
3512: 2b1f cmp r3, #31
3514: dd00 ble.n 3518 <__aeabi_dsub+0x4e0>
3516: e08b b.n 3630 <__aeabi_dsub+0x5f8>
3518: 2620 movs r6, #32
351a: 0027 movs r7, r4
351c: 4650 mov r0, sl
351e: 1af6 subs r6, r6, r3
3520: 40b7 lsls r7, r6
3522: 40d8 lsrs r0, r3
3524: 4307 orrs r7, r0
3526: 4650 mov r0, sl
3528: 40b0 lsls r0, r6
352a: 1e46 subs r6, r0, #1
352c: 41b0 sbcs r0, r6
352e: 4307 orrs r7, r0
3530: 40dc lsrs r4, r3
3532: 18bf adds r7, r7, r2
3534: e7d6 b.n 34e4 <__aeabi_dsub+0x4ac>
3536: 000d movs r5, r1
3538: 4315 orrs r5, r2
353a: d100 bne.n 353e <__aeabi_dsub+0x506>
353c: e602 b.n 3144 <__aeabi_dsub+0x10c>
353e: 4650 mov r0, sl
3540: 1a80 subs r0, r0, r2
3542: 4582 cmp sl, r0
3544: 41bf sbcs r7, r7
3546: 1a65 subs r5, r4, r1
3548: 427f negs r7, r7
354a: 1bed subs r5, r5, r7
354c: 4684 mov ip, r0
354e: 0228 lsls r0, r5, #8
3550: d400 bmi.n 3554 <__aeabi_dsub+0x51c>
3552: e68d b.n 3270 <__aeabi_dsub+0x238>
3554: 4650 mov r0, sl
3556: 1a17 subs r7, r2, r0
3558: 42ba cmp r2, r7
355a: 4192 sbcs r2, r2
355c: 1b0c subs r4, r1, r4
355e: 4252 negs r2, r2
3560: 1aa4 subs r4, r4, r2
3562: 4698 mov r8, r3
3564: e5ee b.n 3144 <__aeabi_dsub+0x10c>
3566: 000d movs r5, r1
3568: 4315 orrs r5, r2
356a: d100 bne.n 356e <__aeabi_dsub+0x536>
356c: e76b b.n 3446 <__aeabi_dsub+0x40e>
356e: 4650 mov r0, sl
3570: 0767 lsls r7, r4, #29
3572: 08c0 lsrs r0, r0, #3
3574: 4307 orrs r7, r0
3576: 2080 movs r0, #128 ; 0x80
3578: 08e4 lsrs r4, r4, #3
357a: 0300 lsls r0, r0, #12
357c: 4204 tst r4, r0
357e: d007 beq.n 3590 <__aeabi_dsub+0x558>
3580: 08cd lsrs r5, r1, #3
3582: 4205 tst r5, r0
3584: d104 bne.n 3590 <__aeabi_dsub+0x558>
3586: 002c movs r4, r5
3588: 4698 mov r8, r3
358a: 08d7 lsrs r7, r2, #3
358c: 0749 lsls r1, r1, #29
358e: 430f orrs r7, r1
3590: 0f7b lsrs r3, r7, #29
3592: 00e4 lsls r4, r4, #3
3594: 431c orrs r4, r3
3596: 00ff lsls r7, r7, #3
3598: 4e30 ldr r6, [pc, #192] ; (365c <__aeabi_dsub+0x624>)
359a: e5d3 b.n 3144 <__aeabi_dsub+0x10c>
359c: 4e2f ldr r6, [pc, #188] ; (365c <__aeabi_dsub+0x624>)
359e: 45b4 cmp ip, r6
35a0: d1b4 bne.n 350c <__aeabi_dsub+0x4d4>
35a2: 000c movs r4, r1
35a4: 0017 movs r7, r2
35a6: 4666 mov r6, ip
35a8: e5cc b.n 3144 <__aeabi_dsub+0x10c>
35aa: 2700 movs r7, #0
35ac: 2400 movs r4, #0
35ae: e5e8 b.n 3182 <__aeabi_dsub+0x14a>
35b0: 2b00 cmp r3, #0
35b2: d039 beq.n 3628 <__aeabi_dsub+0x5f0>
35b4: 000b movs r3, r1
35b6: 4313 orrs r3, r2
35b8: d100 bne.n 35bc <__aeabi_dsub+0x584>
35ba: e744 b.n 3446 <__aeabi_dsub+0x40e>
35bc: 08c0 lsrs r0, r0, #3
35be: 0767 lsls r7, r4, #29
35c0: 4307 orrs r7, r0
35c2: 2080 movs r0, #128 ; 0x80
35c4: 08e4 lsrs r4, r4, #3
35c6: 0300 lsls r0, r0, #12
35c8: 4204 tst r4, r0
35ca: d0e1 beq.n 3590 <__aeabi_dsub+0x558>
35cc: 08cb lsrs r3, r1, #3
35ce: 4203 tst r3, r0
35d0: d1de bne.n 3590 <__aeabi_dsub+0x558>
35d2: 08d7 lsrs r7, r2, #3
35d4: 0749 lsls r1, r1, #29
35d6: 430f orrs r7, r1
35d8: 001c movs r4, r3
35da: e7d9 b.n 3590 <__aeabi_dsub+0x558>
35dc: 2100 movs r1, #0
35de: e771 b.n 34c4 <__aeabi_dsub+0x48c>
35e0: 2500 movs r5, #0
35e2: 2700 movs r7, #0
35e4: e5e9 b.n 31ba <__aeabi_dsub+0x182>
35e6: 002e movs r6, r5
35e8: 0027 movs r7, r4
35ea: 3e20 subs r6, #32
35ec: 40f7 lsrs r7, r6
35ee: 2d20 cmp r5, #32
35f0: d02f beq.n 3652 <__aeabi_dsub+0x61a>
35f2: 2640 movs r6, #64 ; 0x40
35f4: 1b75 subs r5, r6, r5
35f6: 40ac lsls r4, r5
35f8: 4650 mov r0, sl
35fa: 4320 orrs r0, r4
35fc: 1e44 subs r4, r0, #1
35fe: 41a0 sbcs r0, r4
3600: 2400 movs r4, #0
3602: 4338 orrs r0, r7
3604: e6dc b.n 33c0 <__aeabi_dsub+0x388>
3606: 2480 movs r4, #128 ; 0x80
3608: 2500 movs r5, #0
360a: 0324 lsls r4, r4, #12
360c: 4e13 ldr r6, [pc, #76] ; (365c <__aeabi_dsub+0x624>)
360e: 2700 movs r7, #0
3610: e5d3 b.n 31ba <__aeabi_dsub+0x182>
3612: 4650 mov r0, sl
3614: 4320 orrs r0, r4
3616: 0007 movs r7, r0
3618: 1e78 subs r0, r7, #1
361a: 4187 sbcs r7, r0
361c: 2400 movs r4, #0
361e: 18bf adds r7, r7, r2
3620: e760 b.n 34e4 <__aeabi_dsub+0x4ac>
3622: 000c movs r4, r1
3624: 0017 movs r7, r2
3626: e58d b.n 3144 <__aeabi_dsub+0x10c>
3628: 000c movs r4, r1
362a: 0017 movs r7, r2
362c: 4e0b ldr r6, [pc, #44] ; (365c <__aeabi_dsub+0x624>)
362e: e589 b.n 3144 <__aeabi_dsub+0x10c>
3630: 001e movs r6, r3
3632: 0027 movs r7, r4
3634: 3e20 subs r6, #32
3636: 40f7 lsrs r7, r6
3638: 2b20 cmp r3, #32
363a: d00c beq.n 3656 <__aeabi_dsub+0x61e>
363c: 2640 movs r6, #64 ; 0x40
363e: 1af3 subs r3, r6, r3
3640: 409c lsls r4, r3
3642: 4650 mov r0, sl
3644: 4320 orrs r0, r4
3646: 1e44 subs r4, r0, #1
3648: 41a0 sbcs r0, r4
364a: 4307 orrs r7, r0
364c: 2400 movs r4, #0
364e: 18bf adds r7, r7, r2
3650: e748 b.n 34e4 <__aeabi_dsub+0x4ac>
3652: 2400 movs r4, #0
3654: e7d0 b.n 35f8 <__aeabi_dsub+0x5c0>
3656: 2400 movs r4, #0
3658: e7f3 b.n 3642 <__aeabi_dsub+0x60a>
365a: 46c0 nop ; (mov r8, r8)
365c: 000007ff .word 0x000007ff
3660: ff7fffff .word 0xff7fffff
00003664 <__aeabi_d2iz>:
3664: b530 push {r4, r5, lr}
3666: 4d13 ldr r5, [pc, #76] ; (36b4 <__aeabi_d2iz+0x50>)
3668: 030a lsls r2, r1, #12
366a: 004b lsls r3, r1, #1
366c: 0b12 lsrs r2, r2, #12
366e: 0d5b lsrs r3, r3, #21
3670: 0fc9 lsrs r1, r1, #31
3672: 2400 movs r4, #0
3674: 42ab cmp r3, r5
3676: dd10 ble.n 369a <__aeabi_d2iz+0x36>
3678: 4c0f ldr r4, [pc, #60] ; (36b8 <__aeabi_d2iz+0x54>)
367a: 42a3 cmp r3, r4
367c: dc0f bgt.n 369e <__aeabi_d2iz+0x3a>
367e: 2480 movs r4, #128 ; 0x80
3680: 4d0e ldr r5, [pc, #56] ; (36bc <__aeabi_d2iz+0x58>)
3682: 0364 lsls r4, r4, #13
3684: 4322 orrs r2, r4
3686: 1aed subs r5, r5, r3
3688: 2d1f cmp r5, #31
368a: dd0b ble.n 36a4 <__aeabi_d2iz+0x40>
368c: 480c ldr r0, [pc, #48] ; (36c0 <__aeabi_d2iz+0x5c>)
368e: 1ac3 subs r3, r0, r3
3690: 40da lsrs r2, r3
3692: 4254 negs r4, r2
3694: 2900 cmp r1, #0
3696: d100 bne.n 369a <__aeabi_d2iz+0x36>
3698: 0014 movs r4, r2
369a: 0020 movs r0, r4
369c: bd30 pop {r4, r5, pc}
369e: 4b09 ldr r3, [pc, #36] ; (36c4 <__aeabi_d2iz+0x60>)
36a0: 18cc adds r4, r1, r3
36a2: e7fa b.n 369a <__aeabi_d2iz+0x36>
36a4: 4c08 ldr r4, [pc, #32] ; (36c8 <__aeabi_d2iz+0x64>)
36a6: 40e8 lsrs r0, r5
36a8: 46a4 mov ip, r4
36aa: 4463 add r3, ip
36ac: 409a lsls r2, r3
36ae: 4302 orrs r2, r0
36b0: e7ef b.n 3692 <__aeabi_d2iz+0x2e>
36b2: 46c0 nop ; (mov r8, r8)
36b4: 000003fe .word 0x000003fe
36b8: 0000041d .word 0x0000041d
36bc: 00000433 .word 0x00000433
36c0: 00000413 .word 0x00000413
36c4: 7fffffff .word 0x7fffffff
36c8: fffffbed .word 0xfffffbed
000036cc <__aeabi_ui2d>:
36cc: b510 push {r4, lr}
36ce: 1e04 subs r4, r0, #0
36d0: d028 beq.n 3724 <__aeabi_ui2d+0x58>
36d2: f000 f833 bl 373c <__clzsi2>
36d6: 4b15 ldr r3, [pc, #84] ; (372c <__aeabi_ui2d+0x60>)
36d8: 4a15 ldr r2, [pc, #84] ; (3730 <__aeabi_ui2d+0x64>)
36da: 1a1b subs r3, r3, r0
36dc: 1ad2 subs r2, r2, r3
36de: 2a1f cmp r2, #31
36e0: dd15 ble.n 370e <__aeabi_ui2d+0x42>
36e2: 4a14 ldr r2, [pc, #80] ; (3734 <__aeabi_ui2d+0x68>)
36e4: 1ad2 subs r2, r2, r3
36e6: 4094 lsls r4, r2
36e8: 2200 movs r2, #0
36ea: 0324 lsls r4, r4, #12
36ec: 055b lsls r3, r3, #21
36ee: 0b24 lsrs r4, r4, #12
36f0: 0d5b lsrs r3, r3, #21
36f2: 2100 movs r1, #0
36f4: 0010 movs r0, r2
36f6: 0324 lsls r4, r4, #12
36f8: 0d0a lsrs r2, r1, #20
36fa: 0b24 lsrs r4, r4, #12
36fc: 0512 lsls r2, r2, #20
36fe: 4322 orrs r2, r4
3700: 4c0d ldr r4, [pc, #52] ; (3738 <__aeabi_ui2d+0x6c>)
3702: 051b lsls r3, r3, #20
3704: 4022 ands r2, r4
3706: 4313 orrs r3, r2
3708: 005b lsls r3, r3, #1
370a: 0859 lsrs r1, r3, #1
370c: bd10 pop {r4, pc}
370e: 0021 movs r1, r4
3710: 4091 lsls r1, r2
3712: 000a movs r2, r1
3714: 210b movs r1, #11
3716: 1a08 subs r0, r1, r0
3718: 40c4 lsrs r4, r0
371a: 055b lsls r3, r3, #21
371c: 0324 lsls r4, r4, #12
371e: 0b24 lsrs r4, r4, #12
3720: 0d5b lsrs r3, r3, #21
3722: e7e6 b.n 36f2 <__aeabi_ui2d+0x26>
3724: 2300 movs r3, #0
3726: 2400 movs r4, #0
3728: 2200 movs r2, #0
372a: e7e2 b.n 36f2 <__aeabi_ui2d+0x26>
372c: 0000041e .word 0x0000041e
3730: 00000433 .word 0x00000433
3734: 00000413 .word 0x00000413
3738: 800fffff .word 0x800fffff
0000373c <__clzsi2>:
373c: 211c movs r1, #28
373e: 2301 movs r3, #1
3740: 041b lsls r3, r3, #16
3742: 4298 cmp r0, r3
3744: d301 bcc.n 374a <__clzsi2+0xe>
3746: 0c00 lsrs r0, r0, #16
3748: 3910 subs r1, #16
374a: 0a1b lsrs r3, r3, #8
374c: 4298 cmp r0, r3
374e: d301 bcc.n 3754 <__clzsi2+0x18>
3750: 0a00 lsrs r0, r0, #8
3752: 3908 subs r1, #8
3754: 091b lsrs r3, r3, #4
3756: 4298 cmp r0, r3
3758: d301 bcc.n 375e <__clzsi2+0x22>
375a: 0900 lsrs r0, r0, #4
375c: 3904 subs r1, #4
375e: a202 add r2, pc, #8 ; (adr r2, 3768 <__clzsi2+0x2c>)
3760: 5c10 ldrb r0, [r2, r0]
3762: 1840 adds r0, r0, r1
3764: 4770 bx lr
3766: 46c0 nop ; (mov r8, r8)
3768: 02020304 .word 0x02020304
376c: 01010101 .word 0x01010101
...
00003778 <__libc_init_array>:
3778: b570 push {r4, r5, r6, lr}
377a: 2600 movs r6, #0
377c: 4d0c ldr r5, [pc, #48] ; (37b0 <__libc_init_array+0x38>)
377e: 4c0d ldr r4, [pc, #52] ; (37b4 <__libc_init_array+0x3c>)
3780: 1b64 subs r4, r4, r5
3782: 10a4 asrs r4, r4, #2
3784: 42a6 cmp r6, r4
3786: d109 bne.n 379c <__libc_init_array+0x24>
3788: 2600 movs r6, #0
378a: f001 f949 bl 4a20 <_init>
378e: 4d0a ldr r5, [pc, #40] ; (37b8 <__libc_init_array+0x40>)
3790: 4c0a ldr r4, [pc, #40] ; (37bc <__libc_init_array+0x44>)
3792: 1b64 subs r4, r4, r5
3794: 10a4 asrs r4, r4, #2
3796: 42a6 cmp r6, r4
3798: d105 bne.n 37a6 <__libc_init_array+0x2e>
379a: bd70 pop {r4, r5, r6, pc}
379c: 00b3 lsls r3, r6, #2
379e: 58eb ldr r3, [r5, r3]
37a0: 4798 blx r3
37a2: 3601 adds r6, #1
37a4: e7ee b.n 3784 <__libc_init_array+0xc>
37a6: 00b3 lsls r3, r6, #2
37a8: 58eb ldr r3, [r5, r3]
37aa: 4798 blx r3
37ac: 3601 adds r6, #1
37ae: e7f2 b.n 3796 <__libc_init_array+0x1e>
37b0: 00004a2c .word 0x00004a2c
37b4: 00004a2c .word 0x00004a2c
37b8: 00004a2c .word 0x00004a2c
37bc: 00004a30 .word 0x00004a30
000037c0 <memset>:
37c0: 0003 movs r3, r0
37c2: 1882 adds r2, r0, r2
37c4: 4293 cmp r3, r2
37c6: d100 bne.n 37ca <memset+0xa>
37c8: 4770 bx lr
37ca: 7019 strb r1, [r3, #0]
37cc: 3301 adds r3, #1
37ce: e7f9 b.n 37c4 <memset+0x4>
000037d0 <iprintf>:
37d0: b40f push {r0, r1, r2, r3}
37d2: 4b0b ldr r3, [pc, #44] ; (3800 <iprintf+0x30>)
37d4: b513 push {r0, r1, r4, lr}
37d6: 681c ldr r4, [r3, #0]
37d8: 2c00 cmp r4, #0
37da: d005 beq.n 37e8 <iprintf+0x18>
37dc: 69a3 ldr r3, [r4, #24]
37de: 2b00 cmp r3, #0
37e0: d102 bne.n 37e8 <iprintf+0x18>
37e2: 0020 movs r0, r4
37e4: f000 faf2 bl 3dcc <__sinit>
37e8: ab05 add r3, sp, #20
37ea: 9a04 ldr r2, [sp, #16]
37ec: 68a1 ldr r1, [r4, #8]
37ee: 0020 movs r0, r4
37f0: 9301 str r3, [sp, #4]
37f2: f000 fcc7 bl 4184 <_vfiprintf_r>
37f6: bc16 pop {r1, r2, r4}
37f8: bc08 pop {r3}
37fa: b004 add sp, #16
37fc: 4718 bx r3
37fe: 46c0 nop ; (mov r8, r8)
3800: 20000004 .word 0x20000004
00003804 <_puts_r>:
3804: b570 push {r4, r5, r6, lr}
3806: 0005 movs r5, r0
3808: 000e movs r6, r1
380a: 2800 cmp r0, #0
380c: d004 beq.n 3818 <_puts_r+0x14>
380e: 6983 ldr r3, [r0, #24]
3810: 2b00 cmp r3, #0
3812: d101 bne.n 3818 <_puts_r+0x14>
3814: f000 fada bl 3dcc <__sinit>
3818: 69ab ldr r3, [r5, #24]
381a: 68ac ldr r4, [r5, #8]
381c: 2b00 cmp r3, #0
381e: d102 bne.n 3826 <_puts_r+0x22>
3820: 0028 movs r0, r5
3822: f000 fad3 bl 3dcc <__sinit>
3826: 4b24 ldr r3, [pc, #144] ; (38b8 <_puts_r+0xb4>)
3828: 429c cmp r4, r3
382a: d10f bne.n 384c <_puts_r+0x48>
382c: 686c ldr r4, [r5, #4]
382e: 89a3 ldrh r3, [r4, #12]
3830: 071b lsls r3, r3, #28
3832: d502 bpl.n 383a <_puts_r+0x36>
3834: 6923 ldr r3, [r4, #16]
3836: 2b00 cmp r3, #0
3838: d120 bne.n 387c <_puts_r+0x78>
383a: 0021 movs r1, r4
383c: 0028 movs r0, r5
383e: f000 f957 bl 3af0 <__swsetup_r>
3842: 2800 cmp r0, #0
3844: d01a beq.n 387c <_puts_r+0x78>
3846: 2001 movs r0, #1
3848: 4240 negs r0, r0
384a: bd70 pop {r4, r5, r6, pc}
384c: 4b1b ldr r3, [pc, #108] ; (38bc <_puts_r+0xb8>)
384e: 429c cmp r4, r3
3850: d101 bne.n 3856 <_puts_r+0x52>
3852: 68ac ldr r4, [r5, #8]
3854: e7eb b.n 382e <_puts_r+0x2a>
3856: 4b1a ldr r3, [pc, #104] ; (38c0 <_puts_r+0xbc>)
3858: 429c cmp r4, r3
385a: d1e8 bne.n 382e <_puts_r+0x2a>
385c: 68ec ldr r4, [r5, #12]
385e: e7e6 b.n 382e <_puts_r+0x2a>
3860: 3b01 subs r3, #1
3862: 3601 adds r6, #1
3864: 60a3 str r3, [r4, #8]
3866: 2b00 cmp r3, #0
3868: da04 bge.n 3874 <_puts_r+0x70>
386a: 69a2 ldr r2, [r4, #24]
386c: 4293 cmp r3, r2
386e: db16 blt.n 389e <_puts_r+0x9a>
3870: 290a cmp r1, #10
3872: d014 beq.n 389e <_puts_r+0x9a>
3874: 6823 ldr r3, [r4, #0]
3876: 1c5a adds r2, r3, #1
3878: 6022 str r2, [r4, #0]
387a: 7019 strb r1, [r3, #0]
387c: 7831 ldrb r1, [r6, #0]
387e: 68a3 ldr r3, [r4, #8]
3880: 2900 cmp r1, #0
3882: d1ed bne.n 3860 <_puts_r+0x5c>
3884: 3b01 subs r3, #1
3886: 60a3 str r3, [r4, #8]
3888: 2b00 cmp r3, #0
388a: da0f bge.n 38ac <_puts_r+0xa8>
388c: 0022 movs r2, r4
388e: 310a adds r1, #10
3890: 0028 movs r0, r5
3892: f000 f8d7 bl 3a44 <__swbuf_r>
3896: 1c43 adds r3, r0, #1
3898: d0d5 beq.n 3846 <_puts_r+0x42>
389a: 200a movs r0, #10
389c: e7d5 b.n 384a <_puts_r+0x46>
389e: 0022 movs r2, r4
38a0: 0028 movs r0, r5
38a2: f000 f8cf bl 3a44 <__swbuf_r>
38a6: 1c43 adds r3, r0, #1
38a8: d1e8 bne.n 387c <_puts_r+0x78>
38aa: e7cc b.n 3846 <_puts_r+0x42>
38ac: 200a movs r0, #10
38ae: 6823 ldr r3, [r4, #0]
38b0: 1c5a adds r2, r3, #1
38b2: 6022 str r2, [r4, #0]
38b4: 7018 strb r0, [r3, #0]
38b6: e7c8 b.n 384a <_puts_r+0x46>
38b8: 000049ac .word 0x000049ac
38bc: 000049cc .word 0x000049cc
38c0: 0000498c .word 0x0000498c
000038c4 <puts>:
38c4: b510 push {r4, lr}
38c6: 4b03 ldr r3, [pc, #12] ; (38d4 <puts+0x10>)
38c8: 0001 movs r1, r0
38ca: 6818 ldr r0, [r3, #0]
38cc: f7ff ff9a bl 3804 <_puts_r>
38d0: bd10 pop {r4, pc}
38d2: 46c0 nop ; (mov r8, r8)
38d4: 20000004 .word 0x20000004
000038d8 <setbuf>:
38d8: 424a negs r2, r1
38da: 414a adcs r2, r1
38dc: 2380 movs r3, #128 ; 0x80
38de: b510 push {r4, lr}
38e0: 0052 lsls r2, r2, #1
38e2: 00db lsls r3, r3, #3
38e4: f000 f802 bl 38ec <setvbuf>
38e8: bd10 pop {r4, pc}
...
000038ec <setvbuf>:
38ec: b5f0 push {r4, r5, r6, r7, lr}
38ee: 001d movs r5, r3
38f0: 4b4f ldr r3, [pc, #316] ; (3a30 <setvbuf+0x144>)
38f2: b085 sub sp, #20
38f4: 681e ldr r6, [r3, #0]
38f6: 0004 movs r4, r0
38f8: 000f movs r7, r1
38fa: 9200 str r2, [sp, #0]
38fc: 2e00 cmp r6, #0
38fe: d005 beq.n 390c <setvbuf+0x20>
3900: 69b3 ldr r3, [r6, #24]
3902: 2b00 cmp r3, #0
3904: d102 bne.n 390c <setvbuf+0x20>
3906: 0030 movs r0, r6
3908: f000 fa60 bl 3dcc <__sinit>
390c: 4b49 ldr r3, [pc, #292] ; (3a34 <setvbuf+0x148>)
390e: 429c cmp r4, r3
3910: d150 bne.n 39b4 <setvbuf+0xc8>
3912: 6874 ldr r4, [r6, #4]
3914: 9b00 ldr r3, [sp, #0]
3916: 2b02 cmp r3, #2
3918: d005 beq.n 3926 <setvbuf+0x3a>
391a: 2b01 cmp r3, #1
391c: d900 bls.n 3920 <setvbuf+0x34>
391e: e084 b.n 3a2a <setvbuf+0x13e>
3920: 2d00 cmp r5, #0
3922: da00 bge.n 3926 <setvbuf+0x3a>
3924: e081 b.n 3a2a <setvbuf+0x13e>
3926: 0021 movs r1, r4
3928: 0030 movs r0, r6
392a: f000 f9e1 bl 3cf0 <_fflush_r>
392e: 6b61 ldr r1, [r4, #52] ; 0x34
3930: 2900 cmp r1, #0
3932: d008 beq.n 3946 <setvbuf+0x5a>
3934: 0023 movs r3, r4
3936: 3344 adds r3, #68 ; 0x44
3938: 4299 cmp r1, r3
393a: d002 beq.n 3942 <setvbuf+0x56>
393c: 0030 movs r0, r6
393e: f000 fb51 bl 3fe4 <_free_r>
3942: 2300 movs r3, #0
3944: 6363 str r3, [r4, #52] ; 0x34
3946: 2300 movs r3, #0
3948: 61a3 str r3, [r4, #24]
394a: 6063 str r3, [r4, #4]
394c: 89a3 ldrh r3, [r4, #12]
394e: 061b lsls r3, r3, #24
3950: d503 bpl.n 395a <setvbuf+0x6e>
3952: 6921 ldr r1, [r4, #16]
3954: 0030 movs r0, r6
3956: f000 fb45 bl 3fe4 <_free_r>
395a: 89a3 ldrh r3, [r4, #12]
395c: 4a36 ldr r2, [pc, #216] ; (3a38 <setvbuf+0x14c>)
395e: 4013 ands r3, r2
3960: 81a3 strh r3, [r4, #12]
3962: 9b00 ldr r3, [sp, #0]
3964: 2b02 cmp r3, #2
3966: d05a beq.n 3a1e <setvbuf+0x132>
3968: ab03 add r3, sp, #12
396a: aa02 add r2, sp, #8
396c: 0021 movs r1, r4
396e: 0030 movs r0, r6
3970: f000 fac2 bl 3ef8 <__swhatbuf_r>
3974: 89a3 ldrh r3, [r4, #12]
3976: 4318 orrs r0, r3
3978: 81a0 strh r0, [r4, #12]
397a: 2d00 cmp r5, #0
397c: d124 bne.n 39c8 <setvbuf+0xdc>
397e: 9d02 ldr r5, [sp, #8]
3980: 0028 movs r0, r5
3982: f000 fb25 bl 3fd0 <malloc>
3986: 9501 str r5, [sp, #4]
3988: 1e07 subs r7, r0, #0
398a: d142 bne.n 3a12 <setvbuf+0x126>
398c: 9b02 ldr r3, [sp, #8]
398e: 9301 str r3, [sp, #4]
3990: 42ab cmp r3, r5
3992: d139 bne.n 3a08 <setvbuf+0x11c>
3994: 2001 movs r0, #1
3996: 4240 negs r0, r0
3998: 2302 movs r3, #2
399a: 89a2 ldrh r2, [r4, #12]
399c: 4313 orrs r3, r2
399e: 81a3 strh r3, [r4, #12]
39a0: 2300 movs r3, #0
39a2: 60a3 str r3, [r4, #8]
39a4: 0023 movs r3, r4
39a6: 3347 adds r3, #71 ; 0x47
39a8: 6023 str r3, [r4, #0]
39aa: 6123 str r3, [r4, #16]
39ac: 2301 movs r3, #1
39ae: 6163 str r3, [r4, #20]
39b0: b005 add sp, #20
39b2: bdf0 pop {r4, r5, r6, r7, pc}
39b4: 4b21 ldr r3, [pc, #132] ; (3a3c <setvbuf+0x150>)
39b6: 429c cmp r4, r3
39b8: d101 bne.n 39be <setvbuf+0xd2>
39ba: 68b4 ldr r4, [r6, #8]
39bc: e7aa b.n 3914 <setvbuf+0x28>
39be: 4b20 ldr r3, [pc, #128] ; (3a40 <setvbuf+0x154>)
39c0: 429c cmp r4, r3
39c2: d1a7 bne.n 3914 <setvbuf+0x28>
39c4: 68f4 ldr r4, [r6, #12]
39c6: e7a5 b.n 3914 <setvbuf+0x28>
39c8: 2f00 cmp r7, #0
39ca: d0d9 beq.n 3980 <setvbuf+0x94>
39cc: 69b3 ldr r3, [r6, #24]
39ce: 2b00 cmp r3, #0
39d0: d102 bne.n 39d8 <setvbuf+0xec>
39d2: 0030 movs r0, r6
39d4: f000 f9fa bl 3dcc <__sinit>
39d8: 9b00 ldr r3, [sp, #0]
39da: 2b01 cmp r3, #1
39dc: d103 bne.n 39e6 <setvbuf+0xfa>
39de: 89a3 ldrh r3, [r4, #12]
39e0: 9a00 ldr r2, [sp, #0]
39e2: 431a orrs r2, r3
39e4: 81a2 strh r2, [r4, #12]
39e6: 2008 movs r0, #8
39e8: 89a3 ldrh r3, [r4, #12]
39ea: 6027 str r7, [r4, #0]
39ec: 6127 str r7, [r4, #16]
39ee: 6165 str r5, [r4, #20]
39f0: 4018 ands r0, r3
39f2: d018 beq.n 3a26 <setvbuf+0x13a>
39f4: 2001 movs r0, #1
39f6: 4018 ands r0, r3
39f8: 2300 movs r3, #0
39fa: 4298 cmp r0, r3
39fc: d011 beq.n 3a22 <setvbuf+0x136>
39fe: 426d negs r5, r5
3a00: 60a3 str r3, [r4, #8]
3a02: 61a5 str r5, [r4, #24]
3a04: 0018 movs r0, r3
3a06: e7d3 b.n 39b0 <setvbuf+0xc4>
3a08: 9801 ldr r0, [sp, #4]
3a0a: f000 fae1 bl 3fd0 <malloc>
3a0e: 1e07 subs r7, r0, #0
3a10: d0c0 beq.n 3994 <setvbuf+0xa8>
3a12: 2380 movs r3, #128 ; 0x80
3a14: 89a2 ldrh r2, [r4, #12]
3a16: 9d01 ldr r5, [sp, #4]
3a18: 4313 orrs r3, r2
3a1a: 81a3 strh r3, [r4, #12]
3a1c: e7d6 b.n 39cc <setvbuf+0xe0>
3a1e: 2000 movs r0, #0
3a20: e7ba b.n 3998 <setvbuf+0xac>
3a22: 60a5 str r5, [r4, #8]
3a24: e7c4 b.n 39b0 <setvbuf+0xc4>
3a26: 60a0 str r0, [r4, #8]
3a28: e7c2 b.n 39b0 <setvbuf+0xc4>
3a2a: 2001 movs r0, #1
3a2c: 4240 negs r0, r0
3a2e: e7bf b.n 39b0 <setvbuf+0xc4>
3a30: 20000004 .word 0x20000004
3a34: 000049ac .word 0x000049ac
3a38: fffff35c .word 0xfffff35c
3a3c: 000049cc .word 0x000049cc
3a40: 0000498c .word 0x0000498c
00003a44 <__swbuf_r>:
3a44: b5f8 push {r3, r4, r5, r6, r7, lr}
3a46: 0005 movs r5, r0
3a48: 000e movs r6, r1
3a4a: 0014 movs r4, r2
3a4c: 2800 cmp r0, #0
3a4e: d004 beq.n 3a5a <__swbuf_r+0x16>
3a50: 6983 ldr r3, [r0, #24]
3a52: 2b00 cmp r3, #0
3a54: d101 bne.n 3a5a <__swbuf_r+0x16>
3a56: f000 f9b9 bl 3dcc <__sinit>
3a5a: 4b22 ldr r3, [pc, #136] ; (3ae4 <__swbuf_r+0xa0>)
3a5c: 429c cmp r4, r3
3a5e: d12d bne.n 3abc <__swbuf_r+0x78>
3a60: 686c ldr r4, [r5, #4]
3a62: 69a3 ldr r3, [r4, #24]
3a64: 60a3 str r3, [r4, #8]
3a66: 89a3 ldrh r3, [r4, #12]
3a68: 071b lsls r3, r3, #28
3a6a: d531 bpl.n 3ad0 <__swbuf_r+0x8c>
3a6c: 6923 ldr r3, [r4, #16]
3a6e: 2b00 cmp r3, #0
3a70: d02e beq.n 3ad0 <__swbuf_r+0x8c>
3a72: 6823 ldr r3, [r4, #0]
3a74: 6922 ldr r2, [r4, #16]
3a76: b2f7 uxtb r7, r6
3a78: 1a98 subs r0, r3, r2
3a7a: 6963 ldr r3, [r4, #20]
3a7c: b2f6 uxtb r6, r6
3a7e: 4298 cmp r0, r3
3a80: db05 blt.n 3a8e <__swbuf_r+0x4a>
3a82: 0021 movs r1, r4
3a84: 0028 movs r0, r5
3a86: f000 f933 bl 3cf0 <_fflush_r>
3a8a: 2800 cmp r0, #0
3a8c: d126 bne.n 3adc <__swbuf_r+0x98>
3a8e: 68a3 ldr r3, [r4, #8]
3a90: 3001 adds r0, #1
3a92: 3b01 subs r3, #1
3a94: 60a3 str r3, [r4, #8]
3a96: 6823 ldr r3, [r4, #0]
3a98: 1c5a adds r2, r3, #1
3a9a: 6022 str r2, [r4, #0]
3a9c: 701f strb r7, [r3, #0]
3a9e: 6963 ldr r3, [r4, #20]
3aa0: 4298 cmp r0, r3
3aa2: d004 beq.n 3aae <__swbuf_r+0x6a>
3aa4: 89a3 ldrh r3, [r4, #12]
3aa6: 07db lsls r3, r3, #31
3aa8: d51a bpl.n 3ae0 <__swbuf_r+0x9c>
3aaa: 2e0a cmp r6, #10
3aac: d118 bne.n 3ae0 <__swbuf_r+0x9c>
3aae: 0021 movs r1, r4
3ab0: 0028 movs r0, r5
3ab2: f000 f91d bl 3cf0 <_fflush_r>
3ab6: 2800 cmp r0, #0
3ab8: d012 beq.n 3ae0 <__swbuf_r+0x9c>
3aba: e00f b.n 3adc <__swbuf_r+0x98>
3abc: 4b0a ldr r3, [pc, #40] ; (3ae8 <__swbuf_r+0xa4>)
3abe: 429c cmp r4, r3
3ac0: d101 bne.n 3ac6 <__swbuf_r+0x82>
3ac2: 68ac ldr r4, [r5, #8]
3ac4: e7cd b.n 3a62 <__swbuf_r+0x1e>
3ac6: 4b09 ldr r3, [pc, #36] ; (3aec <__swbuf_r+0xa8>)
3ac8: 429c cmp r4, r3
3aca: d1ca bne.n 3a62 <__swbuf_r+0x1e>
3acc: 68ec ldr r4, [r5, #12]
3ace: e7c8 b.n 3a62 <__swbuf_r+0x1e>
3ad0: 0021 movs r1, r4
3ad2: 0028 movs r0, r5
3ad4: f000 f80c bl 3af0 <__swsetup_r>
3ad8: 2800 cmp r0, #0
3ada: d0ca beq.n 3a72 <__swbuf_r+0x2e>
3adc: 2601 movs r6, #1
3ade: 4276 negs r6, r6
3ae0: 0030 movs r0, r6
3ae2: bdf8 pop {r3, r4, r5, r6, r7, pc}
3ae4: 000049ac .word 0x000049ac
3ae8: 000049cc .word 0x000049cc
3aec: 0000498c .word 0x0000498c
00003af0 <__swsetup_r>:
3af0: 4b36 ldr r3, [pc, #216] ; (3bcc <__swsetup_r+0xdc>)
3af2: b570 push {r4, r5, r6, lr}
3af4: 681d ldr r5, [r3, #0]
3af6: 0006 movs r6, r0
3af8: 000c movs r4, r1
3afa: 2d00 cmp r5, #0
3afc: d005 beq.n 3b0a <__swsetup_r+0x1a>
3afe: 69ab ldr r3, [r5, #24]
3b00: 2b00 cmp r3, #0
3b02: d102 bne.n 3b0a <__swsetup_r+0x1a>
3b04: 0028 movs r0, r5
3b06: f000 f961 bl 3dcc <__sinit>
3b0a: 4b31 ldr r3, [pc, #196] ; (3bd0 <__swsetup_r+0xe0>)
3b0c: 429c cmp r4, r3
3b0e: d10f bne.n 3b30 <__swsetup_r+0x40>
3b10: 686c ldr r4, [r5, #4]
3b12: 230c movs r3, #12
3b14: 5ee2 ldrsh r2, [r4, r3]
3b16: b293 uxth r3, r2
3b18: 0719 lsls r1, r3, #28
3b1a: d42d bmi.n 3b78 <__swsetup_r+0x88>
3b1c: 06d9 lsls r1, r3, #27
3b1e: d411 bmi.n 3b44 <__swsetup_r+0x54>
3b20: 2309 movs r3, #9
3b22: 2001 movs r0, #1
3b24: 6033 str r3, [r6, #0]
3b26: 3337 adds r3, #55 ; 0x37
3b28: 4313 orrs r3, r2
3b2a: 81a3 strh r3, [r4, #12]
3b2c: 4240 negs r0, r0
3b2e: bd70 pop {r4, r5, r6, pc}
3b30: 4b28 ldr r3, [pc, #160] ; (3bd4 <__swsetup_r+0xe4>)
3b32: 429c cmp r4, r3
3b34: d101 bne.n 3b3a <__swsetup_r+0x4a>
3b36: 68ac ldr r4, [r5, #8]
3b38: e7eb b.n 3b12 <__swsetup_r+0x22>
3b3a: 4b27 ldr r3, [pc, #156] ; (3bd8 <__swsetup_r+0xe8>)
3b3c: 429c cmp r4, r3
3b3e: d1e8 bne.n 3b12 <__swsetup_r+0x22>
3b40: 68ec ldr r4, [r5, #12]
3b42: e7e6 b.n 3b12 <__swsetup_r+0x22>
3b44: 075b lsls r3, r3, #29
3b46: d513 bpl.n 3b70 <__swsetup_r+0x80>
3b48: 6b61 ldr r1, [r4, #52] ; 0x34
3b4a: 2900 cmp r1, #0
3b4c: d008 beq.n 3b60 <__swsetup_r+0x70>
3b4e: 0023 movs r3, r4
3b50: 3344 adds r3, #68 ; 0x44
3b52: 4299 cmp r1, r3
3b54: d002 beq.n 3b5c <__swsetup_r+0x6c>
3b56: 0030 movs r0, r6
3b58: f000 fa44 bl 3fe4 <_free_r>
3b5c: 2300 movs r3, #0
3b5e: 6363 str r3, [r4, #52] ; 0x34
3b60: 2224 movs r2, #36 ; 0x24
3b62: 89a3 ldrh r3, [r4, #12]
3b64: 4393 bics r3, r2
3b66: 81a3 strh r3, [r4, #12]
3b68: 2300 movs r3, #0
3b6a: 6063 str r3, [r4, #4]
3b6c: 6923 ldr r3, [r4, #16]
3b6e: 6023 str r3, [r4, #0]
3b70: 2308 movs r3, #8
3b72: 89a2 ldrh r2, [r4, #12]
3b74: 4313 orrs r3, r2
3b76: 81a3 strh r3, [r4, #12]
3b78: 6923 ldr r3, [r4, #16]
3b7a: 2b00 cmp r3, #0
3b7c: d10b bne.n 3b96 <__swsetup_r+0xa6>
3b7e: 21a0 movs r1, #160 ; 0xa0
3b80: 2280 movs r2, #128 ; 0x80
3b82: 89a3 ldrh r3, [r4, #12]
3b84: 0089 lsls r1, r1, #2
3b86: 0092 lsls r2, r2, #2
3b88: 400b ands r3, r1
3b8a: 4293 cmp r3, r2
3b8c: d003 beq.n 3b96 <__swsetup_r+0xa6>
3b8e: 0021 movs r1, r4
3b90: 0030 movs r0, r6
3b92: f000 f9d9 bl 3f48 <__smakebuf_r>
3b96: 2301 movs r3, #1
3b98: 89a2 ldrh r2, [r4, #12]
3b9a: 4013 ands r3, r2
3b9c: d011 beq.n 3bc2 <__swsetup_r+0xd2>
3b9e: 2300 movs r3, #0
3ba0: 60a3 str r3, [r4, #8]
3ba2: 6963 ldr r3, [r4, #20]
3ba4: 425b negs r3, r3
3ba6: 61a3 str r3, [r4, #24]
3ba8: 2000 movs r0, #0
3baa: 6923 ldr r3, [r4, #16]
3bac: 4283 cmp r3, r0
3bae: d1be bne.n 3b2e <__swsetup_r+0x3e>
3bb0: 230c movs r3, #12
3bb2: 5ee2 ldrsh r2, [r4, r3]
3bb4: 0613 lsls r3, r2, #24
3bb6: d5ba bpl.n 3b2e <__swsetup_r+0x3e>
3bb8: 2340 movs r3, #64 ; 0x40
3bba: 4313 orrs r3, r2
3bbc: 81a3 strh r3, [r4, #12]
3bbe: 3801 subs r0, #1
3bc0: e7b5 b.n 3b2e <__swsetup_r+0x3e>
3bc2: 0792 lsls r2, r2, #30
3bc4: d400 bmi.n 3bc8 <__swsetup_r+0xd8>
3bc6: 6963 ldr r3, [r4, #20]
3bc8: 60a3 str r3, [r4, #8]
3bca: e7ed b.n 3ba8 <__swsetup_r+0xb8>
3bcc: 20000004 .word 0x20000004
3bd0: 000049ac .word 0x000049ac
3bd4: 000049cc .word 0x000049cc
3bd8: 0000498c .word 0x0000498c
00003bdc <__sflush_r>:
3bdc: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
3bde: 898a ldrh r2, [r1, #12]
3be0: 0005 movs r5, r0
3be2: 000c movs r4, r1
3be4: 0713 lsls r3, r2, #28
3be6: d460 bmi.n 3caa <__sflush_r+0xce>
3be8: 684b ldr r3, [r1, #4]
3bea: 2b00 cmp r3, #0
3bec: dc04 bgt.n 3bf8 <__sflush_r+0x1c>
3bee: 6c0b ldr r3, [r1, #64] ; 0x40
3bf0: 2b00 cmp r3, #0
3bf2: dc01 bgt.n 3bf8 <__sflush_r+0x1c>
3bf4: 2000 movs r0, #0
3bf6: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
3bf8: 6ae7 ldr r7, [r4, #44] ; 0x2c
3bfa: 2f00 cmp r7, #0
3bfc: d0fa beq.n 3bf4 <__sflush_r+0x18>
3bfe: 2300 movs r3, #0
3c00: 682e ldr r6, [r5, #0]
3c02: 602b str r3, [r5, #0]
3c04: 2380 movs r3, #128 ; 0x80
3c06: 015b lsls r3, r3, #5
3c08: 401a ands r2, r3
3c0a: d034 beq.n 3c76 <__sflush_r+0x9a>
3c0c: 6d60 ldr r0, [r4, #84] ; 0x54
3c0e: 89a3 ldrh r3, [r4, #12]
3c10: 075b lsls r3, r3, #29
3c12: d506 bpl.n 3c22 <__sflush_r+0x46>
3c14: 6863 ldr r3, [r4, #4]
3c16: 1ac0 subs r0, r0, r3
3c18: 6b63 ldr r3, [r4, #52] ; 0x34
3c1a: 2b00 cmp r3, #0
3c1c: d001 beq.n 3c22 <__sflush_r+0x46>
3c1e: 6c23 ldr r3, [r4, #64] ; 0x40
3c20: 1ac0 subs r0, r0, r3
3c22: 0002 movs r2, r0
3c24: 6a21 ldr r1, [r4, #32]
3c26: 2300 movs r3, #0
3c28: 0028 movs r0, r5
3c2a: 6ae7 ldr r7, [r4, #44] ; 0x2c
3c2c: 47b8 blx r7
3c2e: 89a1 ldrh r1, [r4, #12]
3c30: 1c43 adds r3, r0, #1
3c32: d106 bne.n 3c42 <__sflush_r+0x66>
3c34: 682b ldr r3, [r5, #0]
3c36: 2b1d cmp r3, #29
3c38: d831 bhi.n 3c9e <__sflush_r+0xc2>
3c3a: 4a2c ldr r2, [pc, #176] ; (3cec <__sflush_r+0x110>)
3c3c: 40da lsrs r2, r3
3c3e: 07d3 lsls r3, r2, #31
3c40: d52d bpl.n 3c9e <__sflush_r+0xc2>
3c42: 2300 movs r3, #0
3c44: 6063 str r3, [r4, #4]
3c46: 6923 ldr r3, [r4, #16]
3c48: 6023 str r3, [r4, #0]
3c4a: 04cb lsls r3, r1, #19
3c4c: d505 bpl.n 3c5a <__sflush_r+0x7e>
3c4e: 1c43 adds r3, r0, #1
3c50: d102 bne.n 3c58 <__sflush_r+0x7c>
3c52: 682b ldr r3, [r5, #0]
3c54: 2b00 cmp r3, #0
3c56: d100 bne.n 3c5a <__sflush_r+0x7e>
3c58: 6560 str r0, [r4, #84] ; 0x54
3c5a: 6b61 ldr r1, [r4, #52] ; 0x34
3c5c: 602e str r6, [r5, #0]
3c5e: 2900 cmp r1, #0
3c60: d0c8 beq.n 3bf4 <__sflush_r+0x18>
3c62: 0023 movs r3, r4
3c64: 3344 adds r3, #68 ; 0x44
3c66: 4299 cmp r1, r3
3c68: d002 beq.n 3c70 <__sflush_r+0x94>
3c6a: 0028 movs r0, r5
3c6c: f000 f9ba bl 3fe4 <_free_r>
3c70: 2000 movs r0, #0
3c72: 6360 str r0, [r4, #52] ; 0x34
3c74: e7bf b.n 3bf6 <__sflush_r+0x1a>
3c76: 2301 movs r3, #1
3c78: 6a21 ldr r1, [r4, #32]
3c7a: 0028 movs r0, r5
3c7c: 47b8 blx r7
3c7e: 1c43 adds r3, r0, #1
3c80: d1c5 bne.n 3c0e <__sflush_r+0x32>
3c82: 682b ldr r3, [r5, #0]
3c84: 2b00 cmp r3, #0
3c86: d0c2 beq.n 3c0e <__sflush_r+0x32>
3c88: 2b1d cmp r3, #29
3c8a: d001 beq.n 3c90 <__sflush_r+0xb4>
3c8c: 2b16 cmp r3, #22
3c8e: d101 bne.n 3c94 <__sflush_r+0xb8>
3c90: 602e str r6, [r5, #0]
3c92: e7af b.n 3bf4 <__sflush_r+0x18>
3c94: 2340 movs r3, #64 ; 0x40
3c96: 89a2 ldrh r2, [r4, #12]
3c98: 4313 orrs r3, r2
3c9a: 81a3 strh r3, [r4, #12]
3c9c: e7ab b.n 3bf6 <__sflush_r+0x1a>
3c9e: 2340 movs r3, #64 ; 0x40
3ca0: 430b orrs r3, r1
3ca2: 2001 movs r0, #1
3ca4: 81a3 strh r3, [r4, #12]
3ca6: 4240 negs r0, r0
3ca8: e7a5 b.n 3bf6 <__sflush_r+0x1a>
3caa: 690f ldr r7, [r1, #16]
3cac: 2f00 cmp r7, #0
3cae: d0a1 beq.n 3bf4 <__sflush_r+0x18>
3cb0: 680b ldr r3, [r1, #0]
3cb2: 600f str r7, [r1, #0]
3cb4: 1bdb subs r3, r3, r7
3cb6: 9301 str r3, [sp, #4]
3cb8: 2300 movs r3, #0
3cba: 0792 lsls r2, r2, #30
3cbc: d100 bne.n 3cc0 <__sflush_r+0xe4>
3cbe: 694b ldr r3, [r1, #20]
3cc0: 60a3 str r3, [r4, #8]
3cc2: 9b01 ldr r3, [sp, #4]
3cc4: 2b00 cmp r3, #0
3cc6: dc00 bgt.n 3cca <__sflush_r+0xee>
3cc8: e794 b.n 3bf4 <__sflush_r+0x18>
3cca: 9b01 ldr r3, [sp, #4]
3ccc: 003a movs r2, r7
3cce: 6a21 ldr r1, [r4, #32]
3cd0: 0028 movs r0, r5
3cd2: 6aa6 ldr r6, [r4, #40] ; 0x28
3cd4: 47b0 blx r6
3cd6: 2800 cmp r0, #0
3cd8: dc03 bgt.n 3ce2 <__sflush_r+0x106>
3cda: 2340 movs r3, #64 ; 0x40
3cdc: 89a2 ldrh r2, [r4, #12]
3cde: 4313 orrs r3, r2
3ce0: e7df b.n 3ca2 <__sflush_r+0xc6>
3ce2: 9b01 ldr r3, [sp, #4]
3ce4: 183f adds r7, r7, r0
3ce6: 1a1b subs r3, r3, r0
3ce8: 9301 str r3, [sp, #4]
3cea: e7ea b.n 3cc2 <__sflush_r+0xe6>
3cec: 20400001 .word 0x20400001
00003cf0 <_fflush_r>:
3cf0: 690b ldr r3, [r1, #16]
3cf2: b570 push {r4, r5, r6, lr}
3cf4: 0005 movs r5, r0
3cf6: 000c movs r4, r1
3cf8: 2b00 cmp r3, #0
3cfa: d101 bne.n 3d00 <_fflush_r+0x10>
3cfc: 2000 movs r0, #0
3cfe: bd70 pop {r4, r5, r6, pc}
3d00: 2800 cmp r0, #0
3d02: d004 beq.n 3d0e <_fflush_r+0x1e>
3d04: 6983 ldr r3, [r0, #24]
3d06: 2b00 cmp r3, #0
3d08: d101 bne.n 3d0e <_fflush_r+0x1e>
3d0a: f000 f85f bl 3dcc <__sinit>
3d0e: 4b0b ldr r3, [pc, #44] ; (3d3c <_fflush_r+0x4c>)
3d10: 429c cmp r4, r3
3d12: d109 bne.n 3d28 <_fflush_r+0x38>
3d14: 686c ldr r4, [r5, #4]
3d16: 220c movs r2, #12
3d18: 5ea3 ldrsh r3, [r4, r2]
3d1a: 2b00 cmp r3, #0
3d1c: d0ee beq.n 3cfc <_fflush_r+0xc>
3d1e: 0021 movs r1, r4
3d20: 0028 movs r0, r5
3d22: f7ff ff5b bl 3bdc <__sflush_r>
3d26: e7ea b.n 3cfe <_fflush_r+0xe>
3d28: 4b05 ldr r3, [pc, #20] ; (3d40 <_fflush_r+0x50>)
3d2a: 429c cmp r4, r3
3d2c: d101 bne.n 3d32 <_fflush_r+0x42>
3d2e: 68ac ldr r4, [r5, #8]
3d30: e7f1 b.n 3d16 <_fflush_r+0x26>
3d32: 4b04 ldr r3, [pc, #16] ; (3d44 <_fflush_r+0x54>)
3d34: 429c cmp r4, r3
3d36: d1ee bne.n 3d16 <_fflush_r+0x26>
3d38: 68ec ldr r4, [r5, #12]
3d3a: e7ec b.n 3d16 <_fflush_r+0x26>
3d3c: 000049ac .word 0x000049ac
3d40: 000049cc .word 0x000049cc
3d44: 0000498c .word 0x0000498c
00003d48 <_cleanup_r>:
3d48: b510 push {r4, lr}
3d4a: 4902 ldr r1, [pc, #8] ; (3d54 <_cleanup_r+0xc>)
3d4c: f000 f8b2 bl 3eb4 <_fwalk_reent>
3d50: bd10 pop {r4, pc}
3d52: 46c0 nop ; (mov r8, r8)
3d54: 00003cf1 .word 0x00003cf1
00003d58 <std.isra.0>:
3d58: 2300 movs r3, #0
3d5a: b510 push {r4, lr}
3d5c: 0004 movs r4, r0
3d5e: 6003 str r3, [r0, #0]
3d60: 6043 str r3, [r0, #4]
3d62: 6083 str r3, [r0, #8]
3d64: 8181 strh r1, [r0, #12]
3d66: 6643 str r3, [r0, #100] ; 0x64
3d68: 81c2 strh r2, [r0, #14]
3d6a: 6103 str r3, [r0, #16]
3d6c: 6143 str r3, [r0, #20]
3d6e: 6183 str r3, [r0, #24]
3d70: 0019 movs r1, r3
3d72: 2208 movs r2, #8
3d74: 305c adds r0, #92 ; 0x5c
3d76: f7ff fd23 bl 37c0 <memset>
3d7a: 4b05 ldr r3, [pc, #20] ; (3d90 <std.isra.0+0x38>)
3d7c: 6224 str r4, [r4, #32]
3d7e: 6263 str r3, [r4, #36] ; 0x24
3d80: 4b04 ldr r3, [pc, #16] ; (3d94 <std.isra.0+0x3c>)
3d82: 62a3 str r3, [r4, #40] ; 0x28
3d84: 4b04 ldr r3, [pc, #16] ; (3d98 <std.isra.0+0x40>)
3d86: 62e3 str r3, [r4, #44] ; 0x2c
3d88: 4b04 ldr r3, [pc, #16] ; (3d9c <std.isra.0+0x44>)
3d8a: 6323 str r3, [r4, #48] ; 0x30
3d8c: bd10 pop {r4, pc}
3d8e: 46c0 nop ; (mov r8, r8)
3d90: 000046f1 .word 0x000046f1
3d94: 00004719 .word 0x00004719
3d98: 00004751 .word 0x00004751
3d9c: 0000477d .word 0x0000477d
00003da0 <__sfmoreglue>:
3da0: b570 push {r4, r5, r6, lr}
3da2: 2568 movs r5, #104 ; 0x68
3da4: 1e4a subs r2, r1, #1
3da6: 4355 muls r5, r2
3da8: 000e movs r6, r1
3daa: 0029 movs r1, r5
3dac: 3174 adds r1, #116 ; 0x74
3dae: f000 f963 bl 4078 <_malloc_r>
3db2: 1e04 subs r4, r0, #0
3db4: d008 beq.n 3dc8 <__sfmoreglue+0x28>
3db6: 2100 movs r1, #0
3db8: 002a movs r2, r5
3dba: 6001 str r1, [r0, #0]
3dbc: 6046 str r6, [r0, #4]
3dbe: 300c adds r0, #12
3dc0: 60a0 str r0, [r4, #8]
3dc2: 3268 adds r2, #104 ; 0x68
3dc4: f7ff fcfc bl 37c0 <memset>
3dc8: 0020 movs r0, r4
3dca: bd70 pop {r4, r5, r6, pc}
00003dcc <__sinit>:
3dcc: 6983 ldr r3, [r0, #24]
3dce: b513 push {r0, r1, r4, lr}
3dd0: 0004 movs r4, r0
3dd2: 2b00 cmp r3, #0
3dd4: d128 bne.n 3e28 <__sinit+0x5c>
3dd6: 6483 str r3, [r0, #72] ; 0x48
3dd8: 64c3 str r3, [r0, #76] ; 0x4c
3dda: 6503 str r3, [r0, #80] ; 0x50
3ddc: 4b13 ldr r3, [pc, #76] ; (3e2c <__sinit+0x60>)
3dde: 4a14 ldr r2, [pc, #80] ; (3e30 <__sinit+0x64>)
3de0: 681b ldr r3, [r3, #0]
3de2: 6282 str r2, [r0, #40] ; 0x28
3de4: 9301 str r3, [sp, #4]
3de6: 4298 cmp r0, r3
3de8: d101 bne.n 3dee <__sinit+0x22>
3dea: 2301 movs r3, #1
3dec: 6183 str r3, [r0, #24]
3dee: 0020 movs r0, r4
3df0: f000 f820 bl 3e34 <__sfp>
3df4: 6060 str r0, [r4, #4]
3df6: 0020 movs r0, r4
3df8: f000 f81c bl 3e34 <__sfp>
3dfc: 60a0 str r0, [r4, #8]
3dfe: 0020 movs r0, r4
3e00: f000 f818 bl 3e34 <__sfp>
3e04: 2200 movs r2, #0
3e06: 60e0 str r0, [r4, #12]
3e08: 2104 movs r1, #4
3e0a: 6860 ldr r0, [r4, #4]
3e0c: f7ff ffa4 bl 3d58 <std.isra.0>
3e10: 2201 movs r2, #1
3e12: 2109 movs r1, #9
3e14: 68a0 ldr r0, [r4, #8]
3e16: f7ff ff9f bl 3d58 <std.isra.0>
3e1a: 2202 movs r2, #2
3e1c: 2112 movs r1, #18
3e1e: 68e0 ldr r0, [r4, #12]
3e20: f7ff ff9a bl 3d58 <std.isra.0>
3e24: 2301 movs r3, #1
3e26: 61a3 str r3, [r4, #24]
3e28: bd13 pop {r0, r1, r4, pc}
3e2a: 46c0 nop ; (mov r8, r8)
3e2c: 00004988 .word 0x00004988
3e30: 00003d49 .word 0x00003d49
00003e34 <__sfp>:
3e34: b5f8 push {r3, r4, r5, r6, r7, lr}
3e36: 4b1e ldr r3, [pc, #120] ; (3eb0 <__sfp+0x7c>)
3e38: 0007 movs r7, r0
3e3a: 681e ldr r6, [r3, #0]
3e3c: 69b3 ldr r3, [r6, #24]
3e3e: 2b00 cmp r3, #0
3e40: d102 bne.n 3e48 <__sfp+0x14>
3e42: 0030 movs r0, r6
3e44: f7ff ffc2 bl 3dcc <__sinit>
3e48: 3648 adds r6, #72 ; 0x48
3e4a: 68b4 ldr r4, [r6, #8]
3e4c: 6873 ldr r3, [r6, #4]
3e4e: 3b01 subs r3, #1
3e50: d504 bpl.n 3e5c <__sfp+0x28>
3e52: 6833 ldr r3, [r6, #0]
3e54: 2b00 cmp r3, #0
3e56: d007 beq.n 3e68 <__sfp+0x34>
3e58: 6836 ldr r6, [r6, #0]
3e5a: e7f6 b.n 3e4a <__sfp+0x16>
3e5c: 220c movs r2, #12
3e5e: 5ea5 ldrsh r5, [r4, r2]
3e60: 2d00 cmp r5, #0
3e62: d00d beq.n 3e80 <__sfp+0x4c>
3e64: 3468 adds r4, #104 ; 0x68
3e66: e7f2 b.n 3e4e <__sfp+0x1a>
3e68: 2104 movs r1, #4
3e6a: 0038 movs r0, r7
3e6c: f7ff ff98 bl 3da0 <__sfmoreglue>
3e70: 6030 str r0, [r6, #0]
3e72: 2800 cmp r0, #0
3e74: d1f0 bne.n 3e58 <__sfp+0x24>
3e76: 230c movs r3, #12
3e78: 0004 movs r4, r0
3e7a: 603b str r3, [r7, #0]
3e7c: 0020 movs r0, r4
3e7e: bdf8 pop {r3, r4, r5, r6, r7, pc}
3e80: 2301 movs r3, #1
3e82: 0020 movs r0, r4
3e84: 425b negs r3, r3
3e86: 81e3 strh r3, [r4, #14]
3e88: 3302 adds r3, #2
3e8a: 81a3 strh r3, [r4, #12]
3e8c: 6665 str r5, [r4, #100] ; 0x64
3e8e: 6025 str r5, [r4, #0]
3e90: 60a5 str r5, [r4, #8]
3e92: 6065 str r5, [r4, #4]
3e94: 6125 str r5, [r4, #16]
3e96: 6165 str r5, [r4, #20]
3e98: 61a5 str r5, [r4, #24]
3e9a: 2208 movs r2, #8
3e9c: 0029 movs r1, r5
3e9e: 305c adds r0, #92 ; 0x5c
3ea0: f7ff fc8e bl 37c0 <memset>
3ea4: 6365 str r5, [r4, #52] ; 0x34
3ea6: 63a5 str r5, [r4, #56] ; 0x38
3ea8: 64a5 str r5, [r4, #72] ; 0x48
3eaa: 64e5 str r5, [r4, #76] ; 0x4c
3eac: e7e6 b.n 3e7c <__sfp+0x48>
3eae: 46c0 nop ; (mov r8, r8)
3eb0: 00004988 .word 0x00004988
00003eb4 <_fwalk_reent>:
3eb4: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
3eb6: 0004 movs r4, r0
3eb8: 0007 movs r7, r0
3eba: 2600 movs r6, #0
3ebc: 9101 str r1, [sp, #4]
3ebe: 3448 adds r4, #72 ; 0x48
3ec0: 2c00 cmp r4, #0
3ec2: d101 bne.n 3ec8 <_fwalk_reent+0x14>
3ec4: 0030 movs r0, r6
3ec6: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
3ec8: 6863 ldr r3, [r4, #4]
3eca: 68a5 ldr r5, [r4, #8]
3ecc: 9300 str r3, [sp, #0]
3ece: 9b00 ldr r3, [sp, #0]
3ed0: 3b01 subs r3, #1
3ed2: 9300 str r3, [sp, #0]
3ed4: d501 bpl.n 3eda <_fwalk_reent+0x26>
3ed6: 6824 ldr r4, [r4, #0]
3ed8: e7f2 b.n 3ec0 <_fwalk_reent+0xc>
3eda: 89ab ldrh r3, [r5, #12]
3edc: 2b01 cmp r3, #1
3ede: d908 bls.n 3ef2 <_fwalk_reent+0x3e>
3ee0: 220e movs r2, #14
3ee2: 5eab ldrsh r3, [r5, r2]
3ee4: 3301 adds r3, #1
3ee6: d004 beq.n 3ef2 <_fwalk_reent+0x3e>
3ee8: 0029 movs r1, r5
3eea: 0038 movs r0, r7
3eec: 9b01 ldr r3, [sp, #4]
3eee: 4798 blx r3
3ef0: 4306 orrs r6, r0
3ef2: 3568 adds r5, #104 ; 0x68
3ef4: e7eb b.n 3ece <_fwalk_reent+0x1a>
...
00003ef8 <__swhatbuf_r>:
3ef8: b570 push {r4, r5, r6, lr}
3efa: 000e movs r6, r1
3efc: 001d movs r5, r3
3efe: 230e movs r3, #14
3f00: 5ec9 ldrsh r1, [r1, r3]
3f02: b090 sub sp, #64 ; 0x40
3f04: 0014 movs r4, r2
3f06: 2900 cmp r1, #0
3f08: da07 bge.n 3f1a <__swhatbuf_r+0x22>
3f0a: 2300 movs r3, #0
3f0c: 602b str r3, [r5, #0]
3f0e: 89b3 ldrh r3, [r6, #12]
3f10: 061b lsls r3, r3, #24
3f12: d411 bmi.n 3f38 <__swhatbuf_r+0x40>
3f14: 2380 movs r3, #128 ; 0x80
3f16: 00db lsls r3, r3, #3
3f18: e00f b.n 3f3a <__swhatbuf_r+0x42>
3f1a: aa01 add r2, sp, #4
3f1c: f000 fc5a bl 47d4 <_fstat_r>
3f20: 2800 cmp r0, #0
3f22: dbf2 blt.n 3f0a <__swhatbuf_r+0x12>
3f24: 22f0 movs r2, #240 ; 0xf0
3f26: 9b02 ldr r3, [sp, #8]
3f28: 0212 lsls r2, r2, #8
3f2a: 4013 ands r3, r2
3f2c: 4a05 ldr r2, [pc, #20] ; (3f44 <__swhatbuf_r+0x4c>)
3f2e: 189b adds r3, r3, r2
3f30: 425a negs r2, r3
3f32: 4153 adcs r3, r2
3f34: 602b str r3, [r5, #0]
3f36: e7ed b.n 3f14 <__swhatbuf_r+0x1c>
3f38: 2340 movs r3, #64 ; 0x40
3f3a: 2000 movs r0, #0
3f3c: 6023 str r3, [r4, #0]
3f3e: b010 add sp, #64 ; 0x40
3f40: bd70 pop {r4, r5, r6, pc}
3f42: 46c0 nop ; (mov r8, r8)
3f44: ffffe000 .word 0xffffe000
00003f48 <__smakebuf_r>:
3f48: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
3f4a: 2602 movs r6, #2
3f4c: 898b ldrh r3, [r1, #12]
3f4e: 0005 movs r5, r0
3f50: 000c movs r4, r1
3f52: 4233 tst r3, r6
3f54: d006 beq.n 3f64 <__smakebuf_r+0x1c>
3f56: 0023 movs r3, r4
3f58: 3347 adds r3, #71 ; 0x47
3f5a: 6023 str r3, [r4, #0]
3f5c: 6123 str r3, [r4, #16]
3f5e: 2301 movs r3, #1
3f60: 6163 str r3, [r4, #20]
3f62: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
3f64: ab01 add r3, sp, #4
3f66: 466a mov r2, sp
3f68: f7ff ffc6 bl 3ef8 <__swhatbuf_r>
3f6c: 9900 ldr r1, [sp, #0]
3f6e: 0007 movs r7, r0
3f70: 0028 movs r0, r5
3f72: f000 f881 bl 4078 <_malloc_r>
3f76: 2800 cmp r0, #0
3f78: d108 bne.n 3f8c <__smakebuf_r+0x44>
3f7a: 220c movs r2, #12
3f7c: 5ea3 ldrsh r3, [r4, r2]
3f7e: 059a lsls r2, r3, #22
3f80: d4ef bmi.n 3f62 <__smakebuf_r+0x1a>
3f82: 2203 movs r2, #3
3f84: 4393 bics r3, r2
3f86: 431e orrs r6, r3
3f88: 81a6 strh r6, [r4, #12]
3f8a: e7e4 b.n 3f56 <__smakebuf_r+0xe>
3f8c: 4b0f ldr r3, [pc, #60] ; (3fcc <__smakebuf_r+0x84>)
3f8e: 62ab str r3, [r5, #40] ; 0x28
3f90: 2380 movs r3, #128 ; 0x80
3f92: 89a2 ldrh r2, [r4, #12]
3f94: 6020 str r0, [r4, #0]
3f96: 4313 orrs r3, r2
3f98: 81a3 strh r3, [r4, #12]
3f9a: 9b00 ldr r3, [sp, #0]
3f9c: 6120 str r0, [r4, #16]
3f9e: 6163 str r3, [r4, #20]
3fa0: 9b01 ldr r3, [sp, #4]
3fa2: 2b00 cmp r3, #0
3fa4: d00d beq.n 3fc2 <__smakebuf_r+0x7a>
3fa6: 230e movs r3, #14
3fa8: 5ee1 ldrsh r1, [r4, r3]
3faa: 0028 movs r0, r5
3fac: f000 fc24 bl 47f8 <_isatty_r>
3fb0: 2800 cmp r0, #0
3fb2: d006 beq.n 3fc2 <__smakebuf_r+0x7a>
3fb4: 2203 movs r2, #3
3fb6: 89a3 ldrh r3, [r4, #12]
3fb8: 4393 bics r3, r2
3fba: 001a movs r2, r3
3fbc: 2301 movs r3, #1
3fbe: 4313 orrs r3, r2
3fc0: 81a3 strh r3, [r4, #12]
3fc2: 89a0 ldrh r0, [r4, #12]
3fc4: 4338 orrs r0, r7
3fc6: 81a0 strh r0, [r4, #12]
3fc8: e7cb b.n 3f62 <__smakebuf_r+0x1a>
3fca: 46c0 nop ; (mov r8, r8)
3fcc: 00003d49 .word 0x00003d49
00003fd0 <malloc>:
3fd0: b510 push {r4, lr}
3fd2: 4b03 ldr r3, [pc, #12] ; (3fe0 <malloc+0x10>)
3fd4: 0001 movs r1, r0
3fd6: 6818 ldr r0, [r3, #0]
3fd8: f000 f84e bl 4078 <_malloc_r>
3fdc: bd10 pop {r4, pc}
3fde: 46c0 nop ; (mov r8, r8)
3fe0: 20000004 .word 0x20000004
00003fe4 <_free_r>:
3fe4: b570 push {r4, r5, r6, lr}
3fe6: 0005 movs r5, r0
3fe8: 2900 cmp r1, #0
3fea: d010 beq.n 400e <_free_r+0x2a>
3fec: 1f0c subs r4, r1, #4
3fee: 6823 ldr r3, [r4, #0]
3ff0: 2b00 cmp r3, #0
3ff2: da00 bge.n 3ff6 <_free_r+0x12>
3ff4: 18e4 adds r4, r4, r3
3ff6: 0028 movs r0, r5
3ff8: f000 fc2f bl 485a <__malloc_lock>
3ffc: 4a1d ldr r2, [pc, #116] ; (4074 <_free_r+0x90>)
3ffe: 6813 ldr r3, [r2, #0]
4000: 2b00 cmp r3, #0
4002: d105 bne.n 4010 <_free_r+0x2c>
4004: 6063 str r3, [r4, #4]
4006: 6014 str r4, [r2, #0]
4008: 0028 movs r0, r5
400a: f000 fc27 bl 485c <__malloc_unlock>
400e: bd70 pop {r4, r5, r6, pc}
4010: 42a3 cmp r3, r4
4012: d909 bls.n 4028 <_free_r+0x44>
4014: 6821 ldr r1, [r4, #0]
4016: 1860 adds r0, r4, r1
4018: 4283 cmp r3, r0
401a: d1f3 bne.n 4004 <_free_r+0x20>
401c: 6818 ldr r0, [r3, #0]
401e: 685b ldr r3, [r3, #4]
4020: 1841 adds r1, r0, r1
4022: 6021 str r1, [r4, #0]
4024: e7ee b.n 4004 <_free_r+0x20>
4026: 0013 movs r3, r2
4028: 685a ldr r2, [r3, #4]
402a: 2a00 cmp r2, #0
402c: d001 beq.n 4032 <_free_r+0x4e>
402e: 42a2 cmp r2, r4
4030: d9f9 bls.n 4026 <_free_r+0x42>
4032: 6819 ldr r1, [r3, #0]
4034: 1858 adds r0, r3, r1
4036: 42a0 cmp r0, r4
4038: d10b bne.n 4052 <_free_r+0x6e>
403a: 6820 ldr r0, [r4, #0]
403c: 1809 adds r1, r1, r0
403e: 1858 adds r0, r3, r1
4040: 6019 str r1, [r3, #0]
4042: 4282 cmp r2, r0
4044: d1e0 bne.n 4008 <_free_r+0x24>
4046: 6810 ldr r0, [r2, #0]
4048: 6852 ldr r2, [r2, #4]
404a: 1841 adds r1, r0, r1
404c: 6019 str r1, [r3, #0]
404e: 605a str r2, [r3, #4]
4050: e7da b.n 4008 <_free_r+0x24>
4052: 42a0 cmp r0, r4
4054: d902 bls.n 405c <_free_r+0x78>
4056: 230c movs r3, #12
4058: 602b str r3, [r5, #0]
405a: e7d5 b.n 4008 <_free_r+0x24>
405c: 6821 ldr r1, [r4, #0]
405e: 1860 adds r0, r4, r1
4060: 4282 cmp r2, r0
4062: d103 bne.n 406c <_free_r+0x88>
4064: 6810 ldr r0, [r2, #0]
4066: 6852 ldr r2, [r2, #4]
4068: 1841 adds r1, r0, r1
406a: 6021 str r1, [r4, #0]
406c: 6062 str r2, [r4, #4]
406e: 605c str r4, [r3, #4]
4070: e7ca b.n 4008 <_free_r+0x24>
4072: 46c0 nop ; (mov r8, r8)
4074: 200000c8 .word 0x200000c8
00004078 <_malloc_r>:
4078: 2303 movs r3, #3
407a: b570 push {r4, r5, r6, lr}
407c: 1ccd adds r5, r1, #3
407e: 439d bics r5, r3
4080: 3508 adds r5, #8
4082: 0006 movs r6, r0
4084: 2d0c cmp r5, #12
4086: d21e bcs.n 40c6 <_malloc_r+0x4e>
4088: 250c movs r5, #12
408a: 42a9 cmp r1, r5
408c: d81d bhi.n 40ca <_malloc_r+0x52>
408e: 0030 movs r0, r6
4090: f000 fbe3 bl 485a <__malloc_lock>
4094: 4a25 ldr r2, [pc, #148] ; (412c <_malloc_r+0xb4>)
4096: 6814 ldr r4, [r2, #0]
4098: 0021 movs r1, r4
409a: 2900 cmp r1, #0
409c: d119 bne.n 40d2 <_malloc_r+0x5a>
409e: 4c24 ldr r4, [pc, #144] ; (4130 <_malloc_r+0xb8>)
40a0: 6823 ldr r3, [r4, #0]
40a2: 2b00 cmp r3, #0
40a4: d103 bne.n 40ae <_malloc_r+0x36>
40a6: 0030 movs r0, r6
40a8: f000 fb10 bl 46cc <_sbrk_r>
40ac: 6020 str r0, [r4, #0]
40ae: 0029 movs r1, r5
40b0: 0030 movs r0, r6
40b2: f000 fb0b bl 46cc <_sbrk_r>
40b6: 1c43 adds r3, r0, #1
40b8: d12c bne.n 4114 <_malloc_r+0x9c>
40ba: 230c movs r3, #12
40bc: 0030 movs r0, r6
40be: 6033 str r3, [r6, #0]
40c0: f000 fbcc bl 485c <__malloc_unlock>
40c4: e003 b.n 40ce <_malloc_r+0x56>
40c6: 2d00 cmp r5, #0
40c8: dadf bge.n 408a <_malloc_r+0x12>
40ca: 230c movs r3, #12
40cc: 6033 str r3, [r6, #0]
40ce: 2000 movs r0, #0
40d0: bd70 pop {r4, r5, r6, pc}
40d2: 680b ldr r3, [r1, #0]
40d4: 1b5b subs r3, r3, r5
40d6: d41a bmi.n 410e <_malloc_r+0x96>
40d8: 2b0b cmp r3, #11
40da: d903 bls.n 40e4 <_malloc_r+0x6c>
40dc: 600b str r3, [r1, #0]
40de: 18cc adds r4, r1, r3
40e0: 6025 str r5, [r4, #0]
40e2: e003 b.n 40ec <_malloc_r+0x74>
40e4: 428c cmp r4, r1
40e6: d10e bne.n 4106 <_malloc_r+0x8e>
40e8: 6863 ldr r3, [r4, #4]
40ea: 6013 str r3, [r2, #0]
40ec: 0030 movs r0, r6
40ee: f000 fbb5 bl 485c <__malloc_unlock>
40f2: 0020 movs r0, r4
40f4: 2207 movs r2, #7
40f6: 300b adds r0, #11
40f8: 1d23 adds r3, r4, #4
40fa: 4390 bics r0, r2
40fc: 1ac3 subs r3, r0, r3
40fe: d0e7 beq.n 40d0 <_malloc_r+0x58>
4100: 425a negs r2, r3
4102: 50e2 str r2, [r4, r3]
4104: e7e4 b.n 40d0 <_malloc_r+0x58>
4106: 684b ldr r3, [r1, #4]
4108: 6063 str r3, [r4, #4]
410a: 000c movs r4, r1
410c: e7ee b.n 40ec <_malloc_r+0x74>
410e: 000c movs r4, r1
4110: 6849 ldr r1, [r1, #4]
4112: e7c2 b.n 409a <_malloc_r+0x22>
4114: 2303 movs r3, #3
4116: 1cc4 adds r4, r0, #3
4118: 439c bics r4, r3
411a: 42a0 cmp r0, r4
411c: d0e0 beq.n 40e0 <_malloc_r+0x68>
411e: 1a21 subs r1, r4, r0
4120: 0030 movs r0, r6
4122: f000 fad3 bl 46cc <_sbrk_r>
4126: 1c43 adds r3, r0, #1
4128: d1da bne.n 40e0 <_malloc_r+0x68>
412a: e7c6 b.n 40ba <_malloc_r+0x42>
412c: 200000c8 .word 0x200000c8
4130: 200000cc .word 0x200000cc
00004134 <__sfputc_r>:
4134: 6893 ldr r3, [r2, #8]
4136: b510 push {r4, lr}
4138: 3b01 subs r3, #1
413a: 6093 str r3, [r2, #8]
413c: 2b00 cmp r3, #0
413e: da05 bge.n 414c <__sfputc_r+0x18>
4140: 6994 ldr r4, [r2, #24]
4142: 42a3 cmp r3, r4
4144: db08 blt.n 4158 <__sfputc_r+0x24>
4146: b2cb uxtb r3, r1
4148: 2b0a cmp r3, #10
414a: d005 beq.n 4158 <__sfputc_r+0x24>
414c: 6813 ldr r3, [r2, #0]
414e: 1c58 adds r0, r3, #1
4150: 6010 str r0, [r2, #0]
4152: 7019 strb r1, [r3, #0]
4154: b2c8 uxtb r0, r1
4156: bd10 pop {r4, pc}
4158: f7ff fc74 bl 3a44 <__swbuf_r>
415c: e7fb b.n 4156 <__sfputc_r+0x22>
0000415e <__sfputs_r>:
415e: b5f8 push {r3, r4, r5, r6, r7, lr}
4160: 0006 movs r6, r0
4162: 000f movs r7, r1
4164: 0014 movs r4, r2
4166: 18d5 adds r5, r2, r3
4168: 42ac cmp r4, r5
416a: d101 bne.n 4170 <__sfputs_r+0x12>
416c: 2000 movs r0, #0
416e: e007 b.n 4180 <__sfputs_r+0x22>
4170: 7821 ldrb r1, [r4, #0]
4172: 003a movs r2, r7
4174: 0030 movs r0, r6
4176: f7ff ffdd bl 4134 <__sfputc_r>
417a: 3401 adds r4, #1
417c: 1c43 adds r3, r0, #1
417e: d1f3 bne.n 4168 <__sfputs_r+0xa>
4180: bdf8 pop {r3, r4, r5, r6, r7, pc}
...
00004184 <_vfiprintf_r>:
4184: b5f0 push {r4, r5, r6, r7, lr}
4186: b09f sub sp, #124 ; 0x7c
4188: 0006 movs r6, r0
418a: 000f movs r7, r1
418c: 0014 movs r4, r2
418e: 9305 str r3, [sp, #20]
4190: 2800 cmp r0, #0
4192: d004 beq.n 419e <_vfiprintf_r+0x1a>
4194: 6983 ldr r3, [r0, #24]
4196: 2b00 cmp r3, #0
4198: d101 bne.n 419e <_vfiprintf_r+0x1a>
419a: f7ff fe17 bl 3dcc <__sinit>
419e: 4b7f ldr r3, [pc, #508] ; (439c <_vfiprintf_r+0x218>)
41a0: 429f cmp r7, r3
41a2: d15c bne.n 425e <_vfiprintf_r+0xda>
41a4: 6877 ldr r7, [r6, #4]
41a6: 89bb ldrh r3, [r7, #12]
41a8: 071b lsls r3, r3, #28
41aa: d562 bpl.n 4272 <_vfiprintf_r+0xee>
41ac: 693b ldr r3, [r7, #16]
41ae: 2b00 cmp r3, #0
41b0: d05f beq.n 4272 <_vfiprintf_r+0xee>
41b2: 2300 movs r3, #0
41b4: ad06 add r5, sp, #24
41b6: 616b str r3, [r5, #20]
41b8: 3320 adds r3, #32
41ba: 766b strb r3, [r5, #25]
41bc: 3310 adds r3, #16
41be: 76ab strb r3, [r5, #26]
41c0: 9402 str r4, [sp, #8]
41c2: 9c02 ldr r4, [sp, #8]
41c4: 7823 ldrb r3, [r4, #0]
41c6: 2b00 cmp r3, #0
41c8: d15d bne.n 4286 <_vfiprintf_r+0x102>
41ca: 9b02 ldr r3, [sp, #8]
41cc: 1ae3 subs r3, r4, r3
41ce: 9304 str r3, [sp, #16]
41d0: d00d beq.n 41ee <_vfiprintf_r+0x6a>
41d2: 9b04 ldr r3, [sp, #16]
41d4: 9a02 ldr r2, [sp, #8]
41d6: 0039 movs r1, r7
41d8: 0030 movs r0, r6
41da: f7ff ffc0 bl 415e <__sfputs_r>
41de: 1c43 adds r3, r0, #1
41e0: d100 bne.n 41e4 <_vfiprintf_r+0x60>
41e2: e0cc b.n 437e <_vfiprintf_r+0x1fa>
41e4: 696a ldr r2, [r5, #20]
41e6: 9b04 ldr r3, [sp, #16]
41e8: 4694 mov ip, r2
41ea: 4463 add r3, ip
41ec: 616b str r3, [r5, #20]
41ee: 7823 ldrb r3, [r4, #0]
41f0: 2b00 cmp r3, #0
41f2: d100 bne.n 41f6 <_vfiprintf_r+0x72>
41f4: e0c3 b.n 437e <_vfiprintf_r+0x1fa>
41f6: 2201 movs r2, #1
41f8: 2300 movs r3, #0
41fa: 4252 negs r2, r2
41fc: 606a str r2, [r5, #4]
41fe: a902 add r1, sp, #8
4200: 3254 adds r2, #84 ; 0x54
4202: 1852 adds r2, r2, r1
4204: 3401 adds r4, #1
4206: 602b str r3, [r5, #0]
4208: 60eb str r3, [r5, #12]
420a: 60ab str r3, [r5, #8]
420c: 7013 strb r3, [r2, #0]
420e: 65ab str r3, [r5, #88] ; 0x58
4210: 7821 ldrb r1, [r4, #0]
4212: 2205 movs r2, #5
4214: 4862 ldr r0, [pc, #392] ; (43a0 <_vfiprintf_r+0x21c>)
4216: f000 fb15 bl 4844 <memchr>
421a: 1c63 adds r3, r4, #1
421c: 469c mov ip, r3
421e: 2800 cmp r0, #0
4220: d135 bne.n 428e <_vfiprintf_r+0x10a>
4222: 6829 ldr r1, [r5, #0]
4224: 06cb lsls r3, r1, #27
4226: d504 bpl.n 4232 <_vfiprintf_r+0xae>
4228: 2353 movs r3, #83 ; 0x53
422a: aa02 add r2, sp, #8
422c: 3020 adds r0, #32
422e: 189b adds r3, r3, r2
4230: 7018 strb r0, [r3, #0]
4232: 070b lsls r3, r1, #28
4234: d504 bpl.n 4240 <_vfiprintf_r+0xbc>
4236: 2353 movs r3, #83 ; 0x53
4238: 202b movs r0, #43 ; 0x2b
423a: aa02 add r2, sp, #8
423c: 189b adds r3, r3, r2
423e: 7018 strb r0, [r3, #0]
4240: 7823 ldrb r3, [r4, #0]
4242: 2b2a cmp r3, #42 ; 0x2a
4244: d02c beq.n 42a0 <_vfiprintf_r+0x11c>
4246: 2000 movs r0, #0
4248: 210a movs r1, #10
424a: 9b09 ldr r3, [sp, #36] ; 0x24
424c: 7822 ldrb r2, [r4, #0]
424e: 3a30 subs r2, #48 ; 0x30
4250: 2a09 cmp r2, #9
4252: d800 bhi.n 4256 <_vfiprintf_r+0xd2>
4254: e06b b.n 432e <_vfiprintf_r+0x1aa>
4256: 2800 cmp r0, #0
4258: d02a beq.n 42b0 <_vfiprintf_r+0x12c>
425a: 9309 str r3, [sp, #36] ; 0x24
425c: e028 b.n 42b0 <_vfiprintf_r+0x12c>
425e: 4b51 ldr r3, [pc, #324] ; (43a4 <_vfiprintf_r+0x220>)
4260: 429f cmp r7, r3
4262: d101 bne.n 4268 <_vfiprintf_r+0xe4>
4264: 68b7 ldr r7, [r6, #8]
4266: e79e b.n 41a6 <_vfiprintf_r+0x22>
4268: 4b4f ldr r3, [pc, #316] ; (43a8 <_vfiprintf_r+0x224>)
426a: 429f cmp r7, r3
426c: d19b bne.n 41a6 <_vfiprintf_r+0x22>
426e: 68f7 ldr r7, [r6, #12]
4270: e799 b.n 41a6 <_vfiprintf_r+0x22>
4272: 0039 movs r1, r7
4274: 0030 movs r0, r6
4276: f7ff fc3b bl 3af0 <__swsetup_r>
427a: 2800 cmp r0, #0
427c: d099 beq.n 41b2 <_vfiprintf_r+0x2e>
427e: 2001 movs r0, #1
4280: 4240 negs r0, r0
4282: b01f add sp, #124 ; 0x7c
4284: bdf0 pop {r4, r5, r6, r7, pc}
4286: 2b25 cmp r3, #37 ; 0x25
4288: d09f beq.n 41ca <_vfiprintf_r+0x46>
428a: 3401 adds r4, #1
428c: e79a b.n 41c4 <_vfiprintf_r+0x40>
428e: 4b44 ldr r3, [pc, #272] ; (43a0 <_vfiprintf_r+0x21c>)
4290: 6829 ldr r1, [r5, #0]
4292: 1ac0 subs r0, r0, r3
4294: 2301 movs r3, #1
4296: 4083 lsls r3, r0
4298: 430b orrs r3, r1
429a: 602b str r3, [r5, #0]
429c: 4664 mov r4, ip
429e: e7b7 b.n 4210 <_vfiprintf_r+0x8c>
42a0: 9b05 ldr r3, [sp, #20]
42a2: 1d18 adds r0, r3, #4
42a4: 681b ldr r3, [r3, #0]
42a6: 9005 str r0, [sp, #20]
42a8: 2b00 cmp r3, #0
42aa: db3a blt.n 4322 <_vfiprintf_r+0x19e>
42ac: 9309 str r3, [sp, #36] ; 0x24
42ae: 4664 mov r4, ip
42b0: 7823 ldrb r3, [r4, #0]
42b2: 2b2e cmp r3, #46 ; 0x2e
42b4: d10b bne.n 42ce <_vfiprintf_r+0x14a>
42b6: 7863 ldrb r3, [r4, #1]
42b8: 1c62 adds r2, r4, #1
42ba: 2b2a cmp r3, #42 ; 0x2a
42bc: d13f bne.n 433e <_vfiprintf_r+0x1ba>
42be: 9b05 ldr r3, [sp, #20]
42c0: 3402 adds r4, #2
42c2: 1d1a adds r2, r3, #4
42c4: 681b ldr r3, [r3, #0]
42c6: 9205 str r2, [sp, #20]
42c8: 2b00 cmp r3, #0
42ca: db35 blt.n 4338 <_vfiprintf_r+0x1b4>
42cc: 9307 str r3, [sp, #28]
42ce: 7821 ldrb r1, [r4, #0]
42d0: 2203 movs r2, #3
42d2: 4836 ldr r0, [pc, #216] ; (43ac <_vfiprintf_r+0x228>)
42d4: f000 fab6 bl 4844 <memchr>
42d8: 2800 cmp r0, #0
42da: d007 beq.n 42ec <_vfiprintf_r+0x168>
42dc: 4b33 ldr r3, [pc, #204] ; (43ac <_vfiprintf_r+0x228>)
42de: 682a ldr r2, [r5, #0]
42e0: 1ac0 subs r0, r0, r3
42e2: 2340 movs r3, #64 ; 0x40
42e4: 4083 lsls r3, r0
42e6: 4313 orrs r3, r2
42e8: 602b str r3, [r5, #0]
42ea: 3401 adds r4, #1
42ec: 7821 ldrb r1, [r4, #0]
42ee: 1c63 adds r3, r4, #1
42f0: 2206 movs r2, #6
42f2: 482f ldr r0, [pc, #188] ; (43b0 <_vfiprintf_r+0x22c>)
42f4: 9302 str r3, [sp, #8]
42f6: 7629 strb r1, [r5, #24]
42f8: f000 faa4 bl 4844 <memchr>
42fc: 2800 cmp r0, #0
42fe: d044 beq.n 438a <_vfiprintf_r+0x206>
4300: 4b2c ldr r3, [pc, #176] ; (43b4 <_vfiprintf_r+0x230>)
4302: 2b00 cmp r3, #0
4304: d12f bne.n 4366 <_vfiprintf_r+0x1e2>
4306: 6829 ldr r1, [r5, #0]
4308: 9b05 ldr r3, [sp, #20]
430a: 2207 movs r2, #7
430c: 05c9 lsls r1, r1, #23
430e: d528 bpl.n 4362 <_vfiprintf_r+0x1de>
4310: 189b adds r3, r3, r2
4312: 4393 bics r3, r2
4314: 3308 adds r3, #8
4316: 9305 str r3, [sp, #20]
4318: 696b ldr r3, [r5, #20]
431a: 9a03 ldr r2, [sp, #12]
431c: 189b adds r3, r3, r2
431e: 616b str r3, [r5, #20]
4320: e74f b.n 41c2 <_vfiprintf_r+0x3e>
4322: 425b negs r3, r3
4324: 60eb str r3, [r5, #12]
4326: 2302 movs r3, #2
4328: 430b orrs r3, r1
432a: 602b str r3, [r5, #0]
432c: e7bf b.n 42ae <_vfiprintf_r+0x12a>
432e: 434b muls r3, r1
4330: 3401 adds r4, #1
4332: 189b adds r3, r3, r2
4334: 2001 movs r0, #1
4336: e789 b.n 424c <_vfiprintf_r+0xc8>
4338: 2301 movs r3, #1
433a: 425b negs r3, r3
433c: e7c6 b.n 42cc <_vfiprintf_r+0x148>
433e: 2300 movs r3, #0
4340: 0014 movs r4, r2
4342: 200a movs r0, #10
4344: 001a movs r2, r3
4346: 606b str r3, [r5, #4]
4348: 7821 ldrb r1, [r4, #0]
434a: 3930 subs r1, #48 ; 0x30
434c: 2909 cmp r1, #9
434e: d903 bls.n 4358 <_vfiprintf_r+0x1d4>
4350: 2b00 cmp r3, #0
4352: d0bc beq.n 42ce <_vfiprintf_r+0x14a>
4354: 9207 str r2, [sp, #28]
4356: e7ba b.n 42ce <_vfiprintf_r+0x14a>
4358: 4342 muls r2, r0
435a: 3401 adds r4, #1
435c: 1852 adds r2, r2, r1
435e: 2301 movs r3, #1
4360: e7f2 b.n 4348 <_vfiprintf_r+0x1c4>
4362: 3307 adds r3, #7
4364: e7d5 b.n 4312 <_vfiprintf_r+0x18e>
4366: ab05 add r3, sp, #20
4368: 9300 str r3, [sp, #0]
436a: 003a movs r2, r7
436c: 4b12 ldr r3, [pc, #72] ; (43b8 <_vfiprintf_r+0x234>)
436e: 0029 movs r1, r5
4370: 0030 movs r0, r6
4372: e000 b.n 4376 <_vfiprintf_r+0x1f2>
4374: bf00 nop
4376: 9003 str r0, [sp, #12]
4378: 9b03 ldr r3, [sp, #12]
437a: 3301 adds r3, #1
437c: d1cc bne.n 4318 <_vfiprintf_r+0x194>
437e: 89bb ldrh r3, [r7, #12]
4380: 065b lsls r3, r3, #25
4382: d500 bpl.n 4386 <_vfiprintf_r+0x202>
4384: e77b b.n 427e <_vfiprintf_r+0xfa>
4386: 980b ldr r0, [sp, #44] ; 0x2c
4388: e77b b.n 4282 <_vfiprintf_r+0xfe>
438a: ab05 add r3, sp, #20
438c: 9300 str r3, [sp, #0]
438e: 003a movs r2, r7
4390: 4b09 ldr r3, [pc, #36] ; (43b8 <_vfiprintf_r+0x234>)
4392: 0029 movs r1, r5
4394: 0030 movs r0, r6
4396: f000 f87f bl 4498 <_printf_i>
439a: e7ec b.n 4376 <_vfiprintf_r+0x1f2>
439c: 000049ac .word 0x000049ac
43a0: 000049ec .word 0x000049ec
43a4: 000049cc .word 0x000049cc
43a8: 0000498c .word 0x0000498c
43ac: 000049f2 .word 0x000049f2
43b0: 000049f6 .word 0x000049f6
43b4: 00000000 .word 0x00000000
43b8: 0000415f .word 0x0000415f
000043bc <_printf_common>:
43bc: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
43be: 0015 movs r5, r2
43c0: 9301 str r3, [sp, #4]
43c2: 688a ldr r2, [r1, #8]
43c4: 690b ldr r3, [r1, #16]
43c6: 9000 str r0, [sp, #0]
43c8: 000c movs r4, r1
43ca: 4293 cmp r3, r2
43cc: da00 bge.n 43d0 <_printf_common+0x14>
43ce: 0013 movs r3, r2
43d0: 0022 movs r2, r4
43d2: 602b str r3, [r5, #0]
43d4: 3243 adds r2, #67 ; 0x43
43d6: 7812 ldrb r2, [r2, #0]
43d8: 2a00 cmp r2, #0
43da: d001 beq.n 43e0 <_printf_common+0x24>
43dc: 3301 adds r3, #1
43de: 602b str r3, [r5, #0]
43e0: 6823 ldr r3, [r4, #0]
43e2: 069b lsls r3, r3, #26
43e4: d502 bpl.n 43ec <_printf_common+0x30>
43e6: 682b ldr r3, [r5, #0]
43e8: 3302 adds r3, #2
43ea: 602b str r3, [r5, #0]
43ec: 2706 movs r7, #6
43ee: 6823 ldr r3, [r4, #0]
43f0: 401f ands r7, r3
43f2: d027 beq.n 4444 <_printf_common+0x88>
43f4: 0023 movs r3, r4
43f6: 3343 adds r3, #67 ; 0x43
43f8: 781b ldrb r3, [r3, #0]
43fa: 1e5a subs r2, r3, #1
43fc: 4193 sbcs r3, r2
43fe: 6822 ldr r2, [r4, #0]
4400: 0692 lsls r2, r2, #26
4402: d430 bmi.n 4466 <_printf_common+0xaa>
4404: 0022 movs r2, r4
4406: 9901 ldr r1, [sp, #4]
4408: 3243 adds r2, #67 ; 0x43
440a: 9800 ldr r0, [sp, #0]
440c: 9e08 ldr r6, [sp, #32]
440e: 47b0 blx r6
4410: 1c43 adds r3, r0, #1
4412: d025 beq.n 4460 <_printf_common+0xa4>
4414: 2306 movs r3, #6
4416: 6820 ldr r0, [r4, #0]
4418: 682a ldr r2, [r5, #0]
441a: 68e1 ldr r1, [r4, #12]
441c: 4003 ands r3, r0
441e: 2500 movs r5, #0
4420: 2b04 cmp r3, #4
4422: d103 bne.n 442c <_printf_common+0x70>
4424: 1a8d subs r5, r1, r2
4426: 43eb mvns r3, r5
4428: 17db asrs r3, r3, #31
442a: 401d ands r5, r3
442c: 68a3 ldr r3, [r4, #8]
442e: 6922 ldr r2, [r4, #16]
4430: 4293 cmp r3, r2
4432: dd01 ble.n 4438 <_printf_common+0x7c>
4434: 1a9b subs r3, r3, r2
4436: 18ed adds r5, r5, r3
4438: 2700 movs r7, #0
443a: 42bd cmp r5, r7
443c: d120 bne.n 4480 <_printf_common+0xc4>
443e: 2000 movs r0, #0
4440: e010 b.n 4464 <_printf_common+0xa8>
4442: 3701 adds r7, #1
4444: 68e3 ldr r3, [r4, #12]
4446: 682a ldr r2, [r5, #0]
4448: 1a9b subs r3, r3, r2
444a: 429f cmp r7, r3
444c: dad2 bge.n 43f4 <_printf_common+0x38>
444e: 0022 movs r2, r4
4450: 2301 movs r3, #1
4452: 3219 adds r2, #25
4454: 9901 ldr r1, [sp, #4]
4456: 9800 ldr r0, [sp, #0]
4458: 9e08 ldr r6, [sp, #32]
445a: 47b0 blx r6
445c: 1c43 adds r3, r0, #1
445e: d1f0 bne.n 4442 <_printf_common+0x86>
4460: 2001 movs r0, #1
4462: 4240 negs r0, r0
4464: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
4466: 2030 movs r0, #48 ; 0x30
4468: 18e1 adds r1, r4, r3
446a: 3143 adds r1, #67 ; 0x43
446c: 7008 strb r0, [r1, #0]
446e: 0021 movs r1, r4
4470: 1c5a adds r2, r3, #1
4472: 3145 adds r1, #69 ; 0x45
4474: 7809 ldrb r1, [r1, #0]
4476: 18a2 adds r2, r4, r2
4478: 3243 adds r2, #67 ; 0x43
447a: 3302 adds r3, #2
447c: 7011 strb r1, [r2, #0]
447e: e7c1 b.n 4404 <_printf_common+0x48>
4480: 0022 movs r2, r4
4482: 2301 movs r3, #1
4484: 321a adds r2, #26
4486: 9901 ldr r1, [sp, #4]
4488: 9800 ldr r0, [sp, #0]
448a: 9e08 ldr r6, [sp, #32]
448c: 47b0 blx r6
448e: 1c43 adds r3, r0, #1
4490: d0e6 beq.n 4460 <_printf_common+0xa4>
4492: 3701 adds r7, #1
4494: e7d1 b.n 443a <_printf_common+0x7e>
...
00004498 <_printf_i>:
4498: b5f0 push {r4, r5, r6, r7, lr}
449a: b08b sub sp, #44 ; 0x2c
449c: 9206 str r2, [sp, #24]
449e: 000a movs r2, r1
44a0: 3243 adds r2, #67 ; 0x43
44a2: 9307 str r3, [sp, #28]
44a4: 9005 str r0, [sp, #20]
44a6: 9204 str r2, [sp, #16]
44a8: 7e0a ldrb r2, [r1, #24]
44aa: 000c movs r4, r1
44ac: 9b10 ldr r3, [sp, #64] ; 0x40
44ae: 2a6e cmp r2, #110 ; 0x6e
44b0: d100 bne.n 44b4 <_printf_i+0x1c>
44b2: e08f b.n 45d4 <_printf_i+0x13c>
44b4: d817 bhi.n 44e6 <_printf_i+0x4e>
44b6: 2a63 cmp r2, #99 ; 0x63
44b8: d02c beq.n 4514 <_printf_i+0x7c>
44ba: d808 bhi.n 44ce <_printf_i+0x36>
44bc: 2a00 cmp r2, #0
44be: d100 bne.n 44c2 <_printf_i+0x2a>
44c0: e099 b.n 45f6 <_printf_i+0x15e>
44c2: 2a58 cmp r2, #88 ; 0x58
44c4: d054 beq.n 4570 <_printf_i+0xd8>
44c6: 0026 movs r6, r4
44c8: 3642 adds r6, #66 ; 0x42
44ca: 7032 strb r2, [r6, #0]
44cc: e029 b.n 4522 <_printf_i+0x8a>
44ce: 2a64 cmp r2, #100 ; 0x64
44d0: d001 beq.n 44d6 <_printf_i+0x3e>
44d2: 2a69 cmp r2, #105 ; 0x69
44d4: d1f7 bne.n 44c6 <_printf_i+0x2e>
44d6: 6821 ldr r1, [r4, #0]
44d8: 681a ldr r2, [r3, #0]
44da: 0608 lsls r0, r1, #24
44dc: d523 bpl.n 4526 <_printf_i+0x8e>
44de: 1d11 adds r1, r2, #4
44e0: 6019 str r1, [r3, #0]
44e2: 6815 ldr r5, [r2, #0]
44e4: e025 b.n 4532 <_printf_i+0x9a>
44e6: 2a73 cmp r2, #115 ; 0x73
44e8: d100 bne.n 44ec <_printf_i+0x54>
44ea: e088 b.n 45fe <_printf_i+0x166>
44ec: d808 bhi.n 4500 <_printf_i+0x68>
44ee: 2a6f cmp r2, #111 ; 0x6f
44f0: d029 beq.n 4546 <_printf_i+0xae>
44f2: 2a70 cmp r2, #112 ; 0x70
44f4: d1e7 bne.n 44c6 <_printf_i+0x2e>
44f6: 2220 movs r2, #32
44f8: 6809 ldr r1, [r1, #0]
44fa: 430a orrs r2, r1
44fc: 6022 str r2, [r4, #0]
44fe: e003 b.n 4508 <_printf_i+0x70>
4500: 2a75 cmp r2, #117 ; 0x75
4502: d020 beq.n 4546 <_printf_i+0xae>
4504: 2a78 cmp r2, #120 ; 0x78
4506: d1de bne.n 44c6 <_printf_i+0x2e>
4508: 0022 movs r2, r4
450a: 2178 movs r1, #120 ; 0x78
450c: 3245 adds r2, #69 ; 0x45
450e: 7011 strb r1, [r2, #0]
4510: 4a6c ldr r2, [pc, #432] ; (46c4 <_printf_i+0x22c>)
4512: e030 b.n 4576 <_printf_i+0xde>
4514: 000e movs r6, r1
4516: 681a ldr r2, [r3, #0]
4518: 3642 adds r6, #66 ; 0x42
451a: 1d11 adds r1, r2, #4
451c: 6019 str r1, [r3, #0]
451e: 6813 ldr r3, [r2, #0]
4520: 7033 strb r3, [r6, #0]
4522: 2301 movs r3, #1
4524: e079 b.n 461a <_printf_i+0x182>
4526: 0649 lsls r1, r1, #25
4528: d5d9 bpl.n 44de <_printf_i+0x46>
452a: 1d11 adds r1, r2, #4
452c: 6019 str r1, [r3, #0]
452e: 2300 movs r3, #0
4530: 5ed5 ldrsh r5, [r2, r3]
4532: 2d00 cmp r5, #0
4534: da03 bge.n 453e <_printf_i+0xa6>
4536: 232d movs r3, #45 ; 0x2d
4538: 9a04 ldr r2, [sp, #16]
453a: 426d negs r5, r5
453c: 7013 strb r3, [r2, #0]
453e: 4b62 ldr r3, [pc, #392] ; (46c8 <_printf_i+0x230>)
4540: 270a movs r7, #10
4542: 9303 str r3, [sp, #12]
4544: e02f b.n 45a6 <_printf_i+0x10e>
4546: 6820 ldr r0, [r4, #0]
4548: 6819 ldr r1, [r3, #0]
454a: 0605 lsls r5, r0, #24
454c: d503 bpl.n 4556 <_printf_i+0xbe>
454e: 1d08 adds r0, r1, #4
4550: 6018 str r0, [r3, #0]
4552: 680d ldr r5, [r1, #0]
4554: e005 b.n 4562 <_printf_i+0xca>
4556: 0640 lsls r0, r0, #25
4558: d5f9 bpl.n 454e <_printf_i+0xb6>
455a: 680d ldr r5, [r1, #0]
455c: 1d08 adds r0, r1, #4
455e: 6018 str r0, [r3, #0]
4560: b2ad uxth r5, r5
4562: 4b59 ldr r3, [pc, #356] ; (46c8 <_printf_i+0x230>)
4564: 2708 movs r7, #8
4566: 9303 str r3, [sp, #12]
4568: 2a6f cmp r2, #111 ; 0x6f
456a: d018 beq.n 459e <_printf_i+0x106>
456c: 270a movs r7, #10
456e: e016 b.n 459e <_printf_i+0x106>
4570: 3145 adds r1, #69 ; 0x45
4572: 700a strb r2, [r1, #0]
4574: 4a54 ldr r2, [pc, #336] ; (46c8 <_printf_i+0x230>)
4576: 9203 str r2, [sp, #12]
4578: 681a ldr r2, [r3, #0]
457a: 6821 ldr r1, [r4, #0]
457c: 1d10 adds r0, r2, #4
457e: 6018 str r0, [r3, #0]
4580: 6815 ldr r5, [r2, #0]
4582: 0608 lsls r0, r1, #24
4584: d522 bpl.n 45cc <_printf_i+0x134>
4586: 07cb lsls r3, r1, #31
4588: d502 bpl.n 4590 <_printf_i+0xf8>
458a: 2320 movs r3, #32
458c: 4319 orrs r1, r3
458e: 6021 str r1, [r4, #0]
4590: 2710 movs r7, #16
4592: 2d00 cmp r5, #0
4594: d103 bne.n 459e <_printf_i+0x106>
4596: 2320 movs r3, #32
4598: 6822 ldr r2, [r4, #0]
459a: 439a bics r2, r3
459c: 6022 str r2, [r4, #0]
459e: 0023 movs r3, r4
45a0: 2200 movs r2, #0
45a2: 3343 adds r3, #67 ; 0x43
45a4: 701a strb r2, [r3, #0]
45a6: 6863 ldr r3, [r4, #4]
45a8: 60a3 str r3, [r4, #8]
45aa: 2b00 cmp r3, #0
45ac: db5c blt.n 4668 <_printf_i+0x1d0>
45ae: 2204 movs r2, #4
45b0: 6821 ldr r1, [r4, #0]
45b2: 4391 bics r1, r2
45b4: 6021 str r1, [r4, #0]
45b6: 2d00 cmp r5, #0
45b8: d158 bne.n 466c <_printf_i+0x1d4>
45ba: 9e04 ldr r6, [sp, #16]
45bc: 2b00 cmp r3, #0
45be: d064 beq.n 468a <_printf_i+0x1f2>
45c0: 0026 movs r6, r4
45c2: 9b03 ldr r3, [sp, #12]
45c4: 3642 adds r6, #66 ; 0x42
45c6: 781b ldrb r3, [r3, #0]
45c8: 7033 strb r3, [r6, #0]
45ca: e05e b.n 468a <_printf_i+0x1f2>
45cc: 0648 lsls r0, r1, #25
45ce: d5da bpl.n 4586 <_printf_i+0xee>
45d0: b2ad uxth r5, r5
45d2: e7d8 b.n 4586 <_printf_i+0xee>
45d4: 6809 ldr r1, [r1, #0]
45d6: 681a ldr r2, [r3, #0]
45d8: 0608 lsls r0, r1, #24
45da: d505 bpl.n 45e8 <_printf_i+0x150>
45dc: 1d11 adds r1, r2, #4
45de: 6019 str r1, [r3, #0]
45e0: 6813 ldr r3, [r2, #0]
45e2: 6962 ldr r2, [r4, #20]
45e4: 601a str r2, [r3, #0]
45e6: e006 b.n 45f6 <_printf_i+0x15e>
45e8: 0649 lsls r1, r1, #25
45ea: d5f7 bpl.n 45dc <_printf_i+0x144>
45ec: 1d11 adds r1, r2, #4
45ee: 6019 str r1, [r3, #0]
45f0: 6813 ldr r3, [r2, #0]
45f2: 8aa2 ldrh r2, [r4, #20]
45f4: 801a strh r2, [r3, #0]
45f6: 2300 movs r3, #0
45f8: 9e04 ldr r6, [sp, #16]
45fa: 6123 str r3, [r4, #16]
45fc: e054 b.n 46a8 <_printf_i+0x210>
45fe: 681a ldr r2, [r3, #0]
4600: 1d11 adds r1, r2, #4
4602: 6019 str r1, [r3, #0]
4604: 6816 ldr r6, [r2, #0]
4606: 2100 movs r1, #0
4608: 6862 ldr r2, [r4, #4]
460a: 0030 movs r0, r6
460c: f000 f91a bl 4844 <memchr>
4610: 2800 cmp r0, #0
4612: d001 beq.n 4618 <_printf_i+0x180>
4614: 1b80 subs r0, r0, r6
4616: 6060 str r0, [r4, #4]
4618: 6863 ldr r3, [r4, #4]
461a: 6123 str r3, [r4, #16]
461c: 2300 movs r3, #0
461e: 9a04 ldr r2, [sp, #16]
4620: 7013 strb r3, [r2, #0]
4622: e041 b.n 46a8 <_printf_i+0x210>
4624: 6923 ldr r3, [r4, #16]
4626: 0032 movs r2, r6
4628: 9906 ldr r1, [sp, #24]
462a: 9805 ldr r0, [sp, #20]
462c: 9d07 ldr r5, [sp, #28]
462e: 47a8 blx r5
4630: 1c43 adds r3, r0, #1
4632: d043 beq.n 46bc <_printf_i+0x224>
4634: 6823 ldr r3, [r4, #0]
4636: 2500 movs r5, #0
4638: 079b lsls r3, r3, #30
463a: d40f bmi.n 465c <_printf_i+0x1c4>
463c: 9b09 ldr r3, [sp, #36] ; 0x24
463e: 68e0 ldr r0, [r4, #12]
4640: 4298 cmp r0, r3
4642: da3d bge.n 46c0 <_printf_i+0x228>
4644: 0018 movs r0, r3
4646: e03b b.n 46c0 <_printf_i+0x228>
4648: 0022 movs r2, r4
464a: 2301 movs r3, #1
464c: 3219 adds r2, #25
464e: 9906 ldr r1, [sp, #24]
4650: 9805 ldr r0, [sp, #20]
4652: 9e07 ldr r6, [sp, #28]
4654: 47b0 blx r6
4656: 1c43 adds r3, r0, #1
4658: d030 beq.n 46bc <_printf_i+0x224>
465a: 3501 adds r5, #1
465c: 68e3 ldr r3, [r4, #12]
465e: 9a09 ldr r2, [sp, #36] ; 0x24
4660: 1a9b subs r3, r3, r2
4662: 429d cmp r5, r3
4664: dbf0 blt.n 4648 <_printf_i+0x1b0>
4666: e7e9 b.n 463c <_printf_i+0x1a4>
4668: 2d00 cmp r5, #0
466a: d0a9 beq.n 45c0 <_printf_i+0x128>
466c: 9e04 ldr r6, [sp, #16]
466e: 0028 movs r0, r5
4670: 0039 movs r1, r7
4672: f7fd fbed bl 1e50 <__aeabi_uidivmod>
4676: 9b03 ldr r3, [sp, #12]
4678: 3e01 subs r6, #1
467a: 5c5b ldrb r3, [r3, r1]
467c: 0028 movs r0, r5
467e: 7033 strb r3, [r6, #0]
4680: 0039 movs r1, r7
4682: f7fd fb5f bl 1d44 <__udivsi3>
4686: 1e05 subs r5, r0, #0
4688: d1f1 bne.n 466e <_printf_i+0x1d6>
468a: 2f08 cmp r7, #8
468c: d109 bne.n 46a2 <_printf_i+0x20a>
468e: 6823 ldr r3, [r4, #0]
4690: 07db lsls r3, r3, #31
4692: d506 bpl.n 46a2 <_printf_i+0x20a>
4694: 6863 ldr r3, [r4, #4]
4696: 6922 ldr r2, [r4, #16]
4698: 4293 cmp r3, r2
469a: dc02 bgt.n 46a2 <_printf_i+0x20a>
469c: 2330 movs r3, #48 ; 0x30
469e: 3e01 subs r6, #1
46a0: 7033 strb r3, [r6, #0]
46a2: 9b04 ldr r3, [sp, #16]
46a4: 1b9b subs r3, r3, r6
46a6: 6123 str r3, [r4, #16]
46a8: 9b07 ldr r3, [sp, #28]
46aa: aa09 add r2, sp, #36 ; 0x24
46ac: 9300 str r3, [sp, #0]
46ae: 0021 movs r1, r4
46b0: 9b06 ldr r3, [sp, #24]
46b2: 9805 ldr r0, [sp, #20]
46b4: f7ff fe82 bl 43bc <_printf_common>
46b8: 1c43 adds r3, r0, #1
46ba: d1b3 bne.n 4624 <_printf_i+0x18c>
46bc: 2001 movs r0, #1
46be: 4240 negs r0, r0
46c0: b00b add sp, #44 ; 0x2c
46c2: bdf0 pop {r4, r5, r6, r7, pc}
46c4: 00004a0e .word 0x00004a0e
46c8: 000049fd .word 0x000049fd
000046cc <_sbrk_r>:
46cc: 2300 movs r3, #0
46ce: b570 push {r4, r5, r6, lr}
46d0: 4c06 ldr r4, [pc, #24] ; (46ec <_sbrk_r+0x20>)
46d2: 0005 movs r5, r0
46d4: 0008 movs r0, r1
46d6: 6023 str r3, [r4, #0]
46d8: f7fd fae8 bl 1cac <_sbrk>
46dc: 1c43 adds r3, r0, #1
46de: d103 bne.n 46e8 <_sbrk_r+0x1c>
46e0: 6823 ldr r3, [r4, #0]
46e2: 2b00 cmp r3, #0
46e4: d000 beq.n 46e8 <_sbrk_r+0x1c>
46e6: 602b str r3, [r5, #0]
46e8: bd70 pop {r4, r5, r6, pc}
46ea: 46c0 nop ; (mov r8, r8)
46ec: 2000025c .word 0x2000025c
000046f0 <__sread>:
46f0: b570 push {r4, r5, r6, lr}
46f2: 000c movs r4, r1
46f4: 250e movs r5, #14
46f6: 5f49 ldrsh r1, [r1, r5]
46f8: f000 f8b2 bl 4860 <_read_r>
46fc: 2800 cmp r0, #0
46fe: db03 blt.n 4708 <__sread+0x18>
4700: 6d63 ldr r3, [r4, #84] ; 0x54
4702: 181b adds r3, r3, r0
4704: 6563 str r3, [r4, #84] ; 0x54
4706: bd70 pop {r4, r5, r6, pc}
4708: 89a3 ldrh r3, [r4, #12]
470a: 4a02 ldr r2, [pc, #8] ; (4714 <__sread+0x24>)
470c: 4013 ands r3, r2
470e: 81a3 strh r3, [r4, #12]
4710: e7f9 b.n 4706 <__sread+0x16>
4712: 46c0 nop ; (mov r8, r8)
4714: ffffefff .word 0xffffefff
00004718 <__swrite>:
4718: b5f8 push {r3, r4, r5, r6, r7, lr}
471a: 001f movs r7, r3
471c: 898b ldrh r3, [r1, #12]
471e: 0005 movs r5, r0
4720: 000c movs r4, r1
4722: 0016 movs r6, r2
4724: 05db lsls r3, r3, #23
4726: d505 bpl.n 4734 <__swrite+0x1c>
4728: 230e movs r3, #14
472a: 5ec9 ldrsh r1, [r1, r3]
472c: 2200 movs r2, #0
472e: 2302 movs r3, #2
4730: f000 f874 bl 481c <_lseek_r>
4734: 89a3 ldrh r3, [r4, #12]
4736: 4a05 ldr r2, [pc, #20] ; (474c <__swrite+0x34>)
4738: 0028 movs r0, r5
473a: 4013 ands r3, r2
473c: 81a3 strh r3, [r4, #12]
473e: 0032 movs r2, r6
4740: 230e movs r3, #14
4742: 5ee1 ldrsh r1, [r4, r3]
4744: 003b movs r3, r7
4746: f000 f81f bl 4788 <_write_r>
474a: bdf8 pop {r3, r4, r5, r6, r7, pc}
474c: ffffefff .word 0xffffefff
00004750 <__sseek>:
4750: b570 push {r4, r5, r6, lr}
4752: 000c movs r4, r1
4754: 250e movs r5, #14
4756: 5f49 ldrsh r1, [r1, r5]
4758: f000 f860 bl 481c <_lseek_r>
475c: 89a3 ldrh r3, [r4, #12]
475e: 1c42 adds r2, r0, #1
4760: d103 bne.n 476a <__sseek+0x1a>
4762: 4a05 ldr r2, [pc, #20] ; (4778 <__sseek+0x28>)
4764: 4013 ands r3, r2
4766: 81a3 strh r3, [r4, #12]
4768: bd70 pop {r4, r5, r6, pc}
476a: 2280 movs r2, #128 ; 0x80
476c: 0152 lsls r2, r2, #5
476e: 4313 orrs r3, r2
4770: 81a3 strh r3, [r4, #12]
4772: 6560 str r0, [r4, #84] ; 0x54
4774: e7f8 b.n 4768 <__sseek+0x18>
4776: 46c0 nop ; (mov r8, r8)
4778: ffffefff .word 0xffffefff
0000477c <__sclose>:
477c: b510 push {r4, lr}
477e: 230e movs r3, #14
4780: 5ec9 ldrsh r1, [r1, r3]
4782: f000 f815 bl 47b0 <_close_r>
4786: bd10 pop {r4, pc}
00004788 <_write_r>:
4788: b570 push {r4, r5, r6, lr}
478a: 0005 movs r5, r0
478c: 0008 movs r0, r1
478e: 0011 movs r1, r2
4790: 2200 movs r2, #0
4792: 4c06 ldr r4, [pc, #24] ; (47ac <_write_r+0x24>)
4794: 6022 str r2, [r4, #0]
4796: 001a movs r2, r3
4798: f7fc f89a bl 8d0 <_write>
479c: 1c43 adds r3, r0, #1
479e: d103 bne.n 47a8 <_write_r+0x20>
47a0: 6823 ldr r3, [r4, #0]
47a2: 2b00 cmp r3, #0
47a4: d000 beq.n 47a8 <_write_r+0x20>
47a6: 602b str r3, [r5, #0]
47a8: bd70 pop {r4, r5, r6, pc}
47aa: 46c0 nop ; (mov r8, r8)
47ac: 2000025c .word 0x2000025c
000047b0 <_close_r>:
47b0: 2300 movs r3, #0
47b2: b570 push {r4, r5, r6, lr}
47b4: 4c06 ldr r4, [pc, #24] ; (47d0 <_close_r+0x20>)
47b6: 0005 movs r5, r0
47b8: 0008 movs r0, r1
47ba: 6023 str r3, [r4, #0]
47bc: f7fd fa88 bl 1cd0 <_close>
47c0: 1c43 adds r3, r0, #1
47c2: d103 bne.n 47cc <_close_r+0x1c>
47c4: 6823 ldr r3, [r4, #0]
47c6: 2b00 cmp r3, #0
47c8: d000 beq.n 47cc <_close_r+0x1c>
47ca: 602b str r3, [r5, #0]
47cc: bd70 pop {r4, r5, r6, pc}
47ce: 46c0 nop ; (mov r8, r8)
47d0: 2000025c .word 0x2000025c
000047d4 <_fstat_r>:
47d4: 2300 movs r3, #0
47d6: b570 push {r4, r5, r6, lr}
47d8: 4c06 ldr r4, [pc, #24] ; (47f4 <_fstat_r+0x20>)
47da: 0005 movs r5, r0
47dc: 0008 movs r0, r1
47de: 0011 movs r1, r2
47e0: 6023 str r3, [r4, #0]
47e2: f7fd fa78 bl 1cd6 <_fstat>
47e6: 1c43 adds r3, r0, #1
47e8: d103 bne.n 47f2 <_fstat_r+0x1e>
47ea: 6823 ldr r3, [r4, #0]
47ec: 2b00 cmp r3, #0
47ee: d000 beq.n 47f2 <_fstat_r+0x1e>
47f0: 602b str r3, [r5, #0]
47f2: bd70 pop {r4, r5, r6, pc}
47f4: 2000025c .word 0x2000025c
000047f8 <_isatty_r>:
47f8: 2300 movs r3, #0
47fa: b570 push {r4, r5, r6, lr}
47fc: 4c06 ldr r4, [pc, #24] ; (4818 <_isatty_r+0x20>)
47fe: 0005 movs r5, r0
4800: 0008 movs r0, r1
4802: 6023 str r3, [r4, #0]
4804: f7fd fa6c bl 1ce0 <_isatty>
4808: 1c43 adds r3, r0, #1
480a: d103 bne.n 4814 <_isatty_r+0x1c>
480c: 6823 ldr r3, [r4, #0]
480e: 2b00 cmp r3, #0
4810: d000 beq.n 4814 <_isatty_r+0x1c>
4812: 602b str r3, [r5, #0]
4814: bd70 pop {r4, r5, r6, pc}
4816: 46c0 nop ; (mov r8, r8)
4818: 2000025c .word 0x2000025c
0000481c <_lseek_r>:
481c: b570 push {r4, r5, r6, lr}
481e: 0005 movs r5, r0
4820: 0008 movs r0, r1
4822: 0011 movs r1, r2
4824: 2200 movs r2, #0
4826: 4c06 ldr r4, [pc, #24] ; (4840 <_lseek_r+0x24>)
4828: 6022 str r2, [r4, #0]
482a: 001a movs r2, r3
482c: f7fd fa5a bl 1ce4 <_lseek>
4830: 1c43 adds r3, r0, #1
4832: d103 bne.n 483c <_lseek_r+0x20>
4834: 6823 ldr r3, [r4, #0]
4836: 2b00 cmp r3, #0
4838: d000 beq.n 483c <_lseek_r+0x20>
483a: 602b str r3, [r5, #0]
483c: bd70 pop {r4, r5, r6, pc}
483e: 46c0 nop ; (mov r8, r8)
4840: 2000025c .word 0x2000025c
00004844 <memchr>:
4844: b2c9 uxtb r1, r1
4846: 1882 adds r2, r0, r2
4848: 4290 cmp r0, r2
484a: d101 bne.n 4850 <memchr+0xc>
484c: 2000 movs r0, #0
484e: 4770 bx lr
4850: 7803 ldrb r3, [r0, #0]
4852: 428b cmp r3, r1
4854: d0fb beq.n 484e <memchr+0xa>
4856: 3001 adds r0, #1
4858: e7f6 b.n 4848 <memchr+0x4>
0000485a <__malloc_lock>:
485a: 4770 bx lr
0000485c <__malloc_unlock>:
485c: 4770 bx lr
...
00004860 <_read_r>:
4860: b570 push {r4, r5, r6, lr}
4862: 0005 movs r5, r0
4864: 0008 movs r0, r1
4866: 0011 movs r1, r2
4868: 2200 movs r2, #0
486a: 4c06 ldr r4, [pc, #24] ; (4884 <_read_r+0x24>)
486c: 6022 str r2, [r4, #0]
486e: 001a movs r2, r3
4870: f7fc f80c bl 88c <_read>
4874: 1c43 adds r3, r0, #1
4876: d103 bne.n 4880 <_read_r+0x20>
4878: 6823 ldr r3, [r4, #0]
487a: 2b00 cmp r3, #0
487c: d000 beq.n 4880 <_read_r+0x20>
487e: 602b str r3, [r5, #0]
4880: bd70 pop {r4, r5, r6, pc}
4882: 46c0 nop ; (mov r8, r8)
4884: 2000025c .word 0x2000025c
4888: 6c6c6548 .word 0x6c6c6548
488c: 6f77206f .word 0x6f77206f
4890: 00646c72 .word 0x00646c72
4894: 42000800 .word 0x42000800
4898: 42000c00 .word 0x42000c00
489c: 42001000 .word 0x42001000
48a0: 42001400 .word 0x42001400
48a4: 42001800 .word 0x42001800
48a8: 42001c00 .word 0x42001c00
48ac: 00001636 .word 0x00001636
48b0: 00001632 .word 0x00001632
48b4: 00001632 .word 0x00001632
48b8: 00001698 .word 0x00001698
48bc: 00001698 .word 0x00001698
48c0: 0000164a .word 0x0000164a
48c4: 0000163c .word 0x0000163c
48c8: 00001650 .word 0x00001650
48cc: 00001686 .word 0x00001686
48d0: 00001720 .word 0x00001720
48d4: 00001700 .word 0x00001700
48d8: 00001700 .word 0x00001700
48dc: 0000178c .word 0x0000178c
48e0: 00001712 .word 0x00001712
48e4: 0000172e .word 0x0000172e
48e8: 00001704 .word 0x00001704
48ec: 0000173c .word 0x0000173c
48f0: 0000177c .word 0x0000177c
48f4: 20433249 .word 0x20433249
48f8: 72646461 .word 0x72646461
48fc: 20737365 .word 0x20737365
4900: 30257830 .word 0x30257830
4904: 000a7832 .word 0x000a7832
4908: 000026c8 .word 0x000026c8
490c: 000026aa .word 0x000026aa
4910: 00002664 .word 0x00002664
4914: 00002582 .word 0x00002582
4918: 00002664 .word 0x00002664
491c: 0000269c .word 0x0000269c
4920: 00002664 .word 0x00002664
4924: 00002582 .word 0x00002582
4928: 000026aa .word 0x000026aa
492c: 000026aa .word 0x000026aa
4930: 0000269c .word 0x0000269c
4934: 00002582 .word 0x00002582
4938: 0000257a .word 0x0000257a
493c: 0000257a .word 0x0000257a
4940: 0000257a .word 0x0000257a
4944: 000028e0 .word 0x000028e0
4948: 00002d28 .word 0x00002d28
494c: 00002be8 .word 0x00002be8
4950: 00002be8 .word 0x00002be8
4954: 00002be4 .word 0x00002be4
4958: 00002d00 .word 0x00002d00
495c: 00002d00 .word 0x00002d00
4960: 00002cf2 .word 0x00002cf2
4964: 00002be4 .word 0x00002be4
4968: 00002d00 .word 0x00002d00
496c: 00002cf2 .word 0x00002cf2
4970: 00002d00 .word 0x00002d00
4974: 00002be4 .word 0x00002be4
4978: 00002d08 .word 0x00002d08
497c: 00002d08 .word 0x00002d08
4980: 00002d08 .word 0x00002d08
4984: 00002f0c .word 0x00002f0c
00004988 <_global_impure_ptr>:
4988: 20000008 ...
0000498c <__sf_fake_stderr>:
...
000049ac <__sf_fake_stdin>:
...
000049cc <__sf_fake_stdout>:
...
49ec: 2b302d23 6c680020 6665004c 47464567 #-0+ .hlL.efgEFG
49fc: 32313000 36353433 41393837 45444342 .0123456789ABCDE
4a0c: 31300046 35343332 39383736 64636261 F.0123456789abcd
4a1c: 00006665 ef..
00004a20 <_init>:
4a20: b5f8 push {r3, r4, r5, r6, r7, lr}
4a22: 46c0 nop ; (mov r8, r8)
4a24: bcf8 pop {r3, r4, r5, r6, r7}
4a26: bc08 pop {r3}
4a28: 469e mov lr, r3
4a2a: 4770 bx lr
00004a2c <__init_array_start>:
4a2c: 000000dd .word 0x000000dd
00004a30 <_fini>:
4a30: b5f8 push {r3, r4, r5, r6, r7, lr}
4a32: 46c0 nop ; (mov r8, r8)
4a34: bcf8 pop {r3, r4, r5, r6, r7}
4a36: bc08 pop {r3}
4a38: 469e mov lr, r3
4a3a: 4770 bx lr
00004a3c <__fini_array_start>:
4a3c: 000000b5 .word 0x000000b5