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GFX-Development-Board/software/firmware/build/eP-GFX.lss

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eP-GFX.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000f04 00000000 00000000 00010000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .relocate 00000000 20000000 20000000 00010f04 2**0
CONTENTS
2 .bkupram 00000000 47000000 47000000 00010f04 2**0
CONTENTS
3 .qspi 00000000 04000000 04000000 00010f04 2**0
CONTENTS
4 .bss 00000090 20000000 20000000 00020000 2**3
ALLOC
5 .stack 0000c000 20000090 20000090 00020000 2**0
ALLOC
6 .ARM.attributes 0000002e 00000000 00000000 00010f04 2**0
CONTENTS, READONLY
7 .comment 0000001e 00000000 00000000 00010f32 2**0
CONTENTS, READONLY
8 .debug_info 0002194c 00000000 00000000 00010f50 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
9 .debug_abbrev 000028f2 00000000 00000000 0003289c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
10 .debug_loc 0000a0c3 00000000 00000000 0003518e 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
11 .debug_aranges 000009b8 00000000 00000000 0003f251 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
12 .debug_ranges 00001878 00000000 00000000 0003fc09 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_macro 0000a22f 00000000 00000000 00041481 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_line 0001221d 00000000 00000000 0004b6b0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_str 0011b7fa 00000000 00000000 0005d8cd 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_frame 00001b14 00000000 00000000 001790c8 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
00000000 <exception_table>:
0: 90 c0 00 20 95 06 00 00 93 06 00 00 93 06 00 00 ... ............
10: 93 06 00 00 93 06 00 00 93 06 00 00 00 00 00 00 ................
...
2c: 93 06 00 00 93 06 00 00 00 00 00 00 93 06 00 00 ................
3c: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
4c: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
5c: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
6c: d5 07 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
7c: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
8c: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
9c: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
ac: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
bc: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
cc: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
dc: 93 06 00 00 93 06 00 00 93 06 00 00 00 00 00 00 ................
...
f4: 59 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 Y...............
104: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
114: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
124: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
134: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
144: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
154: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
164: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
174: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
184: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
194: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
1a4: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
1b4: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
1c4: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
1d4: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
1e4: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
1f4: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
204: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
214: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
224: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
234: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
244: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
254: 93 06 00 00 93 06 00 00 93 06 00 00 93 06 00 00 ................
00000264 <__do_global_dtors_aux>:
264: b510 push {r4, lr}
266: 4c05 ldr r4, [pc, #20] ; (27c <__do_global_dtors_aux+0x18>)
268: 7823 ldrb r3, [r4, #0]
26a: b933 cbnz r3, 27a <__do_global_dtors_aux+0x16>
26c: 4b04 ldr r3, [pc, #16] ; (280 <__do_global_dtors_aux+0x1c>)
26e: b113 cbz r3, 276 <__do_global_dtors_aux+0x12>
270: 4804 ldr r0, [pc, #16] ; (284 <__do_global_dtors_aux+0x20>)
272: f3af 8000 nop.w
276: 2301 movs r3, #1
278: 7023 strb r3, [r4, #0]
27a: bd10 pop {r4, pc}
27c: 20000000 .word 0x20000000
280: 00000000 .word 0x00000000
284: 00000f04 .word 0x00000f04
00000288 <frame_dummy>:
288: b508 push {r3, lr}
28a: 4b03 ldr r3, [pc, #12] ; (298 <frame_dummy+0x10>)
28c: b11b cbz r3, 296 <frame_dummy+0xe>
28e: 4903 ldr r1, [pc, #12] ; (29c <frame_dummy+0x14>)
290: 4803 ldr r0, [pc, #12] ; (2a0 <frame_dummy+0x18>)
292: f3af 8000 nop.w
296: bd08 pop {r3, pc}
298: 00000000 .word 0x00000000
29c: 20000004 .word 0x20000004
2a0: 00000f04 .word 0x00000f04
000002a4 <calendar_init>:
}
/** \brief Initialize Calendar
*/
int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw)
{
2a4: b538 push {r3, r4, r5, lr}
int32_t ret = 0;
/* Sanity check arguments */
ASSERT(calendar);
2a6: 4604 mov r4, r0
2a8: 3800 subs r0, #0
2aa: 4b0c ldr r3, [pc, #48] ; (2dc <calendar_init+0x38>)
{
2ac: 460d mov r5, r1
ASSERT(calendar);
2ae: bf18 it ne
2b0: 2001 movne r0, #1
2b2: 490b ldr r1, [pc, #44] ; (2e0 <calendar_init+0x3c>)
2b4: f44f 72e0 mov.w r2, #448 ; 0x1c0
2b8: 4798 blx r3
if (calendar->device.hw == hw) {
2ba: 6823 ldr r3, [r4, #0]
2bc: 42ab cmp r3, r5
2be: d008 beq.n 2d2 <calendar_init+0x2e>
/* Already initialized with current configuration */
return ERR_NONE;
} else if (calendar->device.hw != NULL) {
2c0: b94b cbnz r3, 2d6 <calendar_init+0x32>
/* Initialized with another configuration */
return ERR_ALREADY_INITIALIZED;
}
calendar->device.hw = (void *)hw;
ret = _calendar_init(&calendar->device);
2c2: 4b08 ldr r3, [pc, #32] ; (2e4 <calendar_init+0x40>)
calendar->device.hw = (void *)hw;
2c4: 6025 str r5, [r4, #0]
ret = _calendar_init(&calendar->device);
2c6: 4620 mov r0, r4
2c8: 4798 blx r3
calendar->base_year = DEFAULT_BASE_YEAR;
2ca: f240 73b2 movw r3, #1970 ; 0x7b2
2ce: 61a3 str r3, [r4, #24]
return ret;
}
2d0: bd38 pop {r3, r4, r5, pc}
return ERR_NONE;
2d2: 2000 movs r0, #0
2d4: e7fc b.n 2d0 <calendar_init+0x2c>
return ERR_ALREADY_INITIALIZED;
2d6: f06f 0011 mvn.w r0, #17
2da: e7f9 b.n 2d0 <calendar_init+0x2c>
2dc: 00000459 .word 0x00000459
2e0: 00000e14 .word 0x00000e14
2e4: 00000759 .word 0x00000759
000002e8 <spi_m_sync_init>:
ASSERT(spi);
spi->func = (struct _spi_m_sync_hpl_interface *)func;
}
int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw)
{
2e8: b538 push {r3, r4, r5, lr}
2ea: 460d mov r5, r1
int32_t rc = 0;
ASSERT(spi && hw);
2ec: 4604 mov r4, r0
2ee: b110 cbz r0, 2f6 <spi_m_sync_init+0xe>
2f0: 1e08 subs r0, r1, #0
2f2: bf18 it ne
2f4: 2001 movne r0, #1
2f6: 490a ldr r1, [pc, #40] ; (320 <spi_m_sync_init+0x38>)
2f8: 4b0a ldr r3, [pc, #40] ; (324 <spi_m_sync_init+0x3c>)
2fa: 2241 movs r2, #65 ; 0x41
2fc: 4798 blx r3
spi->dev.prvt = (void *)hw;
2fe: 4620 mov r0, r4
rc = _spi_m_sync_init(&spi->dev, hw);
300: 4b09 ldr r3, [pc, #36] ; (328 <spi_m_sync_init+0x40>)
spi->dev.prvt = (void *)hw;
302: f840 5f04 str.w r5, [r0, #4]!
rc = _spi_m_sync_init(&spi->dev, hw);
306: 4629 mov r1, r5
308: 4798 blx r3
if (rc < 0) {
30a: 2800 cmp r0, #0
30c: db07 blt.n 31e <spi_m_sync_init+0x36>
return rc;
}
spi->flags = SPI_DEACTIVATE_NEXT;
30e: f44f 4300 mov.w r3, #32768 ; 0x8000
312: 82a3 strh r3, [r4, #20]
spi->io.read = _spi_m_sync_io_read;
314: 4b05 ldr r3, [pc, #20] ; (32c <spi_m_sync_init+0x44>)
316: 6123 str r3, [r4, #16]
spi->io.write = _spi_m_sync_io_write;
318: 4b05 ldr r3, [pc, #20] ; (330 <spi_m_sync_init+0x48>)
31a: 60e3 str r3, [r4, #12]
return ERR_NONE;
31c: 2000 movs r0, #0
}
31e: bd38 pop {r3, r4, r5, pc}
320: 00000e2e .word 0x00000e2e
324: 00000459 .word 0x00000459
328: 00000b95 .word 0x00000b95
32c: 000003a9 .word 0x000003a9
330: 00000371 .word 0x00000371
00000334 <spi_m_sync_transfer>:
return spi_m_sync_transfer(spi, &xfer);
}
int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *const spi, const struct spi_xfer *p_xfer)
{
334: b530 push {r4, r5, lr}
336: 460c mov r4, r1
338: b085 sub sp, #20
struct spi_msg msg;
ASSERT(spi && p_xfer);
33a: 4605 mov r5, r0
33c: b110 cbz r0, 344 <spi_m_sync_transfer+0x10>
33e: 1e08 subs r0, r1, #0
340: bf18 it ne
342: 2001 movne r0, #1
344: 22b4 movs r2, #180 ; 0xb4
346: 4907 ldr r1, [pc, #28] ; (364 <spi_m_sync_transfer+0x30>)
348: 4b07 ldr r3, [pc, #28] ; (368 <spi_m_sync_transfer+0x34>)
34a: 4798 blx r3
msg.txbuf = p_xfer->txbuf;
34c: 6823 ldr r3, [r4, #0]
34e: 9301 str r3, [sp, #4]
msg.rxbuf = p_xfer->rxbuf;
350: 6863 ldr r3, [r4, #4]
352: 9302 str r3, [sp, #8]
msg.size = p_xfer->size;
354: 68a3 ldr r3, [r4, #8]
356: 9303 str r3, [sp, #12]
return _spi_m_sync_trans(&spi->dev, &msg);
358: a901 add r1, sp, #4
35a: 4b04 ldr r3, [pc, #16] ; (36c <spi_m_sync_transfer+0x38>)
35c: 1d28 adds r0, r5, #4
35e: 4798 blx r3
}
360: b005 add sp, #20
362: bd30 pop {r4, r5, pc}
364: 00000e2e .word 0x00000e2e
368: 00000459 .word 0x00000459
36c: 00000cc9 .word 0x00000cc9
00000370 <_spi_m_sync_io_write>:
{
370: b57f push {r0, r1, r2, r3, r4, r5, r6, lr}
ASSERT(io);
372: 4604 mov r4, r0
374: 3800 subs r0, #0
376: bf18 it ne
378: 2001 movne r0, #1
{
37a: 460e mov r6, r1
37c: 4615 mov r5, r2
ASSERT(io);
37e: 4907 ldr r1, [pc, #28] ; (39c <_spi_m_sync_io_write+0x2c>)
380: 4b07 ldr r3, [pc, #28] ; (3a0 <_spi_m_sync_io_write+0x30>)
382: 22a4 movs r2, #164 ; 0xa4
384: 4798 blx r3
xfer.rxbuf = 0;
386: 2300 movs r3, #0
xfer.txbuf = (uint8_t *)buf;
388: e9cd 6301 strd r6, r3, [sp, #4]
return spi_m_sync_transfer(spi, &xfer);
38c: a901 add r1, sp, #4
38e: 4b05 ldr r3, [pc, #20] ; (3a4 <_spi_m_sync_io_write+0x34>)
xfer.size = length;
390: 9503 str r5, [sp, #12]
return spi_m_sync_transfer(spi, &xfer);
392: f1a4 000c sub.w r0, r4, #12
396: 4798 blx r3
}
398: b004 add sp, #16
39a: bd70 pop {r4, r5, r6, pc}
39c: 00000e2e .word 0x00000e2e
3a0: 00000459 .word 0x00000459
3a4: 00000335 .word 0x00000335
000003a8 <_spi_m_sync_io_read>:
{
3a8: b57f push {r0, r1, r2, r3, r4, r5, r6, lr}
ASSERT(io);
3aa: 4604 mov r4, r0
3ac: 3800 subs r0, #0
3ae: bf18 it ne
3b0: 2001 movne r0, #1
{
3b2: 460e mov r6, r1
3b4: 4615 mov r5, r2
ASSERT(io);
3b6: 4907 ldr r1, [pc, #28] ; (3d4 <_spi_m_sync_io_read+0x2c>)
3b8: 4b07 ldr r3, [pc, #28] ; (3d8 <_spi_m_sync_io_read+0x30>)
3ba: 2288 movs r2, #136 ; 0x88
3bc: 4798 blx r3
xfer.txbuf = 0;
3be: 2300 movs r3, #0
3c0: 9301 str r3, [sp, #4]
return spi_m_sync_transfer(spi, &xfer);
3c2: a901 add r1, sp, #4
3c4: 4b05 ldr r3, [pc, #20] ; (3dc <_spi_m_sync_io_read+0x34>)
xfer.rxbuf = buf;
3c6: 9602 str r6, [sp, #8]
return spi_m_sync_transfer(spi, &xfer);
3c8: f1a4 000c sub.w r0, r4, #12
xfer.size = length;
3cc: 9503 str r5, [sp, #12]
return spi_m_sync_transfer(spi, &xfer);
3ce: 4798 blx r3
}
3d0: b004 add sp, #16
3d2: bd70 pop {r4, r5, r6, pc}
3d4: 00000e2e .word 0x00000e2e
3d8: 00000459 .word 0x00000459
3dc: 00000335 .word 0x00000335
000003e0 <_init_chip>:
}
static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask)
{
NVMCTRL_CRITICAL_SECTION_ENTER();
((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask);
3e0: 4a09 ldr r2, [pc, #36] ; (408 <_init_chip+0x28>)
3e2: 8813 ldrh r3, [r2, #0]
/**
* \brief Initialize the hardware abstraction layer
*/
void _init_chip(void)
{
3e4: b510 push {r4, lr}
3e6: b29b uxth r3, r3
3e8: 8013 strh r3, [r2, #0]
hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
_osc32kctrl_init_sources();
3ea: 4b08 ldr r3, [pc, #32] ; (40c <_init_chip+0x2c>)
3ec: 4798 blx r3
_oscctrl_init_sources();
3ee: 4b08 ldr r3, [pc, #32] ; (410 <_init_chip+0x30>)
3f0: 4798 blx r3
_mclk_init();
3f2: 4b08 ldr r3, [pc, #32] ; (414 <_init_chip+0x34>)
3f4: 4798 blx r3
#if _GCLK_INIT_1ST
_gclk_init_generators_by_fref(_GCLK_INIT_1ST);
#endif
_oscctrl_init_referenced_generators();
3f6: 4b08 ldr r3, [pc, #32] ; (418 <_init_chip+0x38>)
3f8: 4798 blx r3
#endif
#if CONF_CMCC_ENABLE
cache_init();
#endif
}
3fa: e8bd 4010 ldmia.w sp!, {r4, lr}
_gclk_init_generators_by_fref(_GCLK_INIT_LAST);
3fe: 4b07 ldr r3, [pc, #28] ; (41c <_init_chip+0x3c>)
400: f640 70ff movw r0, #4095 ; 0xfff
404: 4718 bx r3
406: bf00 nop
408: 41004000 .word 0x41004000
40c: 00000731 .word 0x00000731
410: 00000461 .word 0x00000461
414: 0000064d .word 0x0000064d
418: 00000479 .word 0x00000479
41c: 00000421 .word 0x00000421
00000420 <_gclk_init_generators_by_fref>:
void _gclk_init_generators_by_fref(uint32_t bm)
{
#if CONF_GCLK_GENERATOR_0_CONFIG == 1
if (bm & (1ul << 0)) {
420: 07c2 lsls r2, r0, #31
422: d507 bpl.n 434 <_gclk_init_generators_by_fref+0x14>
}
static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->GENCTRL[index].reg = data;
424: 4b09 ldr r3, [pc, #36] ; (44c <_gclk_init_generators_by_fref+0x2c>)
426: 4a0a ldr r2, [pc, #40] ; (450 <_gclk_init_generators_by_fref+0x30>)
428: 621a str r2, [r3, #32]
while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
42a: f643 72fd movw r2, #16381 ; 0x3ffd
42e: 6859 ldr r1, [r3, #4]
430: 4211 tst r1, r2
432: d1fc bne.n 42e <_gclk_init_generators_by_fref+0xe>
| (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE);
}
#endif
#if CONF_GCLK_GENERATOR_3_CONFIG == 1
if (bm & (1ul << 3)) {
434: 0703 lsls r3, r0, #28
436: d507 bpl.n 448 <_gclk_init_generators_by_fref+0x28>
((Gclk *)hw)->GENCTRL[index].reg = data;
438: 4b04 ldr r3, [pc, #16] ; (44c <_gclk_init_generators_by_fref+0x2c>)
43a: 4a06 ldr r2, [pc, #24] ; (454 <_gclk_init_generators_by_fref+0x34>)
43c: 62da str r2, [r3, #44] ; 0x2c
while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
43e: f643 72fd movw r2, #16381 ; 0x3ffd
442: 6859 ldr r1, [r3, #4]
444: 4211 tst r1, r2
446: d1fc bne.n 442 <_gclk_init_generators_by_fref+0x22>
| (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos)
| (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos)
| (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE);
}
#endif
}
448: 4770 bx lr
44a: bf00 nop
44c: 40001c00 .word 0x40001c00
450: 00010101 .word 0x00010101
454: 00010105 .word 0x00010105
00000458 <assert>:
/**
* \brief Assert function
*/
void assert(const bool condition, const char *const file, const int line)
{
if (!(condition)) {
458: b900 cbnz r0, 45c <assert+0x4>
__asm("BKPT #0");
45a: be00 bkpt 0x0000
}
(void)file;
(void)line;
}
45c: 4770 bx lr
...
00000460 <_oscctrl_init_sources>:
}
static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data)
{
OSCCTRL_CRITICAL_SECTION_ENTER();
((Oscctrl *)hw)->XOSCCTRL[index].reg = data;
460: 4b03 ldr r3, [pc, #12] ; (470 <_oscctrl_init_sources+0x10>)
462: 4a04 ldr r2, [pc, #16] ; (474 <_oscctrl_init_sources+0x14>)
464: 619a str r2, [r3, #24]
return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos;
466: 691a ldr r2, [r3, #16]
| (CONF_XOSC1_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC1_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos));
#endif
#if CONF_XOSC1_CONFIG == 1
#if CONF_XOSC1_ENABLE == 1
while (!hri_oscctrl_get_STATUS_XOSCRDY1_bit(hw))
468: 0792 lsls r2, r2, #30
46a: d5fc bpl.n 466 <_oscctrl_init_sources+0x6>
hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1);
#endif
#endif
(void)hw;
}
46c: 4770 bx lr
46e: bf00 nop
470: 40001000 .word 0x40001000
474: 03002606 .word 0x03002606
00000478 <_oscctrl_init_referenced_generators>:
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
478: 4a2c ldr r2, [pc, #176] ; (52c <_oscctrl_init_referenced_generators+0xb4>)
47a: 6a13 ldr r3, [r2, #32]
tmp &= ~GCLK_GENCTRL_SRC_Msk;
47c: f023 030f bic.w r3, r3, #15
tmp |= GCLK_GENCTRL_SRC(data);
480: f043 0304 orr.w r3, r3, #4
((Gclk *)hw)->GENCTRL[index].reg = tmp;
484: 6213 str r3, [r2, #32]
while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
486: f643 73fd movw r3, #16381 ; 0x3ffd
48a: 6851 ldr r1, [r2, #4]
48c: 4219 tst r1, r3
48e: d1fc bne.n 48a <_oscctrl_init_referenced_generators+0x12>
return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos;
490: 6853 ldr r3, [r2, #4]
{
void *hw = (void *)OSCCTRL;
#if CONF_DFLL_CONFIG == 1
hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K);
while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK))
492: 0758 lsls r0, r3, #29
494: f3c3 0180 ubfx r1, r3, #2, #1
498: d4fa bmi.n 490 <_oscctrl_init_referenced_generators+0x18>
}
static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data)
{
OSCCTRL_CRITICAL_SECTION_ENTER();
((Oscctrl *)hw)->DFLLCTRLA.reg = data;
49a: 4b25 ldr r3, [pc, #148] ; (530 <_oscctrl_init_referenced_generators+0xb8>)
}
static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data)
{
OSCCTRL_CRITICAL_SECTION_ENTER();
((Oscctrl *)hw)->DFLLMUL.reg = data;
49c: 4a25 ldr r2, [pc, #148] ; (534 <_oscctrl_init_referenced_generators+0xbc>)
((Oscctrl *)hw)->DFLLCTRLA.reg = data;
49e: 7719 strb r1, [r3, #28]
((Oscctrl *)hw)->DFLLMUL.reg = data;
4a0: 629a str r2, [r3, #40] ; 0x28
}
static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw)
{
uint8_t tmp;
tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
4a2: f893 202c ldrb.w r2, [r3, #44] ; 0x2c
#endif
hri_oscctrl_write_DFLLMUL_reg(hw,
OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP)
| OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL));
while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw))
4a6: f3c2 1100 ubfx r1, r2, #4, #1
4aa: 06d2 lsls r2, r2, #27
4ac: d4f9 bmi.n 4a2 <_oscctrl_init_referenced_generators+0x2a>
((Oscctrl *)hw)->DFLLCTRLB.reg = data;
4ae: f883 1020 strb.w r1, [r3, #32]
tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
4b2: 4b1f ldr r3, [pc, #124] ; (530 <_oscctrl_init_referenced_generators+0xb8>)
4b4: f893 202c ldrb.w r2, [r3, #44] ; 0x2c
;
hri_oscctrl_write_DFLLCTRLB_reg(hw, 0);
while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw))
4b8: 0750 lsls r0, r2, #29
4ba: d4fb bmi.n 4b4 <_oscctrl_init_referenced_generators+0x3c>
((Oscctrl *)hw)->DFLLCTRLA.reg = data;
4bc: 2202 movs r2, #2
4be: 771a strb r2, [r3, #28]
tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
4c0: 4b1b ldr r3, [pc, #108] ; (530 <_oscctrl_init_referenced_generators+0xb8>)
4c2: f893 202c ldrb.w r2, [r3, #44] ; 0x2c
;
tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE;
hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp);
while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw))
4c6: 0791 lsls r1, r2, #30
4c8: d4fb bmi.n 4c2 <_oscctrl_init_referenced_generators+0x4a>
return ((Oscctrl *)hw)->DFLLVAL.reg;
4ca: 6a5a ldr r2, [r3, #36] ; 0x24
((Oscctrl *)hw)->DFLLVAL.reg = data;
4cc: 625a str r2, [r3, #36] ; 0x24
tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
4ce: 4b18 ldr r3, [pc, #96] ; (530 <_oscctrl_init_referenced_generators+0xb8>)
4d0: f893 202c ldrb.w r2, [r3, #44] ; 0x2c
#if CONF_DFLL_OVERWRITE_CALIBRATION == 1
hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE));
#endif
hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw));
while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw))
4d4: 0712 lsls r2, r2, #28
4d6: d4fb bmi.n 4d0 <_oscctrl_init_referenced_generators+0x58>
((Oscctrl *)hw)->DFLLCTRLB.reg = data;
4d8: 229f movs r2, #159 ; 0x9f
4da: f883 2020 strb.w r2, [r3, #32]
tmp = ((Oscctrl *)hw)->DFLLSYNC.reg;
4de: 4b14 ldr r3, [pc, #80] ; (530 <_oscctrl_init_referenced_generators+0xb8>)
4e0: f893 202c ldrb.w r2, [r3, #44] ; 0x2c
tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)
| (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos)
| (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos)
| (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0;
hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp);
while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw))
4e4: 0750 lsls r0, r2, #29
4e6: d4fb bmi.n 4e0 <_oscctrl_init_referenced_generators+0x68>
tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg;
4e8: f893 2020 ldrb.w r2, [r3, #32]
(CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
| (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos));
#endif
#if CONF_DFLL_CONFIG == 1
if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) {
4ec: 07d1 lsls r1, r2, #31
4ee: d519 bpl.n 524 <_oscctrl_init_referenced_generators+0xac>
tmp = ((Oscctrl *)hw)->STATUS.reg;
4f0: 691a ldr r2, [r3, #16]
tmp &= mask;
4f2: f402 6210 and.w r2, r2, #2304 ; 0x900
hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC;
while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask)
4f6: f5b2 6f10 cmp.w r2, #2304 ; 0x900
4fa: d1f9 bne.n 4f0 <_oscctrl_init_referenced_generators+0x78>
return ((Gclk *)hw)->SYNCBUSY.reg;
4fc: 4a0b ldr r2, [pc, #44] ; (52c <_oscctrl_init_referenced_generators+0xb4>)
4fe: 6853 ldr r3, [r2, #4]
hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1);
#endif
#endif
#if CONF_DFLL_CONFIG == 1
while (hri_gclk_read_SYNCBUSY_reg(GCLK))
500: 2b00 cmp r3, #0
502: d1fc bne.n 4fe <_oscctrl_init_referenced_generators+0x86>
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
504: 6a13 ldr r3, [r2, #32]
tmp &= ~GCLK_GENCTRL_SRC_Msk;
506: f023 030f bic.w r3, r3, #15
tmp |= GCLK_GENCTRL_SRC(data);
50a: f043 0301 orr.w r3, r3, #1
((Gclk *)hw)->GENCTRL[index].reg = tmp;
50e: 6213 str r3, [r2, #32]
while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
510: f643 73fd movw r3, #16381 ; 0x3ffd
514: 6851 ldr r1, [r2, #4]
516: 4219 tst r1, r3
518: d1fc bne.n 514 <_oscctrl_init_referenced_generators+0x9c>
return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos;
51a: 4a04 ldr r2, [pc, #16] ; (52c <_oscctrl_init_referenced_generators+0xb4>)
51c: 6853 ldr r3, [r2, #4]
;
hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE);
while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK))
51e: 075b lsls r3, r3, #29
520: d4fc bmi.n 51c <_oscctrl_init_referenced_generators+0xa4>
;
#endif
(void)hw;
}
522: 4770 bx lr
return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos;
524: 691a ldr r2, [r3, #16]
while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw))
526: 05d2 lsls r2, r2, #23
528: d5fc bpl.n 524 <_oscctrl_init_referenced_generators+0xac>
52a: e7e7 b.n 4fc <_oscctrl_init_referenced_generators+0x84>
52c: 40001c00 .word 0x40001c00
530: 40001000 .word 0x40001000
534: 04010000 .word 0x04010000
00000538 <usart_sync_write>:
* \param[in] length The number of bytes to write
*
* \return The number of bytes written.
*/
static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
{
538: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
53c: 460e mov r6, r1
53e: 4615 mov r5, r2
uint32_t offset = 0;
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
ASSERT(io_descr && buf && length);
540: 4604 mov r4, r0
542: b118 cbz r0, 54c <usart_sync_write+0x14>
544: b329 cbz r1, 592 <usart_sync_write+0x5a>
546: 1e10 subs r0, r2, #0
548: bf18 it ne
54a: 2001 movne r0, #1
54c: 4912 ldr r1, [pc, #72] ; (598 <usart_sync_write+0x60>)
54e: 4b13 ldr r3, [pc, #76] ; (59c <usart_sync_write+0x64>)
while (!_usart_sync_is_ready_to_send(&descr->device))
550: 4f13 ldr r7, [pc, #76] ; (5a0 <usart_sync_write+0x68>)
ASSERT(io_descr && buf && length);
552: 22f1 movs r2, #241 ; 0xf1
554: 4798 blx r3
while (!_usart_sync_is_ready_to_send(&descr->device))
556: 3408 adds r4, #8
558: 46b9 mov r9, r7
55a: 4620 mov r0, r4
55c: 47b8 blx r7
55e: 2800 cmp r0, #0
560: d0fb beq.n 55a <usart_sync_write+0x22>
;
do {
_usart_sync_write_byte(&descr->device, buf[offset]);
562: f8df 8044 ldr.w r8, [pc, #68] ; 5a8 <usart_sync_write+0x70>
uint32_t offset = 0;
566: 2700 movs r7, #0
_usart_sync_write_byte(&descr->device, buf[offset]);
568: 5df1 ldrb r1, [r6, r7]
56a: 4620 mov r0, r4
56c: 47c0 blx r8
while (!_usart_sync_is_ready_to_send(&descr->device))
56e: 4620 mov r0, r4
570: 47c8 blx r9
572: 2800 cmp r0, #0
574: d0fb beq.n 56e <usart_sync_write+0x36>
;
} while (++offset < length);
576: 3701 adds r7, #1
578: 42bd cmp r5, r7
57a: d8f5 bhi.n 568 <usart_sync_write+0x30>
57c: 2d00 cmp r5, #0
while (!_usart_sync_is_transmit_done(&descr->device))
57e: 4e09 ldr r6, [pc, #36] ; (5a4 <usart_sync_write+0x6c>)
} while (++offset < length);
580: bf08 it eq
582: 2501 moveq r5, #1
while (!_usart_sync_is_transmit_done(&descr->device))
584: 4620 mov r0, r4
586: 47b0 blx r6
588: 2800 cmp r0, #0
58a: d0fb beq.n 584 <usart_sync_write+0x4c>
;
return (int32_t)offset;
}
58c: 4628 mov r0, r5
58e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
ASSERT(io_descr && buf && length);
592: 4608 mov r0, r1
594: e7da b.n 54c <usart_sync_write+0x14>
596: bf00 nop
598: 00000e4a .word 0x00000e4a
59c: 00000459 .word 0x00000459
5a0: 00000b77 .word 0x00000b77
5a4: 00000b81 .word 0x00000b81
5a8: 00000b69 .word 0x00000b69
000005ac <usart_sync_read>:
* \param[in] length The size of a buffer
*
* \return The number of bytes read.
*/
static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
{
5ac: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
5b0: 460e mov r6, r1
5b2: 4615 mov r5, r2
uint32_t offset = 0;
struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
ASSERT(io_descr && buf && length);
5b4: 4604 mov r4, r0
5b6: b118 cbz r0, 5c0 <usart_sync_read+0x14>
5b8: b1e9 cbz r1, 5f6 <usart_sync_read+0x4a>
5ba: 1e10 subs r0, r2, #0
5bc: bf18 it ne
5be: 2001 movne r0, #1
5c0: 490e ldr r1, [pc, #56] ; (5fc <usart_sync_read+0x50>)
5c2: 4b0f ldr r3, [pc, #60] ; (600 <usart_sync_read+0x54>)
do {
while (!_usart_sync_is_byte_received(&descr->device))
5c4: f8df 903c ldr.w r9, [pc, #60] ; 604 <usart_sync_read+0x58>
;
buf[offset] = _usart_sync_read_byte(&descr->device);
5c8: f8df 803c ldr.w r8, [pc, #60] ; 608 <usart_sync_read+0x5c>
ASSERT(io_descr && buf && length);
5cc: f44f 7286 mov.w r2, #268 ; 0x10c
5d0: 4798 blx r3
uint32_t offset = 0;
5d2: 2700 movs r7, #0
while (!_usart_sync_is_byte_received(&descr->device))
5d4: 3408 adds r4, #8
5d6: 4620 mov r0, r4
5d8: 47c8 blx r9
5da: 2800 cmp r0, #0
5dc: d0fb beq.n 5d6 <usart_sync_read+0x2a>
buf[offset] = _usart_sync_read_byte(&descr->device);
5de: 4620 mov r0, r4
5e0: 47c0 blx r8
5e2: 55f0 strb r0, [r6, r7]
} while (++offset < length);
5e4: 3701 adds r7, #1
5e6: 42bd cmp r5, r7
5e8: d8f5 bhi.n 5d6 <usart_sync_read+0x2a>
5ea: 2d00 cmp r5, #0
return (int32_t)offset;
}
5ec: bf14 ite ne
5ee: 4628 movne r0, r5
5f0: 2001 moveq r0, #1
5f2: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
ASSERT(io_descr && buf && length);
5f6: 4608 mov r0, r1
5f8: e7e2 b.n 5c0 <usart_sync_read+0x14>
5fa: bf00 nop
5fc: 00000e4a .word 0x00000e4a
600: 00000459 .word 0x00000459
604: 00000b8b .word 0x00000b8b
608: 00000b6f .word 0x00000b6f
0000060c <usart_sync_init>:
{
60c: b538 push {r3, r4, r5, lr}
60e: 460d mov r5, r1
ASSERT(descr && hw);
610: 4604 mov r4, r0
612: b110 cbz r0, 61a <usart_sync_init+0xe>
614: 1e08 subs r0, r1, #0
616: bf18 it ne
618: 2001 movne r0, #1
61a: 4907 ldr r1, [pc, #28] ; (638 <usart_sync_init+0x2c>)
61c: 4b07 ldr r3, [pc, #28] ; (63c <usart_sync_init+0x30>)
61e: 2234 movs r2, #52 ; 0x34
620: 4798 blx r3
init_status = _usart_sync_init(&descr->device, hw);
622: 4b07 ldr r3, [pc, #28] ; (640 <usart_sync_init+0x34>)
624: 4629 mov r1, r5
626: f104 0008 add.w r0, r4, #8
62a: 4798 blx r3
if (init_status) {
62c: b918 cbnz r0, 636 <usart_sync_init+0x2a>
descr->io.read = usart_sync_read;
62e: 4b05 ldr r3, [pc, #20] ; (644 <usart_sync_init+0x38>)
630: 6063 str r3, [r4, #4]
descr->io.write = usart_sync_write;
632: 4b05 ldr r3, [pc, #20] ; (648 <usart_sync_init+0x3c>)
634: 6023 str r3, [r4, #0]
}
636: bd38 pop {r3, r4, r5, pc}
638: 00000e4a .word 0x00000e4a
63c: 00000459 .word 0x00000459
640: 00000b3d .word 0x00000b3d
644: 000005ad .word 0x000005ad
648: 00000539 .word 0x00000539
0000064c <_mclk_init>:
}
static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data)
{
MCLK_CRITICAL_SECTION_ENTER();
((Mclk *)hw)->CPUDIV.reg = data;
64c: 4b01 ldr r3, [pc, #4] ; (654 <_mclk_init+0x8>)
64e: 2201 movs r2, #1
650: 715a strb r2, [r3, #5]
*/
void _mclk_init(void)
{
void *hw = (void *)MCLK;
hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV));
}
652: 4770 bx lr
654: 40000800 .word 0x40000800
00000658 <RAMECC_Handler>:
return tmp;
}
static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw)
{
return ((Ramecc *)hw)->INTFLAG.reg;
658: 4a0b ldr r2, [pc, #44] ; (688 <RAMECC_Handler+0x30>)
65a: 7893 ldrb r3, [r2, #2]
/**
* \internal RAMECC interrupt handler
*/
void RAMECC_Handler(void)
{
65c: b082 sub sp, #8
65e: b2db uxtb r3, r3
struct _ramecc_device *dev = (struct _ramecc_device *)&device;
volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC);
660: 9301 str r3, [sp, #4]
if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) {
662: 9b01 ldr r3, [sp, #4]
664: 0799 lsls r1, r3, #30
666: d505 bpl.n 674 <RAMECC_Handler+0x1c>
668: 4b08 ldr r3, [pc, #32] ; (68c <RAMECC_Handler+0x34>)
66a: 681b ldr r3, [r3, #0]
66c: b113 cbz r3, 674 <RAMECC_Handler+0x1c>
return tmp;
}
static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw)
{
return ((Ramecc *)hw)->ERRADDR.reg;
66e: 6850 ldr r0, [r2, #4]
} else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) {
dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
} else {
return;
}
}
670: b002 add sp, #8
dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
672: 4718 bx r3
} else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) {
674: 9b01 ldr r3, [sp, #4]
676: 07db lsls r3, r3, #31
678: d504 bpl.n 684 <RAMECC_Handler+0x2c>
67a: 4b04 ldr r3, [pc, #16] ; (68c <RAMECC_Handler+0x34>)
67c: 685b ldr r3, [r3, #4]
67e: b10b cbz r3, 684 <RAMECC_Handler+0x2c>
680: 4a01 ldr r2, [pc, #4] ; (688 <RAMECC_Handler+0x30>)
682: e7f4 b.n 66e <RAMECC_Handler+0x16>
}
684: b002 add sp, #8
686: 4770 bx lr
688: 41020000 .word 0x41020000
68c: 2000001c .word 0x2000001c
00000690 <diskio_init>:
#include "diskio_start.h"
void diskio_init(void)
{
}
690: 4770 bx lr
00000692 <Dummy_Handler>:
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
692: e7fe b.n 692 <Dummy_Handler>
00000694 <Reset_Handler>:
if (pSrc != pDest) {
694: 4918 ldr r1, [pc, #96] ; (6f8 <Reset_Handler+0x64>)
696: 4819 ldr r0, [pc, #100] ; (6fc <Reset_Handler+0x68>)
698: 4281 cmp r1, r0
{
69a: b510 push {r4, lr}
if (pSrc != pDest) {
69c: d00a beq.n 6b4 <Reset_Handler+0x20>
*pDest++ = *pSrc++;
69e: 4b18 ldr r3, [pc, #96] ; (700 <Reset_Handler+0x6c>)
6a0: 1cda adds r2, r3, #3
6a2: 1a12 subs r2, r2, r0
6a4: f022 0203 bic.w r2, r2, #3
6a8: 1ec4 subs r4, r0, #3
6aa: 42a3 cmp r3, r4
6ac: bf38 it cc
6ae: 2200 movcc r2, #0
6b0: 4b14 ldr r3, [pc, #80] ; (704 <Reset_Handler+0x70>)
6b2: 4798 blx r3
*pDest++ = 0;
6b4: 4b14 ldr r3, [pc, #80] ; (708 <Reset_Handler+0x74>)
6b6: 4815 ldr r0, [pc, #84] ; (70c <Reset_Handler+0x78>)
6b8: 1cda adds r2, r3, #3
6ba: 1a12 subs r2, r2, r0
6bc: 1ec1 subs r1, r0, #3
6be: f022 0203 bic.w r2, r2, #3
6c2: 4299 cmp r1, r3
6c4: bf88 it hi
6c6: 2200 movhi r2, #0
6c8: 4b11 ldr r3, [pc, #68] ; (710 <Reset_Handler+0x7c>)
6ca: 2100 movs r1, #0
6cc: 4798 blx r3
SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
6ce: 4a11 ldr r2, [pc, #68] ; (714 <Reset_Handler+0x80>)
6d0: 4b11 ldr r3, [pc, #68] ; (718 <Reset_Handler+0x84>)
6d2: f022 027f bic.w r2, r2, #127 ; 0x7f
6d6: 609a str r2, [r3, #8]
SCB->CPACR |= (0xFu << 20);
6d8: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88
6dc: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000
6e0: f8c3 2088 str.w r2, [r3, #136] ; 0x88
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
6e4: f3bf 8f4f dsb sy
__ASM volatile ("isb 0xF":::"memory");
6e8: f3bf 8f6f isb sy
__libc_init_array();
6ec: 4b0b ldr r3, [pc, #44] ; (71c <Reset_Handler+0x88>)
6ee: 4798 blx r3
main();
6f0: 4b0b ldr r3, [pc, #44] ; (720 <Reset_Handler+0x8c>)
6f2: 4798 blx r3
while (1)
6f4: e7fe b.n 6f4 <Reset_Handler+0x60>
6f6: bf00 nop
6f8: 00000f04 .word 0x00000f04
6fc: 20000000 .word 0x20000000
700: 20000000 .word 0x20000000
704: 00000de9 .word 0x00000de9
708: 20000090 .word 0x20000090
70c: 20000000 .word 0x20000000
710: 00000e05 .word 0x00000e05
714: 00000000 .word 0x00000000
718: e000ed00 .word 0xe000ed00
71c: 00000da1 .word 0x00000da1
720: 00000725 .word 0x00000725
00000724 <main>:
#include <atmel_start.h>
int main(void)
{
724: b508 push {r3, lr}
/* Initializes MCU, drivers and middleware */
atmel_start_init();
726: 4b01 ldr r3, [pc, #4] ; (72c <main+0x8>)
728: 4798 blx r3
/* Replace with your application code */
while (1) {
72a: e7fe b.n 72a <main+0x6>
72c: 00000d89 .word 0x00000d89
00000730 <_osc32kctrl_init_sources>:
}
static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data)
{
OSC32KCTRL_CRITICAL_SECTION_ENTER();
((Osc32kctrl *)hw)->XOSC32K.reg = data;
730: 4b06 ldr r3, [pc, #24] ; (74c <_osc32kctrl_init_sources+0x1c>)
732: f242 0286 movw r2, #8326 ; 0x2086
736: 829a strh r2, [r3, #20]
}
static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data)
{
OSC32KCTRL_CRITICAL_SECTION_ENTER();
((Osc32kctrl *)hw)->CFDCTRL.reg = data;
738: 2200 movs r2, #0
73a: 759a strb r2, [r3, #22]
}
static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data)
{
OSC32KCTRL_CRITICAL_SECTION_ENTER();
((Osc32kctrl *)hw)->EVCTRL.reg = data;
73c: 75da strb r2, [r3, #23]
}
static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
{
uint32_t tmp;
tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
73e: 69da ldr r2, [r3, #28]
calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
hri_osc32kctrl_write_OSCULP32K_reg(hw,
#if CONF_OSCULP32K_CALIB_ENABLE == 1
OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB)
#else
OSC32KCTRL_OSCULP32K_CALIB(calib)
740: f402 527c and.w r2, r2, #16128 ; 0x3f00
}
static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
{
OSC32KCTRL_CRITICAL_SECTION_ENTER();
((Osc32kctrl *)hw)->OSCULP32K.reg = data;
744: 61da str r2, [r3, #28]
((Osc32kctrl *)hw)->RTCCTRL.reg = data;
746: 2201 movs r2, #1
748: 741a strb r2, [r3, #16]
#endif
#endif
hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
(void)calib;
}
74a: 4770 bx lr
74c: 40001400 .word 0x40001400
00000750 <hri_rtcmode0_wait_for_sync>:
typedef uint8_t hri_rtcalarm_mask_reg_t;
typedef uint8_t hri_rtcmode2_mask_reg_t;
static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg)
{
while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) {
750: 6903 ldr r3, [r0, #16]
752: 420b tst r3, r1
754: d1fc bne.n 750 <hri_rtcmode0_wait_for_sync>
};
}
756: 4770 bx lr
00000758 <_calendar_init>:
/**
* \brief Initializes the RTC module with given configurations.
*/
int32_t _calendar_init(struct calendar_dev *const dev)
{
758: b510 push {r4, lr}
ASSERT(dev && dev->hw);
75a: 4604 mov r4, r0
75c: b118 cbz r0, 766 <_calendar_init+0xe>
75e: 6800 ldr r0, [r0, #0]
760: 3800 subs r0, #0
762: bf18 it ne
764: 2001 movne r0, #1
766: 4917 ldr r1, [pc, #92] ; (7c4 <_calendar_init+0x6c>)
768: 4b17 ldr r3, [pc, #92] ; (7c8 <_calendar_init+0x70>)
76a: 222f movs r2, #47 ; 0x2f
76c: 4798 blx r3
_rtc_dev = dev;
76e: 4b17 ldr r3, [pc, #92] ; (7cc <_calendar_init+0x74>)
}
static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw)
{
uint16_t tmp;
hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
770: 6820 ldr r0, [r4, #0]
772: 4a17 ldr r2, [pc, #92] ; (7d0 <_calendar_init+0x78>)
774: 601c str r4, [r3, #0]
776: f248 0103 movw r1, #32771 ; 0x8003
77a: 4790 blx r2
tmp = ((Rtc *)hw)->MODE0.CTRLA.reg;
77c: 8803 ldrh r3, [r0, #0]
if (hri_rtcmode0_get_CTRLA_ENABLE_bit(dev->hw)) {
77e: 079b lsls r3, r3, #30
780: d50a bpl.n 798 <_calendar_init+0x40>
#if !CONF_RTC_INIT_RESET
return ERR_DENIED;
#else
hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw);
782: 6820 ldr r0, [r4, #0]
}
static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw)
{
RTC_CRITICAL_SECTION_ENTER();
((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
784: 8803 ldrh r3, [r0, #0]
786: f023 0302 bic.w r3, r3, #2
78a: 041b lsls r3, r3, #16
78c: 0c1b lsrs r3, r3, #16
78e: 8003 strh r3, [r0, #0]
hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
790: 4790 blx r2
hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_ENABLE);
792: 6820 ldr r0, [r4, #0]
794: 2102 movs r1, #2
796: 4790 blx r2
#endif
}
hri_rtcmode0_set_CTRLA_SWRST_bit(dev->hw);
798: 6820 ldr r0, [r4, #0]
((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
79a: 8803 ldrh r3, [r0, #0]
79c: b29b uxth r3, r3
79e: f043 0301 orr.w r3, r3, #1
7a2: 8003 strh r3, [r0, #0]
hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST);
7a4: 2101 movs r1, #1
7a6: 4790 blx r2
hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_SWRST);
7a8: 6820 ldr r0, [r4, #0]
7aa: 4790 blx r2
| (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos) | (CONF_RTC_COMPE1 << RTC_MODE0_EVCTRL_CMPEO1_Pos)
| (CONF_RTC_TAMPEREO << RTC_MODE0_EVCTRL_TAMPEREO_Pos)
| (CONF_RTC_TAMPEVEI << RTC_MODE0_EVCTRL_TAMPEVEI_Pos) | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos));
#endif
hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_PRESCALER(CONF_RTC_PRESCALER) | RTC_MODE0_CTRLA_COUNTSYNC);
7ac: 6820 ldr r0, [r4, #0]
}
static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data)
{
RTC_CRITICAL_SECTION_ENTER();
((Rtc *)hw)->MODE0.CTRLA.reg = data;
7ae: f44f 4301 mov.w r3, #33024 ; 0x8100
7b2: 8003 strh r3, [r0, #0]
hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC);
7b4: f248 0103 movw r1, #32771 ; 0x8003
7b8: 4790 blx r2
hri_rtc_write_TAMPCTRL_reg(
dev->hw,
7ba: 6823 ldr r3, [r4, #0]
}
static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data)
{
RTC_CRITICAL_SECTION_ENTER();
((Rtc *)hw)->MODE0.TAMPCTRL.reg = data;
7bc: 2000 movs r0, #0
7be: 6618 str r0, [r3, #96] ; 0x60
| (CONF_RTC_TAMPER_INACT_2 == TAMPER_MODE_ACTL) | (CONF_RTC_TAMPER_INACT_3 == TAMPER_MODE_ACTL)
| (CONF_RTC_TAMPER_INACT_4 == TAMPER_MODE_ACTL)) {
hri_rtcmode0_set_CTRLB_RTCOUT_bit(dev->hw);
}
return ERR_NONE;
}
7c0: bd10 pop {r4, pc}
7c2: bf00 nop
7c4: 00000e66 .word 0x00000e66
7c8: 00000459 .word 0x00000459
7cc: 2000002c .word 0x2000002c
7d0: 00000751 .word 0x00000751
000007d4 <RTC_Handler>:
/**
* \brief Rtc interrupt handler
*/
void RTC_Handler(void)
{
_rtc_interrupt_handler(_rtc_dev);
7d4: 4b0d ldr r3, [pc, #52] ; (80c <RTC_Handler+0x38>)
{
7d6: b510 push {r4, lr}
_rtc_interrupt_handler(_rtc_dev);
7d8: 681c ldr r4, [r3, #0]
uint16_t interrupt_status = hri_rtcmode0_read_INTFLAG_reg(dev->hw);
7da: 6822 ldr r2, [r4, #0]
return ((Rtc *)hw)->MODE0.INTFLAG.reg;
7dc: 8991 ldrh r1, [r2, #12]
return ((Rtc *)hw)->MODE0.INTENSET.reg;
7de: 8953 ldrh r3, [r2, #10]
7e0: b29b uxth r3, r3
if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_ALARM0) {
7e2: 400b ands r3, r1
7e4: 05da lsls r2, r3, #23
7e6: d507 bpl.n 7f8 <RTC_Handler+0x24>
dev->callback(dev);
7e8: 6863 ldr r3, [r4, #4]
7ea: 4620 mov r0, r4
7ec: 4798 blx r3
hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw);
7ee: 6823 ldr r3, [r4, #0]
((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0;
7f0: f44f 7280 mov.w r2, #256 ; 0x100
((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
7f4: 819a strh r2, [r3, #12]
}
7f6: bd10 pop {r4, pc}
} else if ((interrupt_status & interrupt_enabled) & RTC_MODE2_INTFLAG_TAMPER) {
7f8: 045b lsls r3, r3, #17
7fa: d5fc bpl.n 7f6 <RTC_Handler+0x22>
dev->callback_tamper(dev);
7fc: 68a3 ldr r3, [r4, #8]
7fe: 4620 mov r0, r4
800: 4798 blx r3
hri_rtcmode0_clear_interrupt_TAMPER_bit(dev->hw);
802: 6823 ldr r3, [r4, #0]
804: f44f 4280 mov.w r2, #16384 ; 0x4000
808: e7f4 b.n 7f4 <RTC_Handler+0x20>
80a: bf00 nop
80c: 2000002c .word 0x2000002c
00000810 <gpio_set_pin_direction>:
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
{
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
810: f000 031f and.w r3, r0, #31
{
814: b530 push {r4, r5, lr}
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
816: 2501 movs r5, #1
818: 409d lsls r5, r3
((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data;
}
static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
{
((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
81a: 0940 lsrs r0, r0, #5
81c: 4b0d ldr r3, [pc, #52] ; (854 <gpio_set_pin_direction+0x44>)
81e: 01c0 lsls r0, r0, #7
* \brief Set direction on port with mask
*/
static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
const enum gpio_direction direction)
{
switch (direction) {
820: 2902 cmp r1, #2
PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16));
break;
case GPIO_DIRECTION_IN:
hri_port_clear_DIR_reg(PORT, port, mask);
hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff));
822: b2ac uxth r4, r5
hri_port_write_WRCONFIG_reg(PORT,
port,
PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN
| ((mask & 0xffff0000) >> 16));
824: ea4f 4215 mov.w r2, r5, lsr #16
((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
828: 4403 add r3, r0
switch (direction) {
82a: d00b beq.n 844 <gpio_set_pin_direction+0x34>
hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff));
82c: f044 4480 orr.w r4, r4, #1073741824 ; 0x40000000
830: f444 3400 orr.w r4, r4, #131072 ; 0x20000
hri_port_write_WRCONFIG_reg(PORT,
834: f042 4240 orr.w r2, r2, #3221225472 ; 0xc0000000
((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask;
838: 605d str r5, [r3, #4]
83a: f442 3200 orr.w r2, r2, #131072 ; 0x20000
static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
hri_port_wrconfig_reg_t data)
{
PORT_CRITICAL_SECTION_ENTER();
((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
83e: 629c str r4, [r3, #40] ; 0x28
840: 629a str r2, [r3, #40] ; 0x28
}
842: bd30 pop {r4, r5, pc}
break;
case GPIO_DIRECTION_OUT:
hri_port_set_DIR_reg(PORT, port, mask);
hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff));
844: f044 4480 orr.w r4, r4, #1073741824 ; 0x40000000
((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
848: 609d str r5, [r3, #8]
hri_port_write_WRCONFIG_reg(
84a: f042 4240 orr.w r2, r2, #3221225472 ; 0xc0000000
((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
84e: 629c str r4, [r3, #40] ; 0x28
850: e7f6 b.n 840 <gpio_set_pin_direction+0x30>
852: bf00 nop
854: 41008000 .word 0x41008000
00000858 <gpio_set_pin_pull_mode.constprop.0>:
((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN;
858: 0942 lsrs r2, r0, #5
85a: f000 031f and.w r3, r0, #31
85e: eb03 13c2 add.w r3, r3, r2, lsl #7
862: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000
866: f503 4300 add.w r3, r3, #32768 ; 0x8000
86a: f893 2040 ldrb.w r2, [r3, #64] ; 0x40
86e: f002 02fb and.w r2, r2, #251 ; 0xfb
872: f883 2040 strb.w r2, [r3, #64] ; 0x40
}
876: 4770 bx lr
00000878 <_gpio_set_pin_function>:
/**
* \brief Set gpio pin function
*/
static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function)
{
uint8_t port = GPIO_PORT(gpio);
878: 0943 lsrs r3, r0, #5
tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
87a: 01db lsls r3, r3, #7
87c: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000
{
880: b530 push {r4, r5, lr}
882: f503 4300 add.w r3, r3, #32768 ; 0x8000
uint8_t pin = GPIO_PIN(gpio);
886: f000 041f and.w r4, r0, #31
88a: 191d adds r5, r3, r4
88c: eb03 0354 add.w r3, r3, r4, lsr #1
890: f895 2040 ldrb.w r2, [r5, #64] ; 0x40
tmp &= ~PORT_PINCFG_PMUXEN;
894: f002 02fe and.w r2, r2, #254 ; 0xfe
tmp |= value << PORT_PINCFG_PMUXEN_Pos;
898: f042 0201 orr.w r2, r2, #1
((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
89c: f885 2040 strb.w r2, [r5, #64] ; 0x40
} else {
hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true);
if (pin & 1) {
// Odd numbered pin
hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff);
8a0: b2ca uxtb r2, r1
tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
8a2: f893 1030 ldrb.w r1, [r3, #48] ; 0x30
if (pin & 1) {
8a6: f010 0f01 tst.w r0, #1
tmp &= ~PORT_PMUX_PMUXO_Msk;
8aa: bf1b ittet ne
8ac: f001 010f andne.w r1, r1, #15
tmp |= PORT_PMUX_PMUXO(data);
8b0: ea41 1102 orrne.w r1, r1, r2, lsl #4
tmp &= ~PORT_PMUX_PMUXE_Msk;
8b4: f001 01f0 andeq.w r1, r1, #240 ; 0xf0
tmp |= PORT_PMUX_PMUXO(data);
8b8: b2c9 uxtbne r1, r1
tmp |= PORT_PMUX_PMUXE(data);
8ba: bf08 it eq
8bc: 4311 orreq r1, r2
((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
8be: f883 1030 strb.w r1, [r3, #48] ; 0x30
} else {
// Even numbered pin
hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff);
}
}
}
8c2: bd30 pop {r4, r5, pc}
000008c4 <CALENDER_INTERFACE_CLOCK_init>:
}
static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw)
{
MCLK_CRITICAL_SECTION_ENTER();
((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC;
8c4: 4a02 ldr r2, [pc, #8] ; (8d0 <CALENDER_INTERFACE_CLOCK_init+0xc>)
8c6: 6953 ldr r3, [r2, #20]
8c8: f443 7300 orr.w r3, r3, #512 ; 0x200
8cc: 6153 str r3, [r2, #20]
struct mci_sync_desc IO_BUS;
void CALENDER_INTERFACE_CLOCK_init(void)
{
hri_mclk_set_APBAMASK_RTC_bit(MCLK);
}
8ce: 4770 bx lr
8d0: 40000800 .word 0x40000800
000008d4 <CALENDER_INTERFACE_init>:
void CALENDER_INTERFACE_init(void)
{
8d4: b510 push {r4, lr}
CALENDER_INTERFACE_CLOCK_init();
8d6: 4b04 ldr r3, [pc, #16] ; (8e8 <CALENDER_INTERFACE_init+0x14>)
calendar_init(&CALENDER_INTERFACE, RTC);
8d8: 4904 ldr r1, [pc, #16] ; (8ec <CALENDER_INTERFACE_init+0x18>)
8da: 4805 ldr r0, [pc, #20] ; (8f0 <CALENDER_INTERFACE_init+0x1c>)
CALENDER_INTERFACE_CLOCK_init();
8dc: 4798 blx r3
}
8de: e8bd 4010 ldmia.w sp!, {r4, lr}
calendar_init(&CALENDER_INTERFACE, RTC);
8e2: 4b04 ldr r3, [pc, #16] ; (8f4 <CALENDER_INTERFACE_init+0x20>)
8e4: 4718 bx r3
8e6: bf00 nop
8e8: 000008c5 .word 0x000008c5
8ec: 40002400 .word 0x40002400
8f0: 20000030 .word 0x20000030
8f4: 000002a5 .word 0x000002a5
000008f8 <USART_0_PORT_init>:
void USART_0_PORT_init(void)
{
8f8: b510 push {r4, lr}
_gpio_set_pin_function(pin, function);
8fa: 4c05 ldr r4, [pc, #20] ; (910 <USART_0_PORT_init+0x18>)
8fc: 4905 ldr r1, [pc, #20] ; (914 <USART_0_PORT_init+0x1c>)
8fe: 2004 movs r0, #4
900: 47a0 blx r4
902: 4623 mov r3, r4
904: 4904 ldr r1, [pc, #16] ; (918 <USART_0_PORT_init+0x20>)
gpio_set_pin_function(DBG_TX, PINMUX_PA04D_SERCOM0_PAD0);
gpio_set_pin_function(DBG_RX, PINMUX_PA05D_SERCOM0_PAD1);
}
906: e8bd 4010 ldmia.w sp!, {r4, lr}
90a: 2005 movs r0, #5
90c: 4718 bx r3
90e: bf00 nop
910: 00000879 .word 0x00000879
914: 00040003 .word 0x00040003
918: 00050003 .word 0x00050003
0000091c <USART_0_CLOCK_init>:
}
static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
{
GCLK_CRITICAL_SECTION_ENTER();
((Gclk *)hw)->PCHCTRL[index].reg = data;
91c: 4b06 ldr r3, [pc, #24] ; (938 <USART_0_CLOCK_init+0x1c>)
91e: 2240 movs r2, #64 ; 0x40
920: f8c3 209c str.w r2, [r3, #156] ; 0x9c
924: 2243 movs r2, #67 ; 0x43
926: f8c3 208c str.w r2, [r3, #140] ; 0x8c
}
static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw)
{
MCLK_CRITICAL_SECTION_ENTER();
((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0;
92a: 4a04 ldr r2, [pc, #16] ; (93c <USART_0_CLOCK_init+0x20>)
92c: 6953 ldr r3, [r2, #20]
92e: f443 5380 orr.w r3, r3, #4096 ; 0x1000
932: 6153 str r3, [r2, #20]
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK);
}
934: 4770 bx lr
936: bf00 nop
938: 40001c00 .word 0x40001c00
93c: 40000800 .word 0x40000800
00000940 <USART_0_init>:
void USART_0_init(void)
{
940: b510 push {r4, lr}
USART_0_CLOCK_init();
942: 4b05 ldr r3, [pc, #20] ; (958 <USART_0_init+0x18>)
usart_sync_init(&USART_0, SERCOM0, (void *)NULL);
944: 4905 ldr r1, [pc, #20] ; (95c <USART_0_init+0x1c>)
946: 4806 ldr r0, [pc, #24] ; (960 <USART_0_init+0x20>)
USART_0_CLOCK_init();
948: 4798 blx r3
usart_sync_init(&USART_0, SERCOM0, (void *)NULL);
94a: 4b06 ldr r3, [pc, #24] ; (964 <USART_0_init+0x24>)
94c: 2200 movs r2, #0
94e: 4798 blx r3
USART_0_PORT_init();
}
950: e8bd 4010 ldmia.w sp!, {r4, lr}
USART_0_PORT_init();
954: 4b04 ldr r3, [pc, #16] ; (968 <USART_0_init+0x28>)
956: 4718 bx r3
958: 0000091d .word 0x0000091d
95c: 40003000 .word 0x40003000
960: 20000050 .word 0x20000050
964: 0000060d .word 0x0000060d
968: 000008f9 .word 0x000008f9
0000096c <SPI_0_PORT_init>:
void SPI_0_PORT_init(void)
{
96c: b570 push {r4, r5, r6, lr}
((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask;
96e: 4e12 ldr r6, [pc, #72] ; (9b8 <SPI_0_PORT_init+0x4c>)
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(PC16, GPIO_DIRECTION_OUT);
970: 4d12 ldr r5, [pc, #72] ; (9bc <SPI_0_PORT_init+0x50>)
972: 4c13 ldr r4, [pc, #76] ; (9c0 <SPI_0_PORT_init+0x54>)
974: f44f 3380 mov.w r3, #65536 ; 0x10000
978: f8c6 3114 str.w r3, [r6, #276] ; 0x114
97c: 2102 movs r1, #2
97e: 2050 movs r0, #80 ; 0x50
980: 47a8 blx r5
982: f501 01a0 add.w r1, r1, #5242880 ; 0x500000
986: 2050 movs r0, #80 ; 0x50
988: 47a0 blx r4
98a: f44f 3300 mov.w r3, #131072 ; 0x20000
98e: f8c6 3114 str.w r3, [r6, #276] ; 0x114
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(PC17, GPIO_DIRECTION_OUT);
992: 2102 movs r1, #2
994: 2051 movs r0, #81 ; 0x51
996: 47a8 blx r5
998: f501 01a2 add.w r1, r1, #5308416 ; 0x510000
99c: 2051 movs r0, #81 ; 0x51
99e: 47a0 blx r4
gpio_set_pin_function(PC17, PINMUX_PC17C_SERCOM6_PAD1);
// Set pin direction to input
gpio_set_pin_direction(PC18, GPIO_DIRECTION_IN);
9a0: 2101 movs r1, #1
9a2: 2052 movs r0, #82 ; 0x52
9a4: 47a8 blx r5
gpio_set_pin_pull_mode(PC18,
9a6: 4b07 ldr r3, [pc, #28] ; (9c4 <SPI_0_PORT_init+0x58>)
9a8: 4907 ldr r1, [pc, #28] ; (9c8 <SPI_0_PORT_init+0x5c>)
9aa: 2052 movs r0, #82 ; 0x52
9ac: 4798 blx r3
9ae: 4623 mov r3, r4
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(PC18, PINMUX_PC18C_SERCOM6_PAD2);
}
9b0: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
9b4: 4718 bx r3
9b6: bf00 nop
9b8: 41008000 .word 0x41008000
9bc: 00000811 .word 0x00000811
9c0: 00000879 .word 0x00000879
9c4: 00000859 .word 0x00000859
9c8: 00520002 .word 0x00520002
000009cc <SPI_0_CLOCK_init>:
9cc: 4b06 ldr r3, [pc, #24] ; (9e8 <SPI_0_CLOCK_init+0x1c>)
9ce: 2240 movs r2, #64 ; 0x40
9d0: f8c3 2110 str.w r2, [r3, #272] ; 0x110
9d4: 2243 movs r2, #67 ; 0x43
9d6: f8c3 208c str.w r2, [r3, #140] ; 0x8c
}
static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw)
{
MCLK_CRITICAL_SECTION_ENTER();
((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6;
9da: 4a04 ldr r2, [pc, #16] ; (9ec <SPI_0_CLOCK_init+0x20>)
9dc: 6a13 ldr r3, [r2, #32]
9de: f043 0304 orr.w r3, r3, #4
9e2: 6213 str r3, [r2, #32]
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM6_GCLK_ID_CORE, CONF_GCLK_SERCOM6_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM6_GCLK_ID_SLOW, CONF_GCLK_SERCOM6_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBDMASK_SERCOM6_bit(MCLK);
}
9e4: 4770 bx lr
9e6: bf00 nop
9e8: 40001c00 .word 0x40001c00
9ec: 40000800 .word 0x40000800
000009f0 <SPI_0_init>:
void SPI_0_init(void)
{
9f0: b510 push {r4, lr}
SPI_0_CLOCK_init();
9f2: 4b05 ldr r3, [pc, #20] ; (a08 <SPI_0_init+0x18>)
spi_m_sync_init(&SPI_0, SERCOM6);
9f4: 4905 ldr r1, [pc, #20] ; (a0c <SPI_0_init+0x1c>)
9f6: 4806 ldr r0, [pc, #24] ; (a10 <SPI_0_init+0x20>)
SPI_0_CLOCK_init();
9f8: 4798 blx r3
spi_m_sync_init(&SPI_0, SERCOM6);
9fa: 4b06 ldr r3, [pc, #24] ; (a14 <SPI_0_init+0x24>)
9fc: 4798 blx r3
SPI_0_PORT_init();
}
9fe: e8bd 4010 ldmia.w sp!, {r4, lr}
SPI_0_PORT_init();
a02: 4b05 ldr r3, [pc, #20] ; (a18 <SPI_0_init+0x28>)
a04: 4718 bx r3
a06: bf00 nop
a08: 000009cd .word 0x000009cd
a0c: 43000800 .word 0x43000800
a10: 2000005c .word 0x2000005c
a14: 000002e9 .word 0x000002e9
a18: 0000096d .word 0x0000096d
00000a1c <system_init>:
mci_sync_init(&IO_BUS, SDHC0);
IO_BUS_PORT_init();
}
void system_init(void)
{
a1c: b510 push {r4, lr}
* Currently the following initialization functions are supported:
* - System clock initialization
*/
static inline void init_mcu(void)
{
_init_chip();
a1e: 4b05 ldr r3, [pc, #20] ; (a34 <system_init+0x18>)
a20: 4798 blx r3
init_mcu();
CALENDER_INTERFACE_init();
a22: 4b05 ldr r3, [pc, #20] ; (a38 <system_init+0x1c>)
a24: 4798 blx r3
USART_0_init();
a26: 4b05 ldr r3, [pc, #20] ; (a3c <system_init+0x20>)
a28: 4798 blx r3
SPI_0_init();
//IO_BUS_init();
}
a2a: e8bd 4010 ldmia.w sp!, {r4, lr}
SPI_0_init();
a2e: 4b04 ldr r3, [pc, #16] ; (a40 <system_init+0x24>)
a30: 4718 bx r3
a32: bf00 nop
a34: 000003e1 .word 0x000003e1
a38: 000008d5 .word 0x000008d5
a3c: 00000941 .word 0x00000941
a40: 000009f1 .word 0x000009f1
00000a44 <hri_sercomspi_wait_for_sync>:
return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg;
}
static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg)
{
while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) {
a44: 69c3 ldr r3, [r0, #28]
a46: 420b tst r3, r1
a48: d1fc bne.n a44 <hri_sercomspi_wait_for_sync>
};
}
a4a: 4770 bx lr
00000a4c <hri_sercomusart_wait_for_sync>:
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
}
static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg)
{
while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) {
a4c: 69c3 ldr r3, [r0, #28]
a4e: 420b tst r3, r1
a50: d1fc bne.n a4c <hri_sercomusart_wait_for_sync>
};
}
a52: 4770 bx lr
00000a54 <hri_sercomspi_clear_CTRLA_ENABLE_bit>:
}
static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
a54: 6802 ldr r2, [r0, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
a56: 4b03 ldr r3, [pc, #12] ; (a64 <hri_sercomspi_clear_CTRLA_ENABLE_bit+0x10>)
((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
a58: f022 0202 bic.w r2, r2, #2
a5c: 6002 str r2, [r0, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
a5e: 2103 movs r1, #3
a60: 4718 bx r3
a62: bf00 nop
a64: 00000a45 .word 0x00000a45
00000a68 <hri_sercomusart_clear_CTRLA_ENABLE_bit>:
}
static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
a68: 6802 ldr r2, [r0, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
a6a: 4b03 ldr r3, [pc, #12] ; (a78 <hri_sercomusart_clear_CTRLA_ENABLE_bit+0x10>)
((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
a6c: f022 0202 bic.w r2, r2, #2
a70: 6002 str r2, [r0, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
a72: 2103 movs r1, #3
a74: 4718 bx r3
a76: bf00 nop
a78: 00000a4d .word 0x00000a4d
00000a7c <_sercom_get_hardware_index>:
/**
* \brief Retrieve ordinal number of the given sercom hardware instance
*/
static uint8_t _sercom_get_hardware_index(const void *const hw)
{
a7c: b570 push {r4, r5, r6, lr}
Sercom *const sercom_modules[] = SERCOM_INSTS;
a7e: 4d0c ldr r5, [pc, #48] ; (ab0 <_sercom_get_hardware_index+0x34>)
{
a80: 4606 mov r6, r0
Sercom *const sercom_modules[] = SERCOM_INSTS;
a82: cd0f ldmia r5!, {r0, r1, r2, r3}
{
a84: b088 sub sp, #32
Sercom *const sercom_modules[] = SERCOM_INSTS;
a86: 466c mov r4, sp
a88: c40f stmia r4!, {r0, r1, r2, r3}
a8a: e895 000f ldmia.w r5, {r0, r1, r2, r3}
a8e: e884 000f stmia.w r4, {r0, r1, r2, r3}
/* Find index for SERCOM instance. */
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
a92: 466a mov r2, sp
a94: 2300 movs r3, #0
if ((uint32_t)hw == (uint32_t)sercom_modules[i]) {
a96: f852 1b04 ldr.w r1, [r2], #4
a9a: 42b1 cmp r1, r6
a9c: d102 bne.n aa4 <_sercom_get_hardware_index+0x28>
return i;
a9e: b2d8 uxtb r0, r3
}
}
return 0;
}
aa0: b008 add sp, #32
aa2: bd70 pop {r4, r5, r6, pc}
for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
aa4: 3301 adds r3, #1
aa6: 2b08 cmp r3, #8
aa8: d1f5 bne.n a96 <_sercom_get_hardware_index+0x1a>
return 0;
aaa: 2000 movs r0, #0
aac: e7f8 b.n aa0 <_sercom_get_hardware_index+0x24>
aae: bf00 nop
ab0: 00000e98 .word 0x00000e98
00000ab4 <_usart_init>:
* \param[in] hw The pointer to hardware instance
*
* \return The status of initialization
*/
static int32_t _usart_init(void *const hw)
{
ab4: b538 push {r3, r4, r5, lr}
uint8_t sercom_offset = _sercom_get_hardware_index(hw);
ab6: 4b1a ldr r3, [pc, #104] ; (b20 <_usart_init+0x6c>)
{
ab8: 4604 mov r4, r0
uint8_t sercom_offset = _sercom_get_hardware_index(hw);
aba: 4798 blx r3
if (_usarts[i].number == sercom_offset) {
abc: b128 cbz r0, aca <_usart_init+0x16>
ASSERT(false);
abe: 4919 ldr r1, [pc, #100] ; (b24 <_usart_init+0x70>)
ac0: 4b19 ldr r3, [pc, #100] ; (b28 <_usart_init+0x74>)
ac2: f240 2247 movw r2, #583 ; 0x247
ac6: 2000 movs r0, #0
ac8: 4798 blx r3
return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg;
aca: 69e3 ldr r3, [r4, #28]
acc: 4d17 ldr r5, [pc, #92] ; (b2c <_usart_init+0x78>)
uint8_t i = _get_sercom_index(hw);
if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) {
ace: f013 0f01 tst.w r3, #1
ad2: d10e bne.n af2 <_usart_init+0x3e>
static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw,
hri_sercomusart_ctrla_reg_t mask)
{
uint32_t tmp;
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
ad4: 2103 movs r1, #3
ad6: 4620 mov r0, r4
ad8: 47a8 blx r5
tmp = ((Sercom *)hw)->USART.CTRLA.reg;
ada: 6823 ldr r3, [r4, #0]
uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk;
if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) {
adc: 079b lsls r3, r3, #30
ade: d503 bpl.n ae8 <_usart_init+0x34>
hri_sercomusart_clear_CTRLA_ENABLE_bit(hw);
ae0: 4b13 ldr r3, [pc, #76] ; (b30 <_usart_init+0x7c>)
ae2: 4798 blx r3
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE);
ae4: 2102 movs r1, #2
ae6: 47a8 blx r5
}
static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLA.reg = data;
ae8: 2305 movs r3, #5
aea: 6023 str r3, [r4, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
aec: 2103 movs r1, #3
aee: 4620 mov r0, r4
af0: 47a8 blx r5
}
hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode);
}
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST);
af2: 4620 mov r0, r4
af4: 2101 movs r1, #1
af6: 47a8 blx r5
((Sercom *)hw)->USART.CTRLA.reg = data;
af8: 4b0e ldr r3, [pc, #56] ; (b34 <_usart_init+0x80>)
afa: 6023 str r3, [r4, #0]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE);
afc: 2103 movs r1, #3
afe: 47a8 blx r5
}
static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLB.reg = data;
b00: f44f 3340 mov.w r3, #196608 ; 0x30000
b04: 6063 str r3, [r4, #4]
hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK);
b06: 211f movs r1, #31
b08: 47a8 blx r5
}
static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.CTRLC.reg = data;
b0a: 4b0b ldr r3, [pc, #44] ; (b38 <_usart_init+0x84>)
b0c: 60a3 str r3, [r4, #8]
}
static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.BAUD.reg = data;
b0e: f64f 43b9 movw r3, #64697 ; 0xfcb9
b12: 81a3 strh r3, [r4, #12]
}
static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.RXPL.reg = data;
b14: 2300 movs r3, #0
b16: 73a3 strb r3, [r4, #14]
hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl);
hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl);
return ERR_NONE;
}
b18: 4618 mov r0, r3
}
static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->USART.DBGCTRL.reg = data;
b1a: f884 3030 strb.w r3, [r4, #48] ; 0x30
b1e: bd38 pop {r3, r4, r5, pc}
b20: 00000a7d .word 0x00000a7d
b24: 00000e7b .word 0x00000e7b
b28: 00000459 .word 0x00000459
b2c: 00000a4d .word 0x00000a4d
b30: 00000a69 .word 0x00000a69
b34: 40100004 .word 0x40100004
b38: 00700002 .word 0x00700002
00000b3c <_usart_sync_init>:
{
b3c: b570 push {r4, r5, r6, lr}
ASSERT(device);
b3e: 4605 mov r5, r0
b40: 3800 subs r0, #0
{
b42: 460c mov r4, r1
ASSERT(device);
b44: 4b05 ldr r3, [pc, #20] ; (b5c <_usart_sync_init+0x20>)
b46: 4906 ldr r1, [pc, #24] ; (b60 <_usart_sync_init+0x24>)
b48: bf18 it ne
b4a: 2001 movne r0, #1
b4c: 22bb movs r2, #187 ; 0xbb
b4e: 4798 blx r3
device->hw = hw;
b50: 602c str r4, [r5, #0]
return _usart_init(hw);
b52: 4620 mov r0, r4
b54: 4b03 ldr r3, [pc, #12] ; (b64 <_usart_sync_init+0x28>)
}
b56: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
return _usart_init(hw);
b5a: 4718 bx r3
b5c: 00000459 .word 0x00000459
b60: 00000e7b .word 0x00000e7b
b64: 00000ab5 .word 0x00000ab5
00000b68 <_usart_sync_write_byte>:
hri_sercomusart_write_DATA_reg(device->hw, data);
b68: 6803 ldr r3, [r0, #0]
((Sercom *)hw)->USART.DATA.reg = data;
b6a: 6299 str r1, [r3, #40] ; 0x28
}
b6c: 4770 bx lr
00000b6e <_usart_sync_read_byte>:
return hri_sercomusart_read_DATA_reg(device->hw);
b6e: 6803 ldr r3, [r0, #0]
return ((Sercom *)hw)->USART.DATA.reg;
b70: 6a98 ldr r0, [r3, #40] ; 0x28
}
b72: b2c0 uxtb r0, r0
b74: 4770 bx lr
00000b76 <_usart_sync_is_ready_to_send>:
return hri_sercomusart_get_interrupt_DRE_bit(device->hw);
b76: 6803 ldr r3, [r0, #0]
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos;
b78: 7e18 ldrb r0, [r3, #24]
}
b7a: f000 0001 and.w r0, r0, #1
b7e: 4770 bx lr
00000b80 <_usart_sync_is_transmit_done>:
return hri_sercomusart_get_interrupt_TXC_bit(device->hw);
b80: 6803 ldr r3, [r0, #0]
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos;
b82: 7e18 ldrb r0, [r3, #24]
}
b84: f3c0 0040 ubfx r0, r0, #1, #1
b88: 4770 bx lr
00000b8a <_usart_sync_is_byte_received>:
return hri_sercomusart_get_interrupt_RXC_bit(device->hw);
b8a: 6803 ldr r3, [r0, #0]
return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos;
b8c: 7e18 ldrb r0, [r3, #24]
}
b8e: f3c0 0080 ubfx r0, r0, #2, #1
b92: 4770 bx lr
00000b94 <_spi_m_sync_init>:
return NULL;
}
int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw)
{
b94: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
b98: 4b44 ldr r3, [pc, #272] ; (cac <_spi_m_sync_init+0x118>)
return NULL;
b9a: 4d45 ldr r5, [pc, #276] ; (cb0 <_spi_m_sync_init+0x11c>)
{
b9c: 4607 mov r7, r0
uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
b9e: 4608 mov r0, r1
{
ba0: 460c mov r4, r1
uint8_t n = _sercom_get_hardware_index((const void *)hw_addr);
ba2: 4798 blx r3
return NULL;
ba4: 2806 cmp r0, #6
ba6: bf18 it ne
ba8: 2500 movne r5, #0
const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw);
ASSERT(dev && hw);
baa: 2f00 cmp r7, #0
bac: d05d beq.n c6a <_spi_m_sync_init+0xd6>
bae: 1e20 subs r0, r4, #0
bb0: bf18 it ne
bb2: 2001 movne r0, #1
bb4: 4e3f ldr r6, [pc, #252] ; (cb4 <_spi_m_sync_init+0x120>)
bb6: 4940 ldr r1, [pc, #256] ; (cb8 <_spi_m_sync_init+0x124>)
bb8: f640 123f movw r2, #2367 ; 0x93f
bbc: 47b0 blx r6
if (regs == NULL) {
bbe: 46b0 mov r8, r6
bc0: 2d00 cmp r5, #0
bc2: d070 beq.n ca6 <_spi_m_sync_init+0x112>
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
bc4: 69e3 ldr r3, [r4, #28]
bc6: 4e3d ldr r6, [pc, #244] ; (cbc <_spi_m_sync_init+0x128>)
return ERR_INVALID_ARG;
}
if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) {
bc8: f013 0f01 tst.w r3, #1
bcc: d113 bne.n bf6 <_spi_m_sync_init+0x62>
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
bce: 2103 movs r1, #3
bd0: 4620 mov r0, r4
uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
bd2: f8d5 9000 ldr.w r9, [r5]
bd6: 47b0 blx r6
tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
bd8: 6823 ldr r3, [r4, #0]
if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
bda: 079b lsls r3, r3, #30
uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk;
bdc: f009 091c and.w r9, r9, #28
if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) {
be0: d503 bpl.n bea <_spi_m_sync_init+0x56>
hri_sercomspi_clear_CTRLA_ENABLE_bit(hw);
be2: 4b37 ldr r3, [pc, #220] ; (cc0 <_spi_m_sync_init+0x12c>)
be4: 4798 blx r3
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE);
be6: 2102 movs r1, #2
be8: 47b0 blx r6
}
hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode);
bea: f049 0301 orr.w r3, r9, #1
((Sercom *)hw)->SPI.CTRLA.reg = data;
bee: 6023 str r3, [r4, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
bf0: 2103 movs r1, #3
bf2: 4620 mov r0, r4
bf4: 47b0 blx r6
}
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST);
bf6: 2101 movs r1, #1
bf8: 4620 mov r0, r4
bfa: 47b0 blx r6
dev->prvt = hw;
if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) {
bfc: 682b ldr r3, [r5, #0]
bfe: f8df 90c4 ldr.w r9, [pc, #196] ; cc4 <_spi_m_sync_init+0x130>
dev->prvt = hw;
c02: 603c str r4, [r7, #0]
if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) {
c04: f003 031c and.w r3, r3, #28
c08: 2b08 cmp r3, #8
c0a: d130 bne.n c6e <_spi_m_sync_init+0xda>
ASSERT(hw && regs);
c0c: 492a ldr r1, [pc, #168] ; (cb8 <_spi_m_sync_init+0x124>)
c0e: 2001 movs r0, #1
c10: f640 121d movw r2, #2333 ; 0x91d
c14: 47c0 blx r8
hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
c16: 682b ldr r3, [r5, #0]
hri_sercomspi_write_CTRLA_reg(
c18: ea03 0309 and.w r3, r3, r9
((Sercom *)hw)->SPI.CTRLA.reg = data;
c1c: 6023 str r3, [r4, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
c1e: 2103 movs r1, #3
c20: 4620 mov r0, r4
c22: 47b0 blx r6
(regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN))
c24: 686b ldr r3, [r5, #4]
| (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN));
c26: f423 3308 bic.w r3, r3, #139264 ; 0x22000
c2a: f423 7310 bic.w r3, r3, #576 ; 0x240
hri_sercomspi_write_CTRLB_reg(hw,
c2e: f443 3300 orr.w r3, r3, #131072 ; 0x20000
c32: f443 7310 orr.w r3, r3, #576 ; 0x240
((Sercom *)hw)->SPI.CTRLB.reg = data;
c36: 6063 str r3, [r4, #4]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
c38: 2117 movs r1, #23
c3a: 47b0 blx r6
hri_sercomspi_write_ADDR_reg(hw, regs->addr);
c3c: 68ab ldr r3, [r5, #8]
((Sercom *)hw)->SPI.ADDR.reg = data;
c3e: 6263 str r3, [r4, #36] ; 0x24
hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
c40: 7b6b ldrb r3, [r5, #13]
((Sercom *)hw)->SPI.DBGCTRL.reg = data;
c42: f884 3030 strb.w r3, [r4, #48] ; 0x30
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
c46: 69e3 ldr r3, [r4, #28]
while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF))
c48: 2b00 cmp r3, #0
c4a: d1fc bne.n c46 <_spi_m_sync_init+0xb2>
} else {
_spi_load_regs_master(hw, regs);
}
/* Load character size from default hardware configuration */
dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2;
c4c: 686b ldr r3, [r5, #4]
c4e: f013 0f07 tst.w r3, #7
c52: bf0c ite eq
c54: 2301 moveq r3, #1
c56: 2302 movne r3, #2
c58: 713b strb r3, [r7, #4]
dev->dummy_byte = regs->dummy_byte;
c5a: 7bab ldrb r3, [r5, #14]
c5c: 7bea ldrb r2, [r5, #15]
c5e: ea43 2302 orr.w r3, r3, r2, lsl #8
c62: 80fb strh r3, [r7, #6]
return ERR_NONE;
c64: 2000 movs r0, #0
}
c66: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
ASSERT(dev && hw);
c6a: 4638 mov r0, r7
c6c: e7a2 b.n bb4 <_spi_m_sync_init+0x20>
ASSERT(hw && regs);
c6e: 4912 ldr r1, [pc, #72] ; (cb8 <_spi_m_sync_init+0x124>)
c70: 2001 movs r0, #1
c72: f640 1209 movw r2, #2313 ; 0x909
c76: 47c0 blx r8
hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST));
c78: 682b ldr r3, [r5, #0]
hri_sercomspi_write_CTRLA_reg(
c7a: ea03 0309 and.w r3, r3, r9
((Sercom *)hw)->SPI.CTRLA.reg = data;
c7e: 6023 str r3, [r4, #0]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
c80: 2103 movs r1, #3
c82: 4620 mov r0, r4
c84: 47b0 blx r6
(regs->ctrlb
c86: 686b ldr r3, [r5, #4]
| (SERCOM_SPI_CTRLB_RXEN));
c88: f423 3338 bic.w r3, r3, #188416 ; 0x2e000
c8c: f423 7310 bic.w r3, r3, #576 ; 0x240
hri_sercomspi_write_CTRLB_reg(
c90: f443 3300 orr.w r3, r3, #131072 ; 0x20000
((Sercom *)hw)->SPI.CTRLB.reg = data;
c94: 6063 str r3, [r4, #4]
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK);
c96: 2117 movs r1, #23
c98: 47b0 blx r6
hri_sercomspi_write_BAUD_reg(hw, regs->baud);
c9a: 7b2b ldrb r3, [r5, #12]
((Sercom *)hw)->SPI.BAUD.reg = data;
c9c: 7323 strb r3, [r4, #12]
hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl);
c9e: 7b6b ldrb r3, [r5, #13]
((Sercom *)hw)->SPI.DBGCTRL.reg = data;
ca0: f884 3030 strb.w r3, [r4, #48] ; 0x30
}
ca4: e7d2 b.n c4c <_spi_m_sync_init+0xb8>
return ERR_INVALID_ARG;
ca6: f06f 000c mvn.w r0, #12
caa: e7dc b.n c66 <_spi_m_sync_init+0xd2>
cac: 00000a7d .word 0x00000a7d
cb0: 00000ed0 .word 0x00000ed0
cb4: 00000459 .word 0x00000459
cb8: 00000e7b .word 0x00000e7b
cbc: 00000a45 .word 0x00000a45
cc0: 00000a55 .word 0x00000a55
cc4: fffffefc .word 0xfffffefc
00000cc8 <_spi_m_sync_trans>:
return ERR_NONE;
}
int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg)
{
cc8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
void * hw = dev->prvt;
ccc: 6804 ldr r4, [r0, #0]
int32_t rc = 0;
struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
cce: f890 8004 ldrb.w r8, [r0, #4]
ASSERT(dev && hw);
cd2: 4b2a ldr r3, [pc, #168] ; (d7c <_spi_m_sync_trans+0xb4>)
{
cd4: 4607 mov r7, r0
ASSERT(dev && hw);
cd6: 1e20 subs r0, r4, #0
struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
cd8: e9d1 6500 ldrd r6, r5, [r1]
ASSERT(dev && hw);
cdc: f640 22a3 movw r2, #2723 ; 0xaa3
ce0: bf18 it ne
ce2: 2001 movne r0, #1
{
ce4: 4689 mov r9, r1
ASSERT(dev && hw);
ce6: 4926 ldr r1, [pc, #152] ; (d80 <_spi_m_sync_trans+0xb8>)
ce8: 4798 blx r3
return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg;
cea: 69e2 ldr r2, [r4, #28]
/* If settings are not applied (pending), we can not go on */
if (hri_sercomspi_is_syncing(
cec: f012 0207 ands.w r2, r2, #7
cf0: d13e bne.n d70 <_spi_m_sync_trans+0xa8>
hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE);
cf2: 4b24 ldr r3, [pc, #144] ; (d84 <_spi_m_sync_trans+0xbc>)
cf4: 2103 movs r1, #3
cf6: 4620 mov r0, r4
cf8: 4798 blx r3
tmp = ((Sercom *)hw)->SPI.CTRLA.reg;
cfa: 6823 ldr r3, [r4, #0]
hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) {
return ERR_BUSY;
}
/* SPI must be enabled to start synchronous transfer */
if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) {
cfc: 0799 lsls r1, r3, #30
cfe: d53a bpl.n d76 <_spi_m_sync_trans+0xae>
struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size};
d00: 4611 mov r1, r2
return ((Sercom *)hw)->SPI.INTFLAG.reg;
d02: 7e23 ldrb r3, [r4, #24]
d04: b2d8 uxtb r0, r3
if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) {
d06: 075b lsls r3, r3, #29
d08: d40f bmi.n d2a <_spi_m_sync_trans+0x62>
uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw);
if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) {
/* In master mode, do not start next byte before previous byte received
* to make better output waveform */
if (ctrl.rxcnt >= ctrl.txcnt) {
d0a: 428a cmp r2, r1
d0c: d818 bhi.n d40 <_spi_m_sync_trans+0x78>
if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) {
d0e: 07c3 lsls r3, r0, #31
d10: d516 bpl.n d40 <_spi_m_sync_trans+0x78>
_spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte);
d12: 88fb ldrh r3, [r7, #6]
if (ctrl->txbuf) {
d14: b136 cbz r6, d24 <_spi_m_sync_trans+0x5c>
if (ctrl->char_size > 1) {
d16: f1b8 0f01 cmp.w r8, #1
data = *ctrl->txbuf++;
d1a: 7833 ldrb r3, [r6, #0]
data |= (*ctrl->txbuf) << 8;
d1c: bf8c ite hi
d1e: f836 3b02 ldrhhi.w r3, [r6], #2
data = *ctrl->txbuf++;
d22: 3601 addls r6, #1
ctrl->txcnt++;
d24: 3201 adds r2, #1
((Sercom *)hw)->SPI.DATA.reg = data;
d26: 62a3 str r3, [r4, #40] ; 0x28
}
d28: e00a b.n d40 <_spi_m_sync_trans+0x78>
return ((Sercom *)hw)->SPI.DATA.reg;
d2a: 6aa3 ldr r3, [r4, #40] ; 0x28
if (ctrl->rxbuf) {
d2c: b13d cbz r5, d3e <_spi_m_sync_trans+0x76>
if (ctrl->char_size > 1) {
d2e: f1b8 0f01 cmp.w r8, #1
*ctrl->rxbuf++ = (uint8_t)data;
d32: 702b strb r3, [r5, #0]
*ctrl->rxbuf++ = (uint8_t)(data >> 8);
d34: bf85 ittet hi
d36: 0a1b lsrhi r3, r3, #8
d38: 706b strbhi r3, [r5, #1]
*ctrl->rxbuf++ = (uint8_t)data;
d3a: 3501 addls r5, #1
*ctrl->rxbuf++ = (uint8_t)(data >> 8);
d3c: 3502 addhi r5, #2
ctrl->rxcnt++;
d3e: 3101 adds r1, #1
if (SERCOM_SPI_INTFLAG_ERROR & iflag) {
d40: 0600 lsls r0, r0, #24
d42: d407 bmi.n d54 <_spi_m_sync_trans+0x8c>
rc = _spi_err_check(iflag, hw);
if (rc < 0) {
break;
}
if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) {
d44: f8d9 3008 ldr.w r3, [r9, #8]
d48: 4293 cmp r3, r2
d4a: d8da bhi.n d02 <_spi_m_sync_trans+0x3a>
d4c: 428b cmp r3, r1
d4e: d8d8 bhi.n d02 <_spi_m_sync_trans+0x3a>
rc = ctrl.txcnt;
d50: 4610 mov r0, r2
while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) {
d52: e006 b.n d62 <_spi_m_sync_trans+0x9a>
}
static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask)
{
SERCOM_CRITICAL_SECTION_ENTER();
((Sercom *)hw)->SPI.STATUS.reg = mask;
d54: f64f 73ff movw r3, #65535 ; 0xffff
d58: 8363 strh r3, [r4, #26]
((Sercom *)hw)->SPI.INTFLAG.reg = mask;
d5a: 2380 movs r3, #128 ; 0x80
d5c: 7623 strb r3, [r4, #24]
return ERR_OVERFLOW;
d5e: f06f 0012 mvn.w r0, #18
tmp = ((Sercom *)hw)->SPI.INTFLAG.reg;
d62: 7e23 ldrb r3, [r4, #24]
while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) {
d64: 079b lsls r3, r3, #30
d66: d0fc beq.n d62 <_spi_m_sync_trans+0x9a>
((Sercom *)hw)->SPI.INTFLAG.reg = mask;
d68: 2303 movs r3, #3
d6a: 7623 strb r3, [r4, #24]
}
/* Wait until SPI bus idle */
_spi_wait_bus_idle(hw);
return rc;
}
d6c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
return ERR_BUSY;
d70: f06f 0003 mvn.w r0, #3
d74: e7fa b.n d6c <_spi_m_sync_trans+0xa4>
return ERR_NOT_INITIALIZED;
d76: f06f 0013 mvn.w r0, #19
d7a: e7f7 b.n d6c <_spi_m_sync_trans+0xa4>
d7c: 00000459 .word 0x00000459
d80: 00000e7b .word 0x00000e7b
d84: 00000a45 .word 0x00000a45
00000d88 <atmel_start_init>:
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
d88: b510 push {r4, lr}
system_init();
d8a: 4b03 ldr r3, [pc, #12] ; (d98 <atmel_start_init+0x10>)
d8c: 4798 blx r3
//sd_mmc_stack_init();
diskio_init();
}
d8e: e8bd 4010 ldmia.w sp!, {r4, lr}
diskio_init();
d92: 4b02 ldr r3, [pc, #8] ; (d9c <atmel_start_init+0x14>)
d94: 4718 bx r3
d96: bf00 nop
d98: 00000a1d .word 0x00000a1d
d9c: 00000691 .word 0x00000691
00000da0 <__libc_init_array>:
da0: b570 push {r4, r5, r6, lr}
da2: 4d0d ldr r5, [pc, #52] ; (dd8 <__libc_init_array+0x38>)
da4: 4c0d ldr r4, [pc, #52] ; (ddc <__libc_init_array+0x3c>)
da6: 1b64 subs r4, r4, r5
da8: 10a4 asrs r4, r4, #2
daa: 2600 movs r6, #0
dac: 42a6 cmp r6, r4
dae: d109 bne.n dc4 <__libc_init_array+0x24>
db0: 4d0b ldr r5, [pc, #44] ; (de0 <__libc_init_array+0x40>)
db2: 4c0c ldr r4, [pc, #48] ; (de4 <__libc_init_array+0x44>)
db4: f000 f896 bl ee4 <_init>
db8: 1b64 subs r4, r4, r5
dba: 10a4 asrs r4, r4, #2
dbc: 2600 movs r6, #0
dbe: 42a6 cmp r6, r4
dc0: d105 bne.n dce <__libc_init_array+0x2e>
dc2: bd70 pop {r4, r5, r6, pc}
dc4: f855 3b04 ldr.w r3, [r5], #4
dc8: 4798 blx r3
dca: 3601 adds r6, #1
dcc: e7ee b.n dac <__libc_init_array+0xc>
dce: f855 3b04 ldr.w r3, [r5], #4
dd2: 4798 blx r3
dd4: 3601 adds r6, #1
dd6: e7f2 b.n dbe <__libc_init_array+0x1e>
dd8: 00000ef0 .word 0x00000ef0
ddc: 00000ef0 .word 0x00000ef0
de0: 00000ef0 .word 0x00000ef0
de4: 00000ef4 .word 0x00000ef4
00000de8 <memcpy>:
de8: 440a add r2, r1
dea: 4291 cmp r1, r2
dec: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
df0: d100 bne.n df4 <memcpy+0xc>
df2: 4770 bx lr
df4: b510 push {r4, lr}
df6: f811 4b01 ldrb.w r4, [r1], #1
dfa: f803 4f01 strb.w r4, [r3, #1]!
dfe: 4291 cmp r1, r2
e00: d1f9 bne.n df6 <memcpy+0xe>
e02: bd10 pop {r4, pc}
00000e04 <memset>:
e04: 4402 add r2, r0
e06: 4603 mov r3, r0
e08: 4293 cmp r3, r2
e0a: d100 bne.n e0e <memset+0xa>
e0c: 4770 bx lr
e0e: f803 1b01 strb.w r1, [r3], #1
e12: e7f9 b.n e08 <memset+0x4>
e14: 682f2e2e .word 0x682f2e2e
e18: 732f6c61 .word 0x732f6c61
e1c: 682f6372 .word 0x682f6372
e20: 635f6c61 .word 0x635f6c61
e24: 6e656c61 .word 0x6e656c61
e28: 2e726164 .word 0x2e726164
e2c: 0063 .short 0x0063
e2e: 2e2e .short 0x2e2e
e30: 6c61682f .word 0x6c61682f
e34: 6372732f .word 0x6372732f
e38: 6c61682f .word 0x6c61682f
e3c: 6970735f .word 0x6970735f
e40: 735f6d5f .word 0x735f6d5f
e44: 2e636e79 .word 0x2e636e79
e48: 0063 .short 0x0063
e4a: 2e2e .short 0x2e2e
e4c: 6c61682f .word 0x6c61682f
e50: 6372732f .word 0x6372732f
e54: 6c61682f .word 0x6c61682f
e58: 6173755f .word 0x6173755f
e5c: 735f7472 .word 0x735f7472
e60: 2e636e79 .word 0x2e636e79
e64: 0063 .short 0x0063
e66: 2e2e .short 0x2e2e
e68: 6c70682f .word 0x6c70682f
e6c: 6374722f .word 0x6374722f
e70: 6c70682f .word 0x6c70682f
e74: 6374725f .word 0x6374725f
e78: 632e .short 0x632e
e7a: 00 .byte 0x00
e7b: 2e .byte 0x2e
e7c: 70682f2e .word 0x70682f2e
e80: 65732f6c .word 0x65732f6c
e84: 6d6f6372 .word 0x6d6f6372
e88: 6c70682f .word 0x6c70682f
e8c: 7265735f .word 0x7265735f
e90: 2e6d6f63 .word 0x2e6d6f63
e94: 00000063 .word 0x00000063
e98: 40003000 .word 0x40003000
e9c: 40003400 .word 0x40003400
ea0: 41012000 .word 0x41012000
ea4: 41014000 .word 0x41014000
ea8: 43000000 .word 0x43000000
eac: 43000400 .word 0x43000400
eb0: 43000800 .word 0x43000800
eb4: 43000c00 .word 0x43000c00
00000eb8 <_i2cms>:
...
00000ed0 <sercomspi_regs>:
ed0: 0020000c 00020000 00000000 01ff00fe .. .............
ee0: 00000006 ....
00000ee4 <_init>:
ee4: b5f8 push {r3, r4, r5, r6, r7, lr}
ee6: bf00 nop
ee8: bcf8 pop {r3, r4, r5, r6, r7}
eea: bc08 pop {r3}
eec: 469e mov lr, r3
eee: 4770 bx lr
00000ef0 <__frame_dummy_init_array_entry>:
ef0: 0289 0000 ....
00000ef4 <_fini>:
ef4: b5f8 push {r3, r4, r5, r6, r7, lr}
ef6: bf00 nop
ef8: bcf8 pop {r3, r4, r5, r6, r7}
efa: bc08 pop {r3}
efc: 469e mov lr, r3
efe: 4770 bx lr
00000f00 <__do_global_dtors_aux_fini_array_entry>:
f00: 0265 0000 e...
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