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25 lines
611 B
C
25 lines
611 B
C
/* Auto-generated config file hpl_sdhc_config.h */
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#ifndef HPL_SDHC_CONFIG_H
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#define HPL_SDHC_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#include "peripheral_clk_config.h"
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#ifndef CONF_BASE_FREQUENCY
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#define CONF_BASE_FREQUENCY CONF_SDHC0_FREQUENCY
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#endif
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// <o> Clock Generator Select
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// <0=> Divided Clock mode
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// <1=> Programmable Clock mode
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// <i> This defines the clock generator mode in the SDCLK Frequency Select field
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// <id> sdhc_clk_gsel
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#ifndef CONF_SDHC0_CLK_GEN_SEL
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#define CONF_SDHC0_CLK_GEN_SEL 0
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#endif
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// <<< end of configuration section >>>
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#endif // HPL_SDHC_CONFIG_H
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