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84 lines
2.6 KiB
C
84 lines
2.6 KiB
C
/**
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* \file
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*
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* \brief Generic RAMECC related functionality.
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <utils.h>
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#include <utils_assert.h>
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#include <hpl_ramecc.h>
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/* RAMECC device descriptor */
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struct _ramecc_device device;
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/**
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* \brief Initialize RAMECC
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*/
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int32_t _ramecc_init(void)
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{
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if (hri_ramecc_get_STATUS_ECCDIS_bit(RAMECC)) {
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return ERR_ABORTED;
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}
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NVIC_DisableIRQ(RAMECC_IRQn);
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NVIC_ClearPendingIRQ(RAMECC_IRQn);
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NVIC_EnableIRQ(RAMECC_IRQn);
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return ERR_NONE;
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}
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void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb)
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{
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if (RAMECC_DUAL_ERROR_CB == type) {
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device.ramecc_cb.dual_bit_err = cb;
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hri_ramecc_write_INTEN_DUALE_bit(RAMECC, NULL != cb);
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} else if (RAMECC_SINGLE_ERROR_CB == type) {
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device.ramecc_cb.single_bit_err = cb;
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hri_ramecc_write_INTEN_SINGLEE_bit(RAMECC, NULL != cb);
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}
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}
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/**
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* \internal RAMECC interrupt handler
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*/
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void RAMECC_Handler(void)
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{
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struct _ramecc_device *dev = (struct _ramecc_device *)&device;
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volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC);
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if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) {
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dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
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} else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) {
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dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC));
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} else {
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return;
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}
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}
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