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641 lines
15 KiB
C
641 lines
15 KiB
C
/**
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* \file
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*
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* \brief SAM SDHC HPL
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include <utils_assert.h>
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#include "hpl_mci_sync.h"
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#include <hpl_sdhc_config.h>
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#define HSMCI_SLOT_0_SIZE 4
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static void _mci_reset(const void *const hw);
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static void _mci_set_speed(const void *const hw, uint32_t speed, uint8_t prog_clock_mode);
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static bool _mci_wait_busy(const void *const hw);
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static bool _mci_send_cmd_execute(const void *const hw, uint32_t cmdr, uint32_t cmd, uint32_t arg);
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/**
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* \brief Reset the SDHC interface
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*
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* \param hw The pointer to MCI hardware instance
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*/
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static void _mci_reset(const void *const hw)
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{
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ASSERT(hw);
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hri_sdhc_set_SRR_SWRSTCMD_bit(hw);
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}
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/**
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* \brief Set speed of the SDHC clock.
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*
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* \param hw The pointer to MCI hardware instance
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* \param speed SDHC clock speed in Hz.
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* \param prog_clock_mode Use programmable clock mode
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*/
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static void _mci_set_speed(const void *const hw, uint32_t speed, uint8_t prog_clock_mode)
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{
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uint32_t div;
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uint32_t clkbase;
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uint32_t clkmul;
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if (hri_sdhc_get_CCR_SDCLKEN_bit(hw)) {
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while (hri_sdhc_read_PSR_reg(hw) & (SDHC_PSR_CMDINHC_CANNOT | SDHC_PSR_CMDINHD_CANNOT))
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;
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hri_sdhc_clear_CCR_SDCLKEN_bit(hw);
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}
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// clkbase = hri_sdhc_read_CA0R_BASECLKF_bf(hw);
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clkbase = CONF_BASE_FREQUENCY;
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clkmul = hri_sdhc_read_CA1R_CLKMULT_bf(hw);
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/* If programmable clock mode is enabled, baseclk is divided by 2 */
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if (clkmul > 0) {
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clkbase = clkbase / 2;
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}
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if (prog_clock_mode == 0) {
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/* divided clock mode */
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hri_sdhc_clear_CCR_CLKGSEL_bit(hw);
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/* speed = Base Clock / 2*div */
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div = (clkbase / speed) / 2;
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} else {
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/* programmable clock mode */
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hri_sdhc_set_CCR_CLKGSEL_bit(hw);
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/* Specific constraint for SDHC/SDMMC IP
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speed = Base Clock * Multi Clock / (div+1) */
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div = (clkbase * (clkmul + 1)) / speed;
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if (div > 0) {
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div = div - 1;
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}
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}
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/* Specific constraint for SDHC/SDMMC IP
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The clock divider (DIV) in SDMMC_CCR must be set to a value different from 0 when HSEN is 1. */
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if ((hri_sdhc_get_HC1R_HSEN_bit(hw)) && (div == 0)) {
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div = 1;
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}
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/* Set clock divider */
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hri_sdhc_write_CCR_SDCLKFSEL_bf(hw, div & 0xFF);
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hri_sdhc_write_CCR_USDCLKFSEL_bf(hw, div >> 8);
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hri_sdhc_set_CCR_INTCLKEN_bit(hw);
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/* Repeat this step until Clock Stable is 1 */
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while (hri_sdhc_get_CCR_INTCLKS_bit(hw) == 0)
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;
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/* Output the clock to the card -- Set SD Clock Enable */
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hri_sdhc_set_CCR_SDCLKEN_bit(hw);
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}
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/**
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* \brief Wait the end of busy signal on data line
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*
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* \param hw The pointer to MCI hardware instance
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* \return true if success, otherwise false
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*/
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static bool _mci_wait_busy(const void *const hw)
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{
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uint32_t busy_wait = 0xFFFFFFFF;
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uint32_t psr;
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ASSERT(hw);
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do {
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psr = hri_sdhc_read_PSR_reg(hw);
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if (busy_wait-- == 0) {
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_mci_reset(hw);
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return false;
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}
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} while (!(psr & SDHC_PSR_DATLL(1)));
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return true;
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}
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/**
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* \brief Send a command
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*
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* \param hw The pointer to MCI hardware instance
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* \param cmdr CMDR resgister bit to use for this command
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* \param cmd Command definition
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* \param arg Argument of the command
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*
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* \return true if success, otherwise false
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*/
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static bool _mci_send_cmd_execute(const void *const hw, uint32_t cmdr, uint32_t cmd, uint32_t arg)
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{
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uint32_t sr;
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ASSERT(hw);
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cmdr |= SDHC_CR_CMDIDX(cmd) | SDHC_CR_CMDTYP_NORMAL;
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if (cmd & MCI_RESP_PRESENT) {
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if (cmd & MCI_RESP_136) {
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cmdr |= SDHC_CR_RESPTYP_136_BIT;
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} else if (cmd & MCI_RESP_BUSY) {
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cmdr |= SDHC_CR_RESPTYP_48_BIT_BUSY;
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} else {
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cmdr |= SDHC_CR_RESPTYP_48_BIT;
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}
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}
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if (cmd & MCI_CMD_OPENDRAIN) {
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hri_sdhc_set_MC1R_OPD_bit(hw);
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} else {
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hri_sdhc_clear_MC1R_OPD_bit(hw);
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}
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hri_sdhc_write_ARG1R_reg(hw, arg);
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hri_sdhc_write_CR_reg(hw, cmdr);
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/* Wait end of command */
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do {
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sr = hri_sdhc_read_EISTR_reg(hw);
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if (cmd & MCI_RESP_CRC) {
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if (sr
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& (SDHC_EISTR_CMDTEO | SDHC_EISTR_CMDEND | SDHC_EISTR_CMDIDX | SDHC_EISTR_DATTEO | SDHC_EISTR_DATEND
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| SDHC_EISTR_ADMA)) {
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_mci_reset(hw);
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hri_sdhc_set_EISTR_reg(hw, SDHC_EISTR_MASK);
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return false;
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}
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} else {
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if (sr
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& (SDHC_EISTR_CMDTEO | SDHC_EISTR_CMDEND | SDHC_EISTR_CMDIDX | SDHC_EISTR_CMDCRC | SDHC_EISTR_DATCRC
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| SDHC_EISTR_DATTEO | SDHC_EISTR_DATEND | SDHC_EISTR_ADMA)) {
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_mci_reset(hw);
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hri_sdhc_set_EISTR_reg(hw, SDHC_EISTR_MASK);
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return false;
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}
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}
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} while (!hri_sdhc_get_NISTR_CMDC_bit(hw));
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if (!(cmdr & SDHC_CR_DPSEL_DATA)) {
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hri_sdhc_set_NISTR_CMDC_bit(hw);
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}
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if (cmd & MCI_RESP_BUSY) {
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if (!_mci_wait_busy(hw)) {
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return false;
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}
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}
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return true;
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}
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/**
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* \brief Initialize MCI low level driver.
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*/
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int32_t _mci_sync_init(struct _mci_sync_device *const mci_dev, void *const hw)
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{
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ASSERT(mci_dev && hw);
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mci_dev->hw = hw;
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hri_sdhc_set_SRR_SWRSTALL_bit(hw);
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while (hri_sdhc_get_SRR_SWRSTALL_bit(hw))
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;
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/* Set the Data Timeout Register to 2 Mega Cycles */
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hri_sdhc_write_TCR_reg(hw, SDHC_TCR_DTCVAL(0xE));
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/* Set 3v3 power supply */
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hri_sdhc_write_PCR_reg(hw, SDHC_PCR_SDBPWR_ON | SDHC_PCR_SDBVSEL_3V3);
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hri_sdhc_set_NISTER_reg(hw, SDHC_NISTER_MASK);
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hri_sdhc_set_EISTER_reg(hw, SDHC_EISTER_MASK);
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return ERR_NONE;
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}
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/**
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* \brief Deinitialize MCI low level driver.
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*/
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int32_t _mci_sync_deinit(struct _mci_sync_device *const mci_dev)
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{
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ASSERT(mci_dev);
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mci_dev->hw = NULL;
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return ERR_NONE;
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}
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/**
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* \brief Select a device and initialize it
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*/
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int32_t _mci_sync_select_device(struct _mci_sync_device *const mci_dev, uint8_t slot, uint32_t clock, uint8_t bus_width,
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bool high_speed)
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{
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(void)(slot);
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void *hw;
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ASSERT(mci_dev && mci_dev->hw);
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hw = mci_dev->hw;
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if (high_speed) {
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hri_sdhc_set_HC1R_HSEN_bit(hw);
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} else {
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hri_sdhc_clear_HC1R_HSEN_bit(hw);
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}
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if (hri_sdhc_get_HC2R_PVALEN_bit(hw) == 0) {
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_mci_set_speed(hw, clock, CONF_SDHC0_CLK_GEN_SEL);
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}
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switch (bus_width) {
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case 1:
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hri_sdhc_clear_HC1R_DW_bit(hw);
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break;
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case 4:
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hri_sdhc_set_HC1R_DW_bit(hw);
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break;
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default:
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return ERR_INVALID_ARG;
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}
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return ERR_NONE;
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}
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/**
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* \brief Deselect a device by an assigned slot
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*/
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int32_t _mci_sync_deselect_device(struct _mci_sync_device *const mci_dev, uint8_t slot)
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{
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/* Nothing to do */
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(void)(mci_dev);
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(void)(slot);
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return ERR_NONE;
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}
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/**
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* \brief Get the maximum bus width of a device
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* by a selected slot
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*/
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uint8_t _mci_sync_get_bus_width(struct _mci_sync_device *const mci_dev, uint8_t slot)
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{
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(void)(mci_dev);
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switch (slot) {
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case 0:
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return HSMCI_SLOT_0_SIZE;
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default:
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/* Slot number wrong */
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return 0;
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}
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}
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/**
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* \brief Get the high speed capability of the device.
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*/
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bool _mci_sync_is_high_speed_capable(struct _mci_sync_device *const mci_dev)
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{
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return hri_sdhc_get_CA0R_HSSUP_bit(mci_dev->hw);
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}
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/**
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* \brief Send 74 clock cycles on the line.
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* Note: It is required after card plug and before card install.
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*/
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void _mci_sync_send_clock(struct _mci_sync_device *const mci_dev)
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{
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ASSERT(mci_dev);
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volatile uint32_t i;
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for (i = 0; i < 5000; i++)
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;
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}
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/**
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* \brief Send a command on the selected slot
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*/
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bool _mci_sync_send_cmd(struct _mci_sync_device *const mci_dev, uint32_t cmd, uint32_t arg)
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{
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void *hw;
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ASSERT(mci_dev && mci_dev->hw);
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hw = mci_dev->hw;
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/* Check Command Inhibit (CMD) in the Present State register */
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if (hri_sdhc_get_PSR_CMDINHC_bit(hw)) {
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return false;
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}
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hri_sdhc_clear_TMR_DMAEN_bit(hw);
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hri_sdhc_write_BCR_reg(hw, 0);
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return _mci_send_cmd_execute(hw, 0, cmd, arg);
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}
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/**
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* \brief Get 32 bits response of the last command.
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*/
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uint32_t _mci_sync_get_response(struct _mci_sync_device *const mci_dev)
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{
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void *hw;
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ASSERT(mci_dev && mci_dev->hw);
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hw = mci_dev->hw;
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return hri_sdhc_read_RR_reg(hw, 0);
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}
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/**
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* \brief Get 128 bits response of the last command.
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*/
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void _mci_sync_get_response_128(struct _mci_sync_device *const mci_dev, uint8_t *response)
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{
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uint32_t response_32;
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void * hw;
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ASSERT(mci_dev && mci_dev->hw);
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hw = mci_dev->hw;
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for (int8_t i = 3; i >= 0; i--) {
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response_32 = hri_sdhc_read_RR_reg(hw, i);
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if (i != 3) {
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*response = (response_32 >> 24) & 0xFF;
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response++;
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}
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*response = (response_32 >> 16) & 0xFF;
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response++;
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*response = (response_32 >> 8) & 0xFF;
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response++;
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*response = (response_32 >> 0) & 0xFF;
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response++;
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}
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}
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/**
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* \brief Send an ADTC command on the selected slot
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* An ADTC (Addressed Data Transfer Commands)
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* command is used for read/write access.
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*/
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bool _mci_sync_adtc_start(struct _mci_sync_device *const mci_dev, uint32_t cmd, uint32_t arg, uint16_t block_size,
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uint16_t nb_block, bool access_block)
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{
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uint32_t tmr;
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void * hw;
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ASSERT(mci_dev && mci_dev->hw);
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hw = mci_dev->hw;
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/* No use without dma support */
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(void)access_block;
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/* Check Command Inhibit (CMD/DAT) in the Present State register */
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if (hri_sdhc_get_PSR_CMDINHC_bit(hw) || hri_sdhc_get_PSR_CMDINHD_bit(hw)) {
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return false;
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}
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if (cmd & MCI_CMD_WRITE) {
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tmr = SDHC_TMR_DTDSEL_WRITE;
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} else {
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tmr = SDHC_TMR_DTDSEL_READ;
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}
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if (cmd & MCI_CMD_SDIO_BYTE) {
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tmr |= SDHC_TMR_MSBSEL_SINGLE;
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} else if (cmd & MCI_CMD_SDIO_BLOCK) {
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tmr |= SDHC_TMR_BCEN | SDHC_TMR_MSBSEL_MULTIPLE;
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} else if (cmd & MCI_CMD_SINGLE_BLOCK) {
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tmr |= SDHC_TMR_MSBSEL_SINGLE;
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} else if (cmd & MCI_CMD_MULTI_BLOCK) {
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tmr |= SDHC_TMR_BCEN | SDHC_TMR_MSBSEL_MULTIPLE;
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} else {
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return false;
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}
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hri_sdhc_write_TMR_reg(hw, tmr);
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hri_sdhc_write_BSR_reg(hw, SDHC_BSR_BLOCKSIZE(block_size) | SDHC_BSR_BOUNDARY_4K);
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hri_sdhc_write_BCR_reg(hw, SDHC_BCR_BCNT(nb_block));
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mci_dev->mci_sync_trans_pos = 0;
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mci_dev->mci_sync_block_size = block_size;
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mci_dev->mci_sync_nb_block = nb_block;
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return _mci_send_cmd_execute(hw, SDHC_CR_DPSEL_DATA, cmd, arg);
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}
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/**
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* \brief Send a command to stop an ADTC command on the selected slot.
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*/
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bool _mci_sync_adtc_stop(struct _mci_sync_device *const mci_dev, uint32_t cmd, uint32_t arg)
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{
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ASSERT(mci_dev && mci_dev->hw);
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/* Nothing to do */
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(void)(cmd);
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(void)(arg);
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return true;
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}
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/**
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* \brief Read a word on the line.
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*/
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bool _mci_sync_read_word(struct _mci_sync_device *const mci_dev, uint32_t *value)
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{
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uint32_t sr;
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uint8_t nbytes;
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void * hw;
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ASSERT(mci_dev && mci_dev->hw);
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hw = mci_dev->hw;
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/* Wait data available */
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nbytes = (mci_dev->mci_sync_block_size * mci_dev->mci_sync_nb_block - mci_dev->mci_sync_trans_pos < 4)
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? (mci_dev->mci_sync_block_size % 4)
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: 4;
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if (mci_dev->mci_sync_trans_pos % mci_dev->mci_sync_block_size == 0) {
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do {
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sr = hri_sdhc_read_EISTR_reg(hw);
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if (sr & (SDHC_EISTR_DATTEO | SDHC_EISTR_DATCRC | SDHC_EISTR_DATEND)) {
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_mci_reset(hw);
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return false;
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}
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} while (!hri_sdhc_get_NISTR_BRDRDY_bit(hw));
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hri_sdhc_set_NISTR_BRDRDY_bit(hw);
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}
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/* Read data */
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if (nbytes == 4) {
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*value = hri_sdhc_read_BDPR_reg(hw);
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} else {
|
|
sr = hri_sdhc_read_BDPR_reg(hw);
|
|
switch (nbytes) {
|
|
case 3:
|
|
value[0] = sr & 0xFFFFFF;
|
|
case 2:
|
|
value[0] = sr & 0xFFFF;
|
|
case 1:
|
|
value[0] = sr & 0xFF;
|
|
break;
|
|
}
|
|
}
|
|
mci_dev->mci_sync_trans_pos += nbytes;
|
|
|
|
if (((uint64_t)mci_dev->mci_sync_block_size * mci_dev->mci_sync_nb_block) > mci_dev->mci_sync_trans_pos) {
|
|
return true;
|
|
}
|
|
|
|
/* Wait end of transfer */
|
|
do {
|
|
sr = hri_sdhc_read_EISTR_reg(hw);
|
|
|
|
if (sr & (SDHC_EISTR_DATTEO | SDHC_EISTR_DATCRC | SDHC_EISTR_DATEND)) {
|
|
_mci_reset(hw);
|
|
return false;
|
|
}
|
|
} while (!hri_sdhc_get_NISTR_TRFC_bit(hw));
|
|
hri_sdhc_set_NISTR_TRFC_bit(hw);
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* \brief Write a word on the line
|
|
*/
|
|
bool _mci_sync_write_word(struct _mci_sync_device *const mci_dev, uint32_t value)
|
|
{
|
|
uint32_t sr;
|
|
uint8_t nbytes;
|
|
void * hw;
|
|
|
|
ASSERT(mci_dev && mci_dev->hw);
|
|
hw = mci_dev->hw;
|
|
|
|
/* Wait data available */
|
|
nbytes = 4; //( mci_dev->mci_sync_block_size & 0x3 ) ? 1 : 4;
|
|
if (mci_dev->mci_sync_trans_pos % mci_dev->mci_sync_block_size == 0) {
|
|
do {
|
|
sr = hri_sdhc_read_EISTR_reg(hw);
|
|
|
|
if (sr & (SDHC_EISTR_DATTEO | SDHC_EISTR_DATCRC | SDHC_EISTR_DATEND)) {
|
|
_mci_reset(hw);
|
|
return false;
|
|
}
|
|
} while (!hri_sdhc_get_NISTR_BWRRDY_bit(hw));
|
|
hri_sdhc_set_NISTR_BWRRDY_bit(hw);
|
|
}
|
|
/* Write data */
|
|
hri_sdhc_write_BDPR_reg(hw, value);
|
|
mci_dev->mci_sync_trans_pos += nbytes;
|
|
|
|
if (((uint64_t)mci_dev->mci_sync_block_size * mci_dev->mci_sync_nb_block) > mci_dev->mci_sync_trans_pos) {
|
|
return true;
|
|
}
|
|
|
|
/* Wait end of transfer */
|
|
do {
|
|
sr = hri_sdhc_read_EISTR_reg(hw);
|
|
|
|
if (sr & (SDHC_EISTR_DATTEO | SDHC_EISTR_DATCRC | SDHC_EISTR_DATEND)) {
|
|
_mci_reset(hw);
|
|
return false;
|
|
}
|
|
} while (!hri_sdhc_get_NISTR_TRFC_bit(hw));
|
|
hri_sdhc_set_NISTR_TRFC_bit(hw);
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* \brief Start a read blocks transfer on the line
|
|
* Note: The driver will use the DMA available to speed up the transfer.
|
|
*/
|
|
bool _mci_sync_start_read_blocks(struct _mci_sync_device *const mci_dev, void *dst, uint16_t nb_block)
|
|
{
|
|
uint32_t nb_data;
|
|
uint8_t *ptr = (uint8_t *)dst;
|
|
uint8_t nbytes = 4;
|
|
|
|
ASSERT(mci_dev && mci_dev->hw);
|
|
ASSERT(nb_block);
|
|
ASSERT(dst);
|
|
|
|
nb_data = nb_block * mci_dev->mci_sync_block_size;
|
|
|
|
while (nb_data) {
|
|
_mci_sync_read_word(mci_dev, (uint32_t *)ptr);
|
|
if (nb_data < nbytes) {
|
|
nbytes = mci_dev->mci_sync_block_size % nbytes;
|
|
}
|
|
nb_data -= nbytes;
|
|
ptr += nbytes;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* \brief Start a write blocks transfer on the line
|
|
* Note: The driver will use the DMA available to speed up the transfer.
|
|
*/
|
|
bool _mci_sync_start_write_blocks(struct _mci_sync_device *const mci_dev, const void *src, uint16_t nb_block)
|
|
{
|
|
uint32_t nb_data;
|
|
uint8_t *ptr = (uint8_t *)src;
|
|
uint8_t nbytes = 4;
|
|
|
|
ASSERT(mci_dev && mci_dev->hw);
|
|
ASSERT(nb_block);
|
|
ASSERT(src);
|
|
|
|
nb_data = nb_block * mci_dev->mci_sync_block_size;
|
|
|
|
while (nb_data) {
|
|
_mci_sync_write_word(mci_dev, *(uint32_t *)ptr);
|
|
if (nb_data < nbytes) {
|
|
nbytes = mci_dev->mci_sync_block_size % nbytes;
|
|
}
|
|
nb_data -= nbytes;
|
|
ptr += nbytes;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* \brief Wait the end of transfer initiated by mci_start_read_blocks()
|
|
*/
|
|
bool _mci_sync_wait_end_of_read_blocks(struct _mci_sync_device *const mci_dev)
|
|
{
|
|
ASSERT(mci_dev && mci_dev->hw);
|
|
|
|
/* Always return true for sync read blocks */
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* \brief Wait the end of transfer initiated by mci_start_write_blocks()
|
|
*/
|
|
bool _mci_sync_wait_end_of_write_blocks(struct _mci_sync_device *const mci_dev)
|
|
{
|
|
ASSERT(mci_dev && mci_dev->hw);
|
|
|
|
/* Always return true for sync write blocks */
|
|
return true;
|
|
}
|