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128 lines
3.0 KiB
C
128 lines
3.0 KiB
C
#include "sd_mmc_spi.h"
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#include "assert.h"
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static sd_mmc_spi_errno_t sd_mmc_spi_err;
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static uint8_t spi_m_sync_crc7(uint8_t * buf, uint8_t size)
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{
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uint8_t crc, value, i;
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crc = 0;
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while (size--) {
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value = *buf++;
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for (i = 0; i < 8; i++) {
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crc <<= 1;
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if ((value & 0x80) ^ (crc & 0x80)) {
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crc ^= 0x09;
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}
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value <<= 1;
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}
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}
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crc = (crc << 1) | 1;
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return crc;
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}
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bool spi_m_sync_send_cmd(struct spi_m_sync_descriptor* spi, uint32_t cmd,
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uint32_t arg)
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{
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return spi_m_sync_adtc_start(spi, cmd, arg, 0, 0, false);
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}
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bool spi_m_sync_adtc_start(struct spi_m_sync_descriptor* spi,
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uint32_t cmd, uint32_t arg, uint16_t block_size,
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uint16_t nb_block, bool access_block)
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{
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uint8_t dummy = 0xFF;
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uint8_t cmd_token[6];
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uint8_t ncr_timeout;
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uint8_t r1;
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uint16_t dummy2 = 0xFF;
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(void)access_block;
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assert(cmd & SDMMC_RESP_PRESENT);
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sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
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cmd_token[0] = SPI_CMD_ENCODE(SDMMC_CMD_GET_INDEX(cmd));
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cmd_token[1] = arg >> 24;
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cmd_token[2] = arg >> 16;
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cmd_token[3] = arg >> 8;
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cmd_token[4] = arg;
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cmd_token[5] = spi_m_sync_crc7(cmd_token, 5);
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// 8 cycles to respect Ncs timing
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spi_m_sync_io_write(spi, &dummy, 1);
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// send command
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spi_m_sync_io_write(spi, cmd_token, sizeof(cmd_token));
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// Wait for response
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// Two retries will be done to manage the Ncr timing between command and response
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// Ncr: Min. 1x8 clock cycle, Max 8x8 clock cycles
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// WORKAROUND for no compliance (Atmel Internal ref. SD13)
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r1 = 0xFF;
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// Ignore first byte because Ncr min. = 8 clock cycles
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spi_m_sync_io_write(spi, &dummy, 1);
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spi_m_sync_io_read(spi, &r1, 1);
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ncr_timeout = 7;
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while(1)
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{
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spi_m_sync_io_write(spi, &dummy, 1);
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spi_m_sync_io_read(spi, &r1, 1);
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if((r1 & R1_SPI_ERROR) == 0)
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{
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// Valid response
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break;
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}
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if(--ncr_timeout == 0)
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{
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}
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}
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return true;
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}
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bool spi_m_sync_start_read_blocks(struct spi_m_sync_descriptor* spi,
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void *dst, uint16_t nb_block)
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{
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return true;
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}
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bool spi_m_sync_start_write_blocks(struct spi_m_sync_descriptor* spi,
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const void *src, uint16_t nb_block)
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{
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return true;
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}
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bool spi_m_sync_wait_end_of_write_blocks(struct spi_m_sync_descriptor* spi)
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{
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return true;
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}
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bool spi_m_sync_wait_end_of_read_blocks(struct spi_m_sync_descriptor* spi)
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{
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return true;
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}
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bool spi_m_sync_write_word(struct spi_m_sync_descriptor* spi,
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uint32_t value)
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{
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return true;
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}
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bool spi_m_sync_read_word(struct spi_m_sync_descriptor* spi, uint32_t* value)
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{
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return true;
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}
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uint32_t spi_m_sync_get_response(struct spi_m_sync_descriptor* spi)
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{
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return 0;
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}
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void spi_m_sync_send_clock(struct spi_m_sync_descriptor* spi) {}
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int32_t spi_m_sync_select_device(struct spi_m_sync_descriptor* spi, uint8_t slot, uint32_t clock, uint8_t bus_width, bool high_speed)
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{
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return 0;
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}
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int32_t spi_m_sync_deselect_device(struct spi_m_sync_descriptor* spi, uint8_t slot)
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{
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return 0;
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}
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