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496 lines
13 KiB
C
496 lines
13 KiB
C
#include "sd_mmc_spi.h"
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#include "atmel_start_pins.h"
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#include "hal_spi_m_sync.h"
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#include "sd_mmc_protocol.h"
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#include "usb_includes.h"
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static inline void sd_mmc_device_enable()
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{
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PORT->Group[1].OUT.reg &= ~(1 << SPI_CS_PIN);
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}
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static inline void sd_mmc_device_disable()
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{
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PORT->Group[1].OUT.reg |= (1 << SPI_CS_PIN);
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}
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static sd_mmc_spi_errno_t sd_mmc_spi_err;
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// 32 bits response of the last command
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static uint32_t sd_mmc_spi_response_32;
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// Current position (byte) of the transfer started by spi_m_sync_adtc_start()
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static uint32_t sd_mmc_spi_transfert_pos;
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// Size block requested by last spi_m_sync_adtc_start()
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static uint16_t sd_mmc_spi_block_size;
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// Total number of block requested by last spi_m_sync_adtc_start()
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static uint16_t sd_mmc_spi_nb_block;
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static uint8_t spi_m_sync_crc7(uint8_t * buf, uint8_t size)
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{
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uint8_t crc, value, i;
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crc = 0;
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while (size--) {
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value = *buf++;
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for (i = 0; i < 8; i++) {
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crc <<= 1;
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if ((value & 0x80) ^ (crc & 0x80)) {
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crc ^= 0x09;
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}
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value <<= 1;
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}
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}
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crc = (crc << 1) | 1;
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return crc;
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}
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static bool spi_m_sync_wait_busy(struct spi_m_sync_descriptor* spi)
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{
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uint8_t line = 0xFF;
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uint8_t dummy = 0xFF;
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/* Delay before check busy
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* Nbr timing minimum = 8 cylces
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*/
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spi_m_sync_io_write(spi, &dummy, 1);
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spi_m_sync_io_read(spi, &line, 1);
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/* Wait end of busy signal
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* Nec timing: 0 to unlimited
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* However a timeout is used.
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* 200 000 * 8 cycles
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*/
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uint32_t nec_timeout = 200000;
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spi_m_sync_io_write(spi, &dummy, 1);
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spi_m_sync_io_read(spi, &line, 1);
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do {
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spi_m_sync_io_write(spi, &dummy, 1);
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spi_m_sync_io_read(spi, &line, 1);
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if (!(nec_timeout--)) {
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return false;
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}
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} while (line != 0xFF);
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return true;
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}
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static void spi_m_sync_start_write_block(struct spi_m_sync_descriptor* spi)
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{
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uint8_t dummy = 0xFF;
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assert(!(sd_mmc_spi_transfert_pos %sd_mmc_spi_block_size), ">>>");
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// Delay before start writing block:
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// Nwr timing minimum = 8 cycles
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spi_m_sync_io_write(spi, &dummy, 1);
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// Send start token
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uint8_t token;
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if (1 == sd_mmc_spi_nb_block)
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{
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token = SPI_TOKEN_SINGLE_WRITE;
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}
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else
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{
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token = SPI_TOKEN_MULTI_WRITE;
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}
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spi_m_sync_io_write(spi, &token, 1);
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}
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static bool spi_m_sync_stop_write_block(struct spi_m_sync_descriptor* spi)
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{
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uint8_t resp;
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uint16_t crc;
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uint8_t dummy = 0xFF;
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// Send CRC
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crc = 0xFFFF; /// CRC is disabled in SPI mode
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spi_m_sync_io_write(spi, (uint8_t*)&crc, 2);
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// Receiv data response token
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spi_m_sync_io_write(spi, &dummy, 1);
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spi_m_sync_io_read(spi, &resp, 1);
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if (!SPI_TOKEN_DATA_RESP_VALID(resp)) {
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sd_mmc_spi_err = SD_MMC_SPI_ERR;
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sd_mmc_spi_debug("%s: Invalid Data Response Token 0x%x\n\r", __func__, resp);
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return false;
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}
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// Check data response
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switch (SPI_TOKEN_DATA_RESP_CODE(resp)) {
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case SPI_TOKEN_DATA_RESP_ACCEPTED:
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break;
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case SPI_TOKEN_DATA_RESP_CRC_ERR:
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sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_CRC;
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sd_mmc_spi_debug("%s: Write blocks, SD_MMC_SPI_ERR_CRC, resp 0x%x\n\r",
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__func__, resp);
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return false;
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case SPI_TOKEN_DATA_RESP_WRITE_ERR:
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default:
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sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE;
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sd_mmc_spi_debug("%s: Write blocks SD_MMC_SPI_ERR_WR, resp 0x%x\n\r",
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__func__, resp);
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return false;
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}
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return true;
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}
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static bool spi_m_sync_stop_multiwrite_block(struct spi_m_sync_descriptor* spi)
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{
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uint8_t value;
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if (1 == sd_mmc_spi_nb_block) {
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return true; // Single block write
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}
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if (sd_mmc_spi_nb_block >
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(sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size)) {
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return true; // It is not the End of multi write
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}
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// Delay before start write block:
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// Nwr timing minimum = 8 cylces
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value = 0xFF;
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spi_m_sync_io_write(spi, &value, 1);
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// Send stop token
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value = SPI_TOKEN_STOP_TRAN;
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spi_m_sync_io_write(spi, &value, 1);
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// Wait busy
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if (!spi_m_sync_wait_busy(spi)) {
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sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_TIMEOUT;
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sd_mmc_spi_debug("%s: Stop write blocks timeout\n\r",
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__func__);
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return false;
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}
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return true;
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}
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static bool spi_m_sync_start_read_block(struct spi_m_sync_descriptor* spi)
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{
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uint32_t i;
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uint8_t token;
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uint8_t dummy = 0xFF;
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assert(!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size), ">>>");
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/* Wait for start data token:
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* The read timeout is the Nac timing.
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* Nac must be computed trough CSD values,
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* or it is 100ms for SDHC / SDXC
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* Compute the maximum timeout:
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* Frequency maximum = 25MHz
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* 1 byte = 8 cycles
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* 100ms = 312500 x spi_read_buffer_wait() maximum
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*/
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token = 0;
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i = 500000;
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do {
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if (i-- == 0) {
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sd_mmc_spi_err = SD_MMC_SPI_ERR_READ_TIMEOUT;
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sd_mmc_spi_debug("%s: Read blocks timeout\n\r", __func__);
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return false;
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}
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spi_m_sync_io_write(spi, &dummy, 1);
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spi_m_sync_io_read(spi, &token, 1);
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if (SPI_TOKEN_DATA_ERROR_VALID(token)) {
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assert(SPI_TOKEN_DATA_ERROR_ERRORS & token, ">>>");
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if (token & (SPI_TOKEN_DATA_ERROR_ERROR
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| SPI_TOKEN_DATA_ERROR_ECC_ERROR
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| SPI_TOKEN_DATA_ERROR_CC_ERROR)) {
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sd_mmc_spi_debug("%s: CRC data error token\n\r", __func__);
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sd_mmc_spi_err = SD_MMC_SPI_ERR_READ_CRC;
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} else {
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sd_mmc_spi_debug("%s: Out of range data error token\n\r", __func__);
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sd_mmc_spi_err = SD_MMC_SPI_ERR_OUT_OF_RANGE;
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}
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return false;
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}
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} while (token != SPI_TOKEN_SINGLE_MULTI_READ);
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return true;
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}
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static void spi_m_sync_stop_read_block(struct spi_m_sync_descriptor* spi)
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{
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uint8_t crc[2];
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uint8_t dummy = 0xFF;
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// Read 16-bit CRC (not cheked)
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spi_m_sync_io_write(spi, &dummy, 1);
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spi_m_sync_io_read(spi, crc, 2);
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}
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bool spi_m_sync_send_cmd(struct spi_m_sync_descriptor* spi, uint32_t cmd,
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uint32_t arg)
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{
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return spi_m_sync_adtc_start(spi, cmd, arg, 0, 0, false);
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}
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bool spi_m_sync_adtc_start(struct spi_m_sync_descriptor* spi,
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uint32_t cmd, uint32_t arg, uint16_t block_size,
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uint16_t nb_block, bool access_block)
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{
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uint8_t dummy = 0xFF;
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uint8_t cmd_token[6];
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uint8_t ncr_timeout;
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uint8_t r1;
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uint8_t dummy2 = 0xFF;
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(void)access_block;
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assert(cmd & SDMMC_RESP_PRESENT, "No SD Card response was present...");
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sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
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cmd_token[0] = SPI_CMD_ENCODE(SDMMC_CMD_GET_INDEX(cmd));
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cmd_token[1] = arg >> 24;
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cmd_token[2] = arg >> 16;
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cmd_token[3] = arg >> 8;
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cmd_token[4] = arg;
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cmd_token[5] = spi_m_sync_crc7(cmd_token, 5);
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// 8 cycles to respect Ncs timing
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spi_m_sync_io_write(spi, &dummy, 1);
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// send command
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spi_m_sync_io_write(spi, cmd_token, sizeof(cmd_token));
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// Wait for response
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// Two retries will be done to manage the Ncr timing between command and response
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// Ncr: Min. 1x8 clock cycle, Max 8x8 clock cycles
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// WORKAROUND for no compliance (Atmel Internal ref. SD13)
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r1 = 0xFF;
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// Ignore first byte because Ncr min. = 8 clock cycles
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spi_m_sync_io_read(spi, &r1, 1);
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ncr_timeout = 7;
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while(1)
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{
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spi_m_sync_io_read(spi, &r1, 1);
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if((r1 & R1_SPI_ERROR) == 0)
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{
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// Valid response
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break;
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}
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if(--ncr_timeout == 0)
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{
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// Here valid r1 response received
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sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lX, R1 timeout\r\n",
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__func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg);
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sd_mmc_spi_err = SD_MMC_SPI_ERR_RESP_TIMEOUT;
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return false;
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}
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}
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// Save R1 (specific to spi interface) in 32 bit response
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// The R1_SPI_IDLE bit can be checked by high level
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sd_mmc_spi_response_32 = r1;
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// Manage error in R1
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if (r1 & R1_SPI_COM_CRC)
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{
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sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%02x, R1_SPI_COM_CRC\n\r",
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__func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg, r1);
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sd_mmc_spi_err = SD_MMC_SPI_ERR_RESP_CRC;
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return false;
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}
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if (r1 & R1_SPI_ILLEGAL_COMMAND)
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{
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sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%x, R1 ILLEGAL_COMMAND\n\r",
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__func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg, r1);
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sd_mmc_spi_err = SD_MMC_SPI_ERR_ILLEGAL_COMMAND;
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return false;
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}
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if (r1 & ~R1_SPI_IDLE) {
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// Other error
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sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, r1 0x%x, R1 error\n\r",
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__func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg, r1);
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sd_mmc_spi_err = SD_MMC_SPI_ERR;
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return false;
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}
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// Manage other responses
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if (cmd & SDMMC_RESP_BUSY) {
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if (!spi_m_sync_wait_busy(spi)) {
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sd_mmc_spi_err = SD_MMC_SPI_ERR_RESP_BUSY_TIMEOUT;
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sd_mmc_spi_debug("%s: cmd %02d, arg 0x%08lx, Busy signal always high\n\r",
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__func__, (int)SDMMC_CMD_GET_INDEX(cmd), arg);
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return false;
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}
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}
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if (cmd & SDMMC_RESP_8) {
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sd_mmc_spi_response_32 = 0;
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spi_m_sync_io_write(spi, &dummy2, 1);
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spi_m_sync_io_read(spi, (uint8_t*)&sd_mmc_spi_response_32, 1);
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sd_mmc_spi_response_32 = LE32(sd_mmc_spi_response_32);
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}
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if (cmd & SDMMC_RESP_32) {
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spi_m_sync_io_write(spi, &dummy2, 1);
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spi_m_sync_io_read(spi, (uint8_t*)&sd_mmc_spi_response_32, 4);
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sd_mmc_spi_response_32 = BE32(sd_mmc_spi_response_32);
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}
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sd_mmc_spi_block_size = block_size;
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sd_mmc_spi_nb_block = nb_block;
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sd_mmc_spi_transfert_pos = 0;
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return true;
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}
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bool spi_m_sync_start_read_blocks(struct spi_m_sync_descriptor* spi,
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void *dst, uint16_t nb_block)
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{
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uint32_t pos;
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uint8_t dummy = 0xFF;
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sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
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pos = 0;
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while (nb_block--) {
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assert(sd_mmc_spi_nb_block >
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(sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size), ">>>");
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if (!spi_m_sync_start_read_block(spi)) {
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return false;
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}
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// Read block
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spi_m_sync_io_write(spi, &dummy, 1);
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spi_m_sync_io_read(spi, &((uint8_t*)dst)[pos], sd_mmc_spi_block_size);
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pos += sd_mmc_spi_block_size;
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sd_mmc_spi_transfert_pos += sd_mmc_spi_block_size;
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spi_m_sync_stop_read_block(spi);
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}
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return true;
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}
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bool spi_m_sync_start_write_blocks(struct spi_m_sync_descriptor* spi,
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const void *src, uint16_t nb_block)
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{
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uint32_t pos;
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sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
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pos = 0;
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while (nb_block--) {
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assert(sd_mmc_spi_nb_block >
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(sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size), ">>>");
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spi_m_sync_start_write_block(spi);
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// Write block
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spi_m_sync_io_write(spi, &((uint8_t*)src)[pos], sd_mmc_spi_block_size);
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pos += sd_mmc_spi_block_size;
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sd_mmc_spi_transfert_pos += sd_mmc_spi_block_size;
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if (!spi_m_sync_stop_write_block(spi)) {
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return false;
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}
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// Do not check busy of last block
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// but delay it to mci_wait_end_of_write_blocks()
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if (nb_block) {
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// Wait busy due to data programmation
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if (!spi_m_sync_wait_busy(spi)) {
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sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_TIMEOUT;
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sd_mmc_spi_debug("%s: Write blocks timeout\n\r", __func__);
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return false;
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}
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}
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}
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return true;
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}
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bool spi_m_sync_wait_end_of_write_blocks(struct spi_m_sync_descriptor* spi)
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{
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// Wait busy due to data programmation of last block writed
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if (!spi_m_sync_wait_busy(spi)) {
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sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_TIMEOUT;
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sd_mmc_spi_debug("%s: Write blocks timeout\n\r", __func__);
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return false;
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}
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return spi_m_sync_stop_multiwrite_block(spi);
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}
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bool spi_m_sync_wait_end_of_read_blocks(struct spi_m_sync_descriptor* spi)
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{
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return true;
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}
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bool spi_m_sync_write_word(struct spi_m_sync_descriptor* spi,
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uint32_t value)
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{
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sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
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assert(sd_mmc_spi_nb_block > (sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size), "<<<");
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if(!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size))
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{
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spi_m_sync_start_write_block(spi);
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}
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// Write data
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value = LE32(value);
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spi_m_sync_io_write(spi, (uint8_t*)&value, 4);
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sd_mmc_spi_transfert_pos += 4;
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if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
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// End of block
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if (!spi_m_sync_stop_write_block(spi)) {
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return false;
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}
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// Wait busy due to data programmation
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if (!spi_m_sync_wait_busy(spi)) {
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sd_mmc_spi_err = SD_MMC_SPI_ERR_WRITE_TIMEOUT;
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sd_mmc_spi_debug("%s: Write blocks timeout\n\r", __func__);
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return false;
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}
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}
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return spi_m_sync_stop_multiwrite_block(spi);
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}
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bool spi_m_sync_read_word(struct spi_m_sync_descriptor* spi, uint32_t* value)
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{
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uint8_t dummy = 0xFF;
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sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
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assert(sd_mmc_spi_nb_block >
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(sd_mmc_spi_transfert_pos / sd_mmc_spi_block_size),
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">>>");
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if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
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// New block
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if (!spi_m_sync_start_read_block(spi)) {
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return false;
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}
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}
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// Read data
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spi_m_sync_io_write(spi, &dummy, 1);
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spi_m_sync_io_read(spi, (uint8_t*)&value, 4);
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*value = LE32(*value);
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sd_mmc_spi_transfert_pos += 4;
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if (!(sd_mmc_spi_transfert_pos % sd_mmc_spi_block_size)) {
|
|
// End of block
|
|
spi_m_sync_stop_read_block(spi);
|
|
}
|
|
return true;}
|
|
|
|
uint32_t spi_m_sync_get_response(struct spi_m_sync_descriptor* spi)
|
|
{
|
|
return sd_mmc_spi_response_32;
|
|
}
|
|
|
|
|
|
void spi_m_sync_send_clock(struct spi_m_sync_descriptor* spi)
|
|
{
|
|
uint8_t i;
|
|
uint8_t dummy = 0xFF;
|
|
|
|
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
|
|
// Send 80 cycles
|
|
for(i = 0; i < 10; i++)
|
|
{
|
|
spi_m_sync_io_write(spi, &dummy, 1); // 8 cycles
|
|
}
|
|
}
|
|
|
|
int32_t spi_m_sync_select_device(struct spi_m_sync_descriptor* spi, uint8_t slot, uint32_t clock, uint8_t bus_width, bool high_speed)
|
|
{
|
|
UNUSED(bus_width);
|
|
UNUSED(high_speed);
|
|
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
|
|
PORT->Group[1].OUT.reg &= ~(1 << SPI_CS_PIN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int32_t spi_m_sync_deselect_device(struct spi_m_sync_descriptor* spi, uint8_t slot)
|
|
{
|
|
sd_mmc_spi_err = SD_MMC_SPI_NO_ERR;
|
|
PORT->Group[1].OUT.reg |= (1 << SPI_CS_PIN);
|
|
return 0;
|
|
}
|