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BeagleV-Fire-ubuntu
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linux: build: mpfs-beaglev-fire.dtb

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Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
default-cape-symlinks
Robert Nelson 1 year ago
parent 78bd5b8dd4
commit 11aed1f766
11 changed files with 2827 additions and 3 deletions
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1
.gitignore vendored
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@ -6,6 +6,7 @@ deploy/u-boot.bin
deploy/.modules
deploy/*-modules.tar.gz
deploy/Image
deploy/*.dtb
mirror/
riscv-toolchain/
hart-software-services/

21
04_build_linux.sh
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@ -6,9 +6,25 @@ CC=${CC:-"${wdir}/riscv-toolchain/bin/riscv64-linux-"}
cd ./linux/
if [ ! -f ./.patched ] ; then
patch -p1 < ../patches/linux/0001-Add-BeagleV-Fire-device-tree.patch
patch -p1 < ../patches/linux/0001-PCIe-Change-controller-and-bridge-base-address.patch
patch -p1 < ../patches/linux/0001-GPIO-Add-Microchip-CoreGPIO-driver.patch
patch -p1 < ../patches/linux/0001-ADC-Add-Microchip-MCP356X-driver.patch
patch -p1 < ../patches/linux/0001-Microchip-QSPI-Add-regular-transfers.patch
patch -p1 < ../patches/linux/0001-BeagleV-Fire-Add-printk-to-IM219-driver-for-board-te.patch
patch -p1 < ../patches/linux/0001-MMC-SPI-Hack-to-support-non-DMA-capable-SPI-ctrl.patch
touch .patched
fi
cp -v ../patches/linux/Makefile arch/riscv/boot/dts/microchip/
make ARCH=riscv CROSS_COMPILE=${CC} clean
make ARCH=riscv CROSS_COMPILE=${CC} mpfs_defconfig
#./scripts/config --enable CONFIG_OF_OVERLAY
./scripts/config --enable CONFIG_OF_OVERLAY
./scripts/config --enable CONFIG_GPIO_MICROCHIP_CORE
./scripts/config --enable CONFIG_MCP356X
echo "make -j${CORES} ARCH=riscv CROSS_COMPILE=${CC} Image modules dtbs"
make -j${CORES} ARCH=riscv CROSS_COMPILE=${CC} Image modules dtbs
@ -27,10 +43,9 @@ tar --create --gzip --file "../${KERNEL_UTS}-modules.tar.gz" ./*
cd "${wdir}/linux/" || exit
rm -rf "${wdir}/deploy/tmp" || true
#cp -v ./arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts ../BeagleBoard-DeviceTrees/src/thead/
cp -v ./.config ../patches/linux/mpfs_defconfig
cp -v ./arch/riscv/boot/Image ../deploy/
#cp -v ./arch/riscv/boot/dts/thead/*.dtb ../deploy/
cp -v ./arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dtb ../deploy/
cd ../

1450
patches/linux/0001-ADC-Add-Microchip-MCP356X-driver.patch
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File diff suppressed because it is too large Load Diff

563
patches/linux/0001-Add-BeagleV-Fire-device-tree.patch
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@ -0,0 +1,563 @@
From 97e16ad53f7ac47279fbc559df6dd5ebb19c002b Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 6 Aug 2023 09:42:33 +0100
Subject: [PATCH] Add: BeagleV-Fire device tree.
---
.../microchip/mpfs-beaglev-fire-fabric.dtsi | 156 +++++++
.../boot/dts/microchip/mpfs-beaglev-fire.dts | 380 ++++++++++++++++++
2 files changed, 536 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts
diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi
new file mode 100644
index 000000000000..c6f2c7ed9bc2
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+#include "dt-bindings/mailbox/miv-ihc.h"
+
+/ {
+ compatible = "microchip,mpfs-icicle-reference-rtlv2210";
+
+ fabric-bus@40000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
+ <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
+ <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
+ <0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
+ <0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */
+
+// core_pwm0: pwm@40000000 {
+// compatible = "microchip,corepwm-rtl-v4";
+// reg = <0x0 0x40000000 0x0 0xF0>;
+// microchip,sync-update-mask = /bits/ 32 <0>;
+// #pwm-cells = <2>;
+// clocks = <&fabric_clk3>;
+// status = "disabled";
+// };
+
+ fabric_clk3: fabric-clk3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ fabric_clk1: fabric-clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ cape_gpios_p8: gpio@41100000 {
+ compatible = "microchip,core-gpio";
+ reg = <0x0 0x41100000 0x0 0x1000>;
+ clocks = <&fabric_clk3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios=<16>;
+ gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34",
+ "P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38",
+ "P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42",
+ "P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46";
+ };
+
+ cape_gpios_p9: gpio@41200000 {
+ compatible = "microchip,core-gpio";
+ reg = <0x0 0x41200000 0x0 0x1000>;
+ clocks = <&fabric_clk3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios=<21>;
+ gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14",
+ "P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18",
+ "P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24",
+ "P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28",
+ "P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42";
+ };
+
+ hsi_gpios: gpio@44000000 {
+ compatible = "microchip,core-gpio";
+ reg = <0x0 0x44000000 0x0 0x1000>;
+ clocks = <&fabric_clk3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios=<20>;
+ gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N", "B0_HSIO73N_C2P_CLKN",
+ "B0_HSIO70P", "B0_HSIO71P", "B0_HSIO83P", "B0_HSIO73N_C2P_CLKP",
+ "XCVR1_RX_VALID", "XCVR1_LOCK", "XCVR1_ERROR",
+ "XCVR2_RX_VALID", "XCVR2_LOCK", "XCVR2_ERROR",
+ "XCVR3_RX_VALID", "XCVR3_LOCK", "XCVR3_ERROR",
+ "XCVR_0B_REF_CLK_PLL_LOCK", "XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N";
+ };
+ };
+
+ ihc: mailbox {
+ compatible = "microchip,miv-ihc";
+ interrupt-parent = <&plic>;
+ interrupts = <IHC_HART1_INT>;
+ microchip,miv-ihc-remote-context-id = <IHC_CONTEXT_B>;
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ fabric-pcie-bus@3000000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>,
+ <0x30 0x0 0x30 0x0 0x10 0x0>;
+ dma-ranges = <0x0 0x0 0x0 0x80000000 0x0 0x4000000>,
+ <0x0 0x4000000 0x0 0xc4000000 0x0 0x6000000>,
+ <0x0 0xa000000 0x0 0x8a000000 0x0 0x8000000>,
+ <0x0 0x12000000 0x14 0x12000000 0x0 0x10000000>,
+ <0x0 0x22000000 0x10 0x22000000 0x0 0x5e000000>;
+
+ pcie: pcie@3000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ dma-noncoherent;
+ reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
+ clock-names = "fic1", "fic3";
+ ranges = <0x43000000 0x0 0x9000000 0x30 0x9000000 0x0 0xf000000>,
+ <0x1000000 0x0 0x8000000 0x30 0x8000000 0x0 0x1000000>,
+ <0x3000000 0x0 0x18000000 0x30 0x18000000 0x0 0x70000000>;
+ dma-ranges = <0x3000000 0x0 0x80000000 0x0 0x0 0x0 0x4000000>,
+ <0x3000000 0x0 0x84000000 0x0 0x4000000 0x0 0x6000000>,
+ <0x3000000 0x0 0x8a000000 0x0 0xa000000 0x0 0x8000000>,
+ <0x3000000 0x0 0x92000000 0x0 0x12000000 0x0 0x10000000>,
+ <0x3000000 0x0 0xa2000000 0x0 0x22000000 0x0 0x5e000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ status = "disabled";
+
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
+
+ refclk_ccc: cccrefclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+};
+
+&ccc_nw {
+ clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
+ <&refclk_ccc>, <&refclk_ccc>;
+ clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
+ "dll0_ref", "dll1_ref";
+ status = "okay";
+};
+
diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts
new file mode 100644
index 000000000000..0c608922e54e
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "mpfs.dtsi"
+#include "mpfs-beaglev-fire-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "BeagleBoard BeagleV-Fire";
+ compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs";
+
+ soc {
+ dma-ranges = <0x14 0x0 0x0 0x80000000 0x0 0x4000000>,
+ <0x14 0x4000000 0x0 0xc4000000 0x0 0x6000000>,
+ <0x14 0xa000000 0x0 0x8a000000 0x0 0x8000000>,
+ <0x14 0x12000000 0x14 0x12000000 0x0 0x10000000>,
+ <0x14 0x22000000 0x10 0x22000000 0x0 0x5e000000>;
+ };
+
+ aliases {
+ ethernet0 = &mac1;
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
+ serial4 = &mmuart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+
+ kernel: memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x4000000>;
+ };
+
+ ddr_cached_low: memory@8a000000 {
+ device_type = "memory";
+ reg = <0x0 0x8a000000 0x0 0x8000000>;
+ };
+
+ ddr_non_cached_low: memory@c4000000 {
+ device_type = "memory";
+ reg = <0x0 0xc4000000 0x0 0x6000000>;
+ };
+
+ ddr_cached_high: memory@1022000000 {
+ device_type = "memory";
+ reg = <0x10 0x22000000 0x0 0x5e000000>;
+ };
+
+ ddr_non_cached_high: memory@1412000000 {
+ device_type = "memory";
+ reg = <0x14 0x12000000 0x0 0x10000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hss: hss-buffer@103fc00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x10 0x3fc00000 0x0 0x400000>;
+ no-map;
+ };
+
+ dma_non_cached_low: non-cached-low-buffer {
+ compatible = "shared-dma-pool";
+ size = <0x0 0x4000000>;
+ no-map;
+ linux,dma-default;
+ alloc-ranges = <0x0 0xc4000000 0x0 0x4000000>;
+ };
+
+ dma_non_cached_high: non-cached-high-buffer {
+ compatible = "shared-dma-pool";
+ size = <0x0 0x10000000>;
+ no-map;
+ linux,dma-default;
+ alloc-ranges = <0x14 0x12000000 0x0 0x10000000>;
+ };
+ };
+
+ imx219_vana: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "imx219_vana";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+ imx219_vdig: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "imx219_vdig";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ imx219_vddl: fixedregulator@2 {
+ compatible = "regulator-fixed";
+ regulator-name = "imx219_vddl";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+
+ imx219_clk: camera-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+
+};
+
+&gpio0 {
+ ngpios=<14>;
+ gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "SD_CARD_CS", "USER_BUTTON";
+ status = "okay";
+
+ sd_card_cs {
+ gpio-hog;
+ gpios = <12 12>;
+ output_high;
+ line-name = "SD_CARD_CS";
+ };
+
+ user_button {
+ gpio-hog;
+ gpios = <13 13>;
+ input;
+ line-name = "USER_BUTTON";
+ };
+};
+
+&gpio1 {
+ ngpios=<24>;
+ gpio-line-names = "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "ADC_IRQn", "", "", "USB_OCn";
+ status = "okay";
+
+ adc_irqn {
+ gpio-hog;
+ gpios = <20 20>;
+ input;
+ line-name = "ADC_IRQn";
+ };
+
+ user_button {
+ gpio-hog;
+ gpios = <23 23>;
+ input;
+ line-name = "USB_OCn";
+ };
+
+};
+
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2",
+ "P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5",
+ "P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8",
+ "P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11",
+ "P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19",
+ "P8_PIN20", "P8_PIN21", "P8_PIN22", "P8_PIN23", "P8_PIN24",
+ "P8_PIN25", "P8_PIN26", "P8_PIN27", "P8_PIN28", "P8_PIN29",
+ "P8_PIN30",
+ "M2_W_DISABLE1", "M2_W_DISABLE2",
+ "VIO_ENABLE", "SD_DET";
+ status = "okay";
+
+ vio_enable {
+ gpio-hog;
+ gpios = <30 30>;
+ output_high;
+ line-name = "VIO_ENABLE";
+ };
+
+ sd_det {
+ gpio-hog;
+ gpios = <31 31>;
+ input;
+ line-name = "SD_DET";
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ eeprom: eeprom@50 {
+ compatible = "at,24c32";
+ reg = <0x50>;
+ };
+
+ imx219: sensor@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+ clocks = <&imx219_clk>;
+ VANA-supply = <&imx219_vana>; /* 2.8v */
+ VDIG-supply = <&imx219_vdig>; /* 1.8v */
+ VDDL-supply = <&imx219_vddl>; /* 1.2v */
+
+ port {
+ imx219_0: endpoint {
+// remote-endpoint = <&csi1_ep>;
+ data-lanes = <1 2>;
+ clock-noncontinuous;
+ link-frequencies = /bits/ 64 <456000000>;
+ };
+ };
+ };
+
+
+
+};
+
+&mac0 {
+ dma-noncoherent;
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&mac1 {
+ dma-noncoherent;
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&mbox {
+ status = "okay";
+};
+
+//&mmc {
+// status = "okay";
+// bus-width = <8>;
+// disable-wp;
+// cap-mmc-highspeed;
+// mmc-ddr-1_8v;
+// mmc-hs200-1_8v;
+//};
+
+&mmc {
+ dma-noncoherent;
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+
+&mmuart0 {
+ status = "okay";
+};
+
+&mmuart1 {
+ status = "okay";
+};
+
+//&mmuart2 {
+// status = "okay";
+//};
+
+//&mmuart3 //{
+// statu//s = "okay";
+//};//
+//
+//&mmuart4 {
+// status = "okay";
+//};
+
+//&pcie {
+// status = "okay";
+//};
+
+&qspi {
+ status = "okay";
+ cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>, <&gpio0 12 GPIO_ACTIVE_LOW>;
+ num-cs = <2>;
+
+
+ mcp3464: mcp3464@0 {
+ compatible = "microchip,mcp3464r";
+ reg = <0>; /* CE0 */
+ spi-cpol;
+ spi-cpha;
+ spi-max-frequency = <15000000>;
+ status = "okay";
+ microchip,hw-device-address = <1>;
+ };
+
+ mmc-slot@1 {
+ compatible = "mmc-spi-slot";
+ reg = <1>;
+ gpios = <&gpio2 31 1>;
+ voltage-ranges = <3300 3300>;
+ spi-max-frequency = <15000000>;
+ disable-wp;
+ };
+};
+
+&refclk {
+ clock-frequency = <125000000>;
+};
+
+&refclk_ccc {
+ clock-frequency = <50000000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&syscontroller {
+ microchip,bitstream-flash = <&sys_ctrl_flash>;
+ status = "okay";
+};
+
+&syscontroller_qspi {
+ status = "okay";
+
+ sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <20000000>;
+ spi-rx-bus-width = <1>;
+ reg = <0>;
+ };
+};
+
+
+&usb {
+ dma-noncoherent;
+ status = "okay";
+ dr_mode = "otg";
+};
--
2.25.1

45
patches/linux/0001-BeagleV-Fire-Add-printk-to-IM219-driver-for-board-te.patch
Unescape Escape View File

@ -0,0 +1,45 @@
From fa73238dfe5e29d9d77ecb2166fbae46215d59b6 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sat, 12 Aug 2023 18:14:01 +0100
Subject: [PATCH] BeagleV-Fire: Add printk to IM219 driver for board tests.
---
drivers/media/i2c/imx219.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c
index 7a14688f8c22..effb399b143f 100644
--- a/drivers/media/i2c/imx219.c
+++ b/drivers/media/i2c/imx219.c
@@ -1181,6 +1181,9 @@ static int imx219_identify_module(struct imx219 *imx219)
int ret;
u32 val;
+ printk(KERN_INFO "imx219_identify_module()\n");
+
+
ret = imx219_read_reg(imx219, IMX219_REG_CHIP_ID,
IMX219_REG_VALUE_16BIT, &val);
if (ret) {
@@ -1195,6 +1198,9 @@ static int imx219_identify_module(struct imx219 *imx219)
return -EIO;
}
+ printk(KERN_INFO "imx219_identify_module() - Success\n");
+
+
return 0;
}
@@ -1402,6 +1408,8 @@ static int imx219_probe(struct i2c_client *client)
struct imx219 *imx219;
int ret;
+ printk(KERN_INFO "imx219_probe()\n");
+
imx219 = devm_kzalloc(&client->dev, sizeof(*imx219), GFP_KERNEL);
if (!imx219)
return -ENOMEM;
--
2.25.1

371
patches/linux/0001-GPIO-Add-Microchip-CoreGPIO-driver.patch
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@ -0,0 +1,371 @@
From 49e37dfd8c7070958960ba23d0e3e005b6604940 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Fri, 21 Jul 2023 19:33:28 +0100
Subject: [PATCH] GPIO: Add Microchip CoreGPIO driver.
---
drivers/gpio/Kconfig | 8 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-microchip-core.c | 319 +++++++++++++++++++++++++++++
3 files changed, 328 insertions(+)
create mode 100644 drivers/gpio/gpio-microchip-core.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d71f5bd6f532..8e3858e34cc7 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -501,6 +501,14 @@ config GPIO_POLARFIRE_SOC
help
Say yes here to support the GPIO device on Microchip FPGAs.
+config GPIO_MICROCHIP_CORE
+ bool "Microchip FPGA soft-IP GPIO support"
+ depends on OF_GPIO
+ select GPIOLIB_IRQCHIP
+ help
+ Say yes here to support the soft-IP GPIO device on Microchip FPGAs
+
+
config GPIO_PXA
bool "PXA GPIO support"
depends on ARCH_PXA || ARCH_MMP || COMPILE_TEST
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 9be0691d9660..05a65ff04b23 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -121,6 +121,7 @@ obj-$(CONFIG_GPIO_PISOSR) += gpio-pisosr.o
obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o
obj-$(CONFIG_GPIO_POLARFIRE_SOC) += gpio-mpfs.o
+obj-$(CONFIG_GPIO_MICROCHIP_CORE) += gpio-microchip-core.o
obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o
obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
diff --git a/drivers/gpio/gpio-microchip-core.c b/drivers/gpio/gpio-microchip-core.c
new file mode 100644
index 000000000000..fd630cac4fe5
--- /dev/null
+++ b/drivers/gpio/gpio-microchip-core.c
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * Microchip CoreGPIO FPGA soft-IP GPIO controller driver
+ *
+ * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Lewis Hanly <lewis.hanly@microchip.com>
+ *
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+#define MPFS_GPIO_CTRL(i) (0x4 * (i))
+#define MAX_NUM_GPIO 32
+#define MPFS_GPIO_EN_INT 3
+#define MPFS_GPIO_EN_OUT_BUF BIT(2)
+#define MPFS_GPIO_EN_IN BIT(1)
+#define MPFS_GPIO_EN_OUT BIT(0)
+
+#define MPFS_GPIO_TYPE_INT_EDGE_BOTH 0x80
+#define MPFS_GPIO_TYPE_INT_EDGE_NEG 0x60
+#define MPFS_GPIO_TYPE_INT_EDGE_POS 0x40
+#define MPFS_GPIO_TYPE_INT_LEVEL_LOW 0x20
+#define MPFS_GPIO_TYPE_INT_LEVEL_HIGH 0x00
+#define MPFS_GPIO_TYPE_INT_MASK GENMASK(7, 5)
+#define MPFS_IRQ_REG 0x80
+#define MPFS_INP_REG 0x90
+#define MPFS_OUTP_REG 0xA0
+
+struct mpfs_gpio_chip {
+ void __iomem *base;
+ struct clk *clk;
+ raw_spinlock_t lock;
+ struct gpio_chip gc;
+};
+
+static void mpfs_gpio_assign_bit(void __iomem *addr, unsigned int bit_offset, bool value)
+{
+ unsigned long reg = readl(addr);
+
+ __assign_bit(bit_offset, &reg, value);
+ writel(reg, addr);
+}
+
+static int mpfs_gpio_direction_input(struct gpio_chip *gc, unsigned int gpio_index)
+{
+ struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
+ u32 gpio_cfg;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&mpfs_gpio->lock, flags);
+
+ gpio_cfg = readl(mpfs_gpio->base + MPFS_GPIO_CTRL(gpio_index));
+ gpio_cfg |= MPFS_GPIO_EN_IN;
+ gpio_cfg &= ~(MPFS_GPIO_EN_OUT | MPFS_GPIO_EN_OUT_BUF);
+ writel(gpio_cfg, mpfs_gpio->base + MPFS_GPIO_CTRL(gpio_index));
+
+ raw_spin_unlock_irqrestore(&mpfs_gpio->lock, flags);
+
+ return 0;
+}
+
+static int mpfs_gpio_direction_output(struct gpio_chip *gc, unsigned int gpio_index, int value)
+{
+ struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
+ u32 gpio_cfg;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&mpfs_gpio->lock, flags);
+
+ gpio_cfg = readl(mpfs_gpio->base + MPFS_GPIO_CTRL(gpio_index));
+ gpio_cfg |= MPFS_GPIO_EN_OUT | MPFS_GPIO_EN_OUT_BUF;
+ gpio_cfg &= ~MPFS_GPIO_EN_IN;
+ writel(gpio_cfg, mpfs_gpio->base + MPFS_GPIO_CTRL(gpio_index));
+
+ mpfs_gpio_assign_bit(mpfs_gpio->base + MPFS_OUTP_REG, gpio_index, value);
+
+ raw_spin_unlock_irqrestore(&mpfs_gpio->lock, flags);
+
+ return 0;
+}
+
+static int mpfs_gpio_get_direction(struct gpio_chip *gc,
+ unsigned int gpio_index)
+{
+ struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
+ u32 gpio_cfg;
+
+ gpio_cfg = readl(mpfs_gpio->base + MPFS_GPIO_CTRL(gpio_index));
+ if (gpio_cfg & MPFS_GPIO_EN_IN)
+ return GPIO_LINE_DIRECTION_IN;
+
+ return GPIO_LINE_DIRECTION_OUT;
+}
+
+static int mpfs_gpio_get(struct gpio_chip *gc,
+ unsigned int gpio_index)
+{
+ struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
+
+ return !!(readl(mpfs_gpio->base + MPFS_INP_REG) & BIT(gpio_index));
+}
+
+static void mpfs_gpio_set(struct gpio_chip *gc, unsigned int gpio_index, int value)
+{
+ struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&mpfs_gpio->lock, flags);
+
+ mpfs_gpio_assign_bit(mpfs_gpio->base + MPFS_OUTP_REG,
+ gpio_index, value);
+
+ raw_spin_unlock_irqrestore(&mpfs_gpio->lock, flags);
+}
+
+static int mpfs_gpio_irq_set_type(struct irq_data *data, unsigned int type)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+ struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
+ int gpio_index = irqd_to_hwirq(data);
+ u32 interrupt_type;
+ u32 gpio_cfg;
+ unsigned long flags;
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_BOTH:
+ interrupt_type = MPFS_GPIO_TYPE_INT_EDGE_BOTH;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ interrupt_type = MPFS_GPIO_TYPE_INT_EDGE_NEG;
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ interrupt_type = MPFS_GPIO_TYPE_INT_EDGE_POS;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ interrupt_type = MPFS_GPIO_TYPE_INT_LEVEL_HIGH;
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ interrupt_type = MPFS_GPIO_TYPE_INT_LEVEL_LOW;
+ break;
+ }
+
+ raw_spin_lock_irqsave(&mpfs_gpio->lock, flags);
+
+ gpio_cfg = readl(mpfs_gpio->base + MPFS_GPIO_CTRL(gpio_index));
+ gpio_cfg &= ~MPFS_GPIO_TYPE_INT_MASK;
+ gpio_cfg |= interrupt_type;
+ writel(gpio_cfg, mpfs_gpio->base + MPFS_GPIO_CTRL(gpio_index));
+
+ raw_spin_unlock_irqrestore(&mpfs_gpio->lock, flags);
+
+ return 0;
+}
+
+static void mpfs_gpio_irq_unmask(struct irq_data *data)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+ struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
+ int gpio_index = irqd_to_hwirq(data) % MAX_NUM_GPIO;
+
+ mpfs_gpio_direction_input(gc, gpio_index);
+ mpfs_gpio_assign_bit(mpfs_gpio->base + MPFS_IRQ_REG, gpio_index, 1);
+ mpfs_gpio_assign_bit(mpfs_gpio->base + MPFS_GPIO_CTRL(gpio_index),
+ MPFS_GPIO_EN_INT, 1);
+}
+
+static void mpfs_gpio_irq_mask(struct irq_data *data)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+ struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc);
+ int gpio_index = irqd_to_hwirq(data) % MAX_NUM_GPIO;
+
+ mpfs_gpio_assign_bit(mpfs_gpio->base + MPFS_IRQ_REG, gpio_index, 1);
+ mpfs_gpio_assign_bit(mpfs_gpio->base + MPFS_GPIO_CTRL(gpio_index),
+ MPFS_GPIO_EN_INT, 0);
+}
+
+static struct irq_chip mpfs_gpio_irqchip = {
+ .name = "mpfs",
+ .irq_set_type = mpfs_gpio_irq_set_type,
+ .irq_mask = mpfs_gpio_irq_mask,
+ .irq_unmask = mpfs_gpio_irq_unmask,
+ .flags = IRQCHIP_MASK_ON_SUSPEND,
+};
+
+static void mpfs_gpio_irq_handler(struct irq_desc *desc)
+{
+ struct irq_chip *irqchip = irq_desc_get_chip(desc);
+ struct mpfs_gpio_chip *mpfs_gpio =
+ gpiochip_get_data(irq_desc_get_handler_data(desc));
+ unsigned long status;
+ int offset;
+
+ chained_irq_enter(irqchip, desc);
+
+ status = readl(mpfs_gpio->base + MPFS_IRQ_REG);
+ for_each_set_bit(offset, &status, mpfs_gpio->gc.ngpio) {
+ mpfs_gpio_assign_bit(mpfs_gpio->base + MPFS_IRQ_REG, offset, 1);
+ generic_handle_irq(irq_find_mapping(mpfs_gpio->gc.irq.domain, offset));
+ }
+
+ chained_irq_exit(irqchip, desc);
+}
+
+static int mpfs_gpio_probe(struct platform_device *pdev)
+{
+ struct clk *clk;
+ struct device *dev = &pdev->dev;
+ struct device_node *node = pdev->dev.of_node;
+ struct mpfs_gpio_chip *mpfs_gpio;
+ struct gpio_irq_chip *girq;
+ int i, ret, ngpios, nirqs;
+
+ mpfs_gpio = devm_kzalloc(dev, sizeof(*mpfs_gpio), GFP_KERNEL);
+ if (!mpfs_gpio)
+ return -ENOMEM;
+
+ mpfs_gpio->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(mpfs_gpio->base))
+ return dev_err_probe(dev, PTR_ERR(mpfs_gpio->base), "memory allocation failure\n");
+
+ clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "devm_clk_get failed\n");
+
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to enable clock\n");
+
+ mpfs_gpio->clk = clk;
+
+ raw_spin_lock_init(&mpfs_gpio->lock);
+
+ ngpios = MAX_NUM_GPIO;
+ device_property_read_u32(dev, "ngpios", &ngpios);
+ if (ngpios > MAX_NUM_GPIO)
+ ngpios = MAX_NUM_GPIO;
+
+ mpfs_gpio->gc.direction_input = mpfs_gpio_direction_input;
+ mpfs_gpio->gc.direction_output = mpfs_gpio_direction_output;
+ mpfs_gpio->gc.get_direction = mpfs_gpio_get_direction;
+ mpfs_gpio->gc.get = mpfs_gpio_get;
+ mpfs_gpio->gc.set = mpfs_gpio_set;
+ mpfs_gpio->gc.base = -1;
+ mpfs_gpio->gc.ngpio = ngpios;
+ mpfs_gpio->gc.label = dev_name(dev);
+ mpfs_gpio->gc.parent = dev;
+ mpfs_gpio->gc.owner = THIS_MODULE;
+
+ nirqs = of_irq_count(node);
+ if (nirqs > MAX_NUM_GPIO) {
+ ret = -ENXIO;
+ goto cleanup_clock;
+ }
+ girq = &mpfs_gpio->gc.irq;
+ girq->chip = &mpfs_gpio_irqchip;
+ girq->handler = handle_simple_irq;
+ girq->parent_handler = mpfs_gpio_irq_handler;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->num_parents = nirqs;
+ girq->parents = devm_kcalloc(&pdev->dev, nirqs,
+ sizeof(*girq->parents), GFP_KERNEL);
+ if (!girq->parents) {
+ ret = -ENOMEM;
+ goto cleanup_clock;
+ }
+ for (i = 0; i < nirqs; i++)
+ girq->parents[i] = platform_get_irq(pdev, i);
+
+ ret = gpiochip_add_data(&mpfs_gpio->gc, mpfs_gpio);
+ if (ret)
+ goto cleanup_clock;
+
+ platform_set_drvdata(pdev, mpfs_gpio);
+
+ return 0;
+
+cleanup_clock:
+ clk_disable_unprepare(mpfs_gpio->clk);
+ return ret;
+}
+
+static int mpfs_gpio_remove(struct platform_device *pdev)
+{
+ struct mpfs_gpio_chip *mpfs_gpio = platform_get_drvdata(pdev);
+
+ gpiochip_remove(&mpfs_gpio->gc);
+ clk_disable_unprepare(mpfs_gpio->clk);
+
+ return 0;
+}
+
+static const struct of_device_id mpfs_of_ids[] = {
+ { .compatible = "microchip,core-gpio", },
+ { /* end of list */ }
+};
+
+static struct platform_driver mchp_core_gpio_driver = {
+ .probe = mpfs_gpio_probe,
+ .driver = {
+ .name = "microchip,core-gpio",
+ .of_match_table = mpfs_of_ids,
+ },
+ .remove = mpfs_gpio_remove,
+};
+builtin_platform_driver(mchp_core_gpio_driver);
--
2.25.1

66
patches/linux/0001-MMC-SPI-Hack-to-support-non-DMA-capable-SPI-ctrl.patch
Unescape Escape View File

@ -0,0 +1,66 @@
From 5252a0a75c390e01fc9b402660c1a28f7f4d172f Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 6 Aug 2023 11:13:27 +0100
Subject: [PATCH] MMC SPI: Hack to support non DMA capable SPI ctrl.
---
drivers/mmc/host/mmc_spi.c | 6 +++++-
drivers/spi/internals.h | 3 +++
drivers/spi/spi.c | 3 +++
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/mmc_spi.c b/drivers/mmc/host/mmc_spi.c
index cc333ad67cac..fb45c7fa431d 100644
--- a/drivers/mmc/host/mmc_spi.c
+++ b/drivers/mmc/host/mmc_spi.c
@@ -29,6 +29,9 @@
#include <asm/unaligned.h>
+//<CJ>:
+#undef CONFIG_HAS_DMA
+//#define DEBUG 1
/* NOTES:
*
@@ -1375,7 +1378,8 @@ static int mmc_spi_probe(struct spi_device *spi)
* that's the only reason not to use a few MHz for f_min (until
* the upper layer reads the target frequency from the CSD).
*/
- mmc->f_min = 400000;
+//<CJ> mmc->f_min = 400000;
+ mmc->f_min = 5000000;
mmc->f_max = spi->max_speed_hz;
host = mmc_priv(mmc);
diff --git a/drivers/spi/internals.h b/drivers/spi/internals.h
index 4a28a8395552..c49350240978 100644
--- a/drivers/spi/internals.h
+++ b/drivers/spi/internals.h
@@ -12,6 +12,9 @@
#ifndef __LINUX_SPI_INTERNALS_H
#define __LINUX_SPI_INTERNALS_H
+//<CJ>:
+#undef CONFIG_HAS_DMA
+
#include <linux/device.h>
#include <linux/dma-direction.h>
#include <linux/scatterlist.h>
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index a221478e528e..e198049cc80c 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -42,6 +42,9 @@ EXPORT_TRACEPOINT_SYMBOL(spi_transfer_stop);
#include "internals.h"
+//<CJ>:
+#undef CONFIG_HAS_DMA
+
static DEFINE_IDR(spi_master_idr);
static void spidev_release(struct device *dev)
--
2.25.1

275
patches/linux/0001-Microchip-QSPI-Add-regular-transfers.patch
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@ -0,0 +1,275 @@
From 0777b8ed4d5994b906dcfd06fa9c626b6905d655 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sun, 6 Aug 2023 09:37:40 +0100
Subject: [PATCH] Microchip QSPI: Add regular transfers.
---
drivers/spi/spi-microchip-core-qspi.c | 226 +++++++++++++++++++++++++-
1 file changed, 223 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microchip-core-qspi.c
index 33c19b98b9e2..2cce6526a507 100644
--- a/drivers/spi/spi-microchip-core-qspi.c
+++ b/drivers/spi/spi-microchip-core-qspi.c
@@ -1,3 +1,4 @@
+
// SPDX-License-Identifier: (GPL-2.0)
/*
* Microchip coreQSPI QSPI controller driver
@@ -117,10 +118,10 @@ struct mchp_coreqspi {
struct completion data_completion;
struct mutex op_lock; /* lock access to the device */
u8 *txbuf;
- u8 *rxbuf;
+ volatile u8 *rxbuf;
int irq;
- int tx_len;
- int rx_len;
+ volatile int tx_len;
+ volatile int rx_len;
};
static int mchp_coreqspi_set_mode(struct mchp_coreqspi *qspi, const struct spi_mem_op *op)
@@ -222,6 +223,68 @@ static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi, bool word)
}
}
+static inline void mchp_coreqspi_write_read_op(struct mchp_coreqspi *qspi, bool last)
+{
+ u32 frames, control, data;
+ qspi->rx_len = qspi->tx_len;
+
+ control = readl_relaxed(qspi->regs + REG_CONTROL);
+ control |= CONTROL_FLAGSX4;
+ writel_relaxed(control, qspi->regs + REG_CONTROL);
+
+ while (qspi->tx_len >= 4) {
+ while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
+ ;
+
+ data = *(u32 *)qspi->txbuf;
+ qspi->txbuf += 4;
+ qspi->tx_len -= 4;
+ writel_relaxed(data, qspi->regs + REG_X4_TX_DATA);
+
+ if (qspi->rx_len >= 8) {
+ if (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXAVAILABLE) {
+ data = readl_relaxed(qspi->regs + REG_X4_RX_DATA);
+ *(u32 *)qspi->rxbuf = data;
+ qspi->rxbuf += 4;
+ qspi->rx_len -= 4;
+ }
+ }
+ }
+
+ if (!last ) {
+ while (qspi->rx_len >= 4) {
+ while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
+ ;
+ data = readl_relaxed(qspi->regs + REG_X4_RX_DATA);
+ *(u32 *)qspi->rxbuf = data;
+ qspi->rxbuf += 4;
+ qspi->rx_len -= 4;
+ }
+ }
+
+ if (qspi->tx_len) {
+ control &= ~CONTROL_FLAGSX4;
+ writel_relaxed(control, qspi->regs + REG_CONTROL);
+
+
+ while (qspi->tx_len--) {
+ while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
+ ;
+ data = *qspi->txbuf++;
+ writel_relaxed(data, qspi->regs + REG_TX_DATA);
+ }
+ if (!last) {
+ while (qspi->rx_len--) {
+ while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
+ ;
+ data = readl_relaxed(qspi->regs + REG_RX_DATA);
+ *qspi->rxbuf++ = (data & 0xFF);
+ }
+ }
+ }
+}
+
+
static void mchp_coreqspi_enable_ints(struct mchp_coreqspi *qspi)
{
u32 mask = IEN_TXDONE |
@@ -497,6 +560,160 @@ static const struct spi_controller_mem_ops mchp_coreqspi_mem_ops = {
.exec_op = mchp_coreqspi_exec_op,
};
+static int mchp_coreqspi_transfer_one_message(struct spi_controller *ctlr,
+ struct spi_message *m)
+{
+ struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr);
+ struct spi_transfer *t = NULL;
+ u32 control, frames, status;
+ u32 total_bytes, cmd_bytes = 0, idle_cycles = 0;
+ int ret;
+ bool quad = false, dual = false;
+ bool keep_cs = false;
+
+ mutex_lock(&qspi->op_lock);
+ ret = readl_poll_timeout(qspi->regs + REG_STATUS, status,
+ (status & STATUS_READY), 0,
+ TIMEOUT_MS);
+ if (ret) {
+ dev_err(&ctlr->dev,
+ "Timeout waiting on QSPI ready.\n");
+ return -ETIMEDOUT;
+ }
+
+ ret = mchp_coreqspi_setup_clock(qspi, m->spi);
+ if (ret)
+ goto error;
+
+ if (m->spi->cs_gpiod) {
+ if (m->spi->mode & SPI_CS_HIGH) {
+ gpiod_set_value(m->spi->cs_gpiod, 0);
+ } else {
+ gpiod_set_value(m->spi->cs_gpiod, 1);
+ }
+ }
+
+ control = readl_relaxed(qspi->regs + REG_CONTROL);
+ control &= ~(CONTROL_MODE12_MASK |
+ CONTROL_MODE0);
+ writel_relaxed(control, qspi->regs + REG_CONTROL);
+
+ reinit_completion(&qspi->data_completion);
+
+ /* Check the total bytes and command bytes */
+ list_for_each_entry(t, &m->transfers, transfer_list) {
+ total_bytes += t->len;
+ if ((!cmd_bytes) && !(t->tx_buf && t->rx_buf))
+ cmd_bytes = t->len;
+ if (!t->rx_buf)
+ cmd_bytes = total_bytes;
+ if (t->tx_nbits == SPI_NBITS_QUAD || t->rx_nbits == SPI_NBITS_QUAD)
+ quad = true;
+ else if (t->tx_nbits == SPI_NBITS_DUAL || t->rx_nbits == SPI_NBITS_DUAL)
+ dual = true;
+ }
+
+ control = readl_relaxed(qspi->regs + REG_CONTROL);
+ if (quad) {
+ control |= (CONTROL_MODE0 | CONTROL_MODE12_EX_RW);
+ } else if (dual) {
+ control &= ~CONTROL_MODE0;
+ control |= CONTROL_MODE12_FULL;
+ } else {
+ control &= ~(CONTROL_MODE12_MASK |
+ CONTROL_MODE0);
+ }
+
+ writel_relaxed(control, qspi->regs + REG_CONTROL);
+ frames = total_bytes & BYTESUPPER_MASK;
+ writel_relaxed(frames, qspi->regs + REG_FRAMESUP);
+ frames = total_bytes & BYTESLOWER_MASK;
+ frames |= cmd_bytes << FRAMES_CMDBYTES_SHIFT;
+ frames |= idle_cycles << FRAMES_IDLE_SHIFT;
+ control = readl_relaxed(qspi->regs + REG_CONTROL);
+ if (control & CONTROL_MODE12_MASK)
+ frames |= (1 << FRAMES_SHIFT);
+
+ frames |= FRAMES_FLAGWORD;
+ writel_relaxed(frames, qspi->regs + REG_FRAMES);
+
+ list_for_each_entry(t, &m->transfers, transfer_list) {
+
+ if ((t->tx_buf) && (t->rx_buf)){
+ bool last = false;
+ qspi->txbuf = (u8 *)t->tx_buf;
+ qspi->rxbuf = (u8 *)t->rx_buf;
+ qspi->tx_len = t->len;
+ if (list_is_last(&t->transfer_list, &m->transfers))
+ last = true;
+ mchp_coreqspi_write_read_op(qspi, last);
+ } else if (t->tx_buf) {
+ qspi->txbuf = (u8 *)t->tx_buf;
+ qspi->tx_len = t->len;
+ mchp_coreqspi_write_op(qspi, true);
+ } else {
+ qspi->rxbuf = (u8 *)t->rx_buf;
+ qspi->rx_len = t->len;
+ }
+
+ if (t->cs_change) {
+ if (list_is_last(&t->transfer_list,
+ &m->transfers)) {
+ keep_cs = true;
+ } else {
+ if (!t->cs_off) {
+// gpiod_set_value(m->spi->cs_gpiod, 0);
+ if (m->spi->mode & SPI_CS_HIGH) {
+ gpiod_set_value(m->spi->cs_gpiod, 0);
+ } else {
+ gpiod_set_value(m->spi->cs_gpiod, 1);
+ }
+ }
+// _spi_transfer_cs_change_delay(m, t);
+ if (!list_next_entry(t, transfer_list)->cs_off) {
+// spi_set_cs(m->spi, true, false);
+ if (m->spi->mode & SPI_CS_HIGH) {
+// gpiod_set_value(m->spi->cs_gpiod, 0);
+ gpiod_set_value(m->spi->cs_gpiod, 1);
+ } else {
+// gpiod_set_value(m->spi->cs_gpiod, 1);
+ gpiod_set_value(m->spi->cs_gpiod, 0);
+ }
+// gpiod_set_value(m->spi->cs_gpiod, 1);
+ }
+ }
+ } else if (!list_is_last(&t->transfer_list, &m->transfers) &&
+ t->cs_off != list_next_entry(t, transfer_list)->cs_off) {
+// spi_set_cs(m->spi, t->cs_off, false);
+ if (m->spi->mode & SPI_CS_HIGH) {
+ gpiod_set_value(m->spi->cs_gpiod, !t->cs_off);
+ } else {
+ gpiod_set_value(m->spi->cs_gpiod, !t->cs_off);
+ }
+ }
+
+
+
+ }
+
+ mchp_coreqspi_enable_ints(qspi);
+
+ if (!wait_for_completion_timeout(&qspi->data_completion, msecs_to_jiffies(1000)))
+ ret = -ETIMEDOUT;
+
+ m->actual_length = total_bytes;
+
+error:
+ if (ret != 0 || !keep_cs)
+ gpiod_set_value(m->spi->cs_gpiod, 0);
+
+ m->status = ret;
+ spi_finalize_current_message(ctlr);
+ mutex_unlock(&qspi->op_lock);
+ mchp_coreqspi_disable_ints(qspi);
+ return ret;
+}
+
static int mchp_coreqspi_probe(struct platform_device *pdev)
{
struct spi_controller *ctlr;
@@ -550,6 +767,9 @@ static int mchp_coreqspi_probe(struct platform_device *pdev)
ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
SPI_TX_DUAL | SPI_TX_QUAD;
ctlr->dev.of_node = np;
+ ctlr->transfer_one_message = mchp_coreqspi_transfer_one_message;
+ ctlr->num_chipselect = 2;
+ ctlr->use_gpio_descriptors = true;
ret = devm_spi_register_controller(&pdev->dev, ctlr);
if (ret) {
--
2.25.1

27
patches/linux/0001-PCIe-Change-controller-and-bridge-base-address.patch
Unescape Escape View File

@ -0,0 +1,27 @@
From a9ba71fb483fdacbc4f0d1d3ab2ec3013cc69f17 Mon Sep 17 00:00:00 2001
From: vauban353 <vauban353@gmail.com>
Date: Sat, 5 Nov 2022 17:47:50 +0000
Subject: [PATCH] PCIe: Change controller and bridge base address.
---
drivers/pci/controller/pcie-microchip-host.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c
index 4b37b3403b85..04ca330f643d 100644
--- a/drivers/pci/controller/pcie-microchip-host.c
+++ b/drivers/pci/controller/pcie-microchip-host.c
@@ -24,8 +24,8 @@
#define MC_NUM_MSI_IRQS_CODED 5
/* PCIe Bridge Phy and Controller Phy offsets */
-#define MC_PCIE1_BRIDGE_ADDR 0x00008000u
-#define MC_PCIE1_CTRL_ADDR 0x0000a000u
+#define MC_PCIE1_BRIDGE_ADDR 0x00004000u
+#define MC_PCIE1_CTRL_ADDR 0x00006000u
#define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR)
#define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR)
--
2.25.1

9
patches/linux/Makefile
Unescape Escape View File

@ -0,0 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit-context-a.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-video-kit.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

2
patches/linux/mpfs_defconfig
Unescape Escape View File

@ -1977,6 +1977,7 @@ CONFIG_GPIO_CDEV_V1=y
# CONFIG_GPIO_HLWD is not set
# CONFIG_GPIO_MB86S7X is not set
CONFIG_GPIO_POLARFIRE_SOC=y
CONFIG_GPIO_MICROCHIP_CORE=y
# CONFIG_GPIO_SIFIVE is not set
# CONFIG_GPIO_XILINX is not set
# CONFIG_GPIO_AMD_FCH is not set
@ -3468,6 +3469,7 @@ CONFIG_IIO_SW_TRIGGER=m
# CONFIG_MCP320X is not set
# CONFIG_MCP3422 is not set
# CONFIG_MCP3911 is not set
CONFIG_MCP356X=m
# CONFIG_NAU7802 is not set
# CONFIG_RICHTEK_RTQ6056 is not set
# CONFIG_SD_ADC_MODULATOR is not set

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