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BeagleV-Fire-ubuntu/patches/u-boot/microchip-mpfs-icicle-kit.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 Microchip Technology Inc.
* Padmarao Begari <padmarao.begari@microchip.com>
*/
/dts-v1/;
#include "microchip-mpfs.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
"microchip,mpfs";
aliases {
serial0 = &uart0;
ethernet0 = &mac1;
spi0 = &qspi;
};
chosen {
stdout-path = "serial0";
};
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
kernel: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x4000000>;
label = "kernel";
};
ddr_cached_low: memory@8a000000 {
device_type = "memory";
reg = <0x0 0x8a000000 0x0 0x8000000>;
label = "cached-low";
};
ddr_non_cached_low: memory@c4000000 {
device_type = "memory";
reg = <0x0 0xc4000000 0x0 0x6000000>;
label = "non-cached-low";
};
ddr_cached_high: memory@1022000000 {
device_type = "memory";
reg = <0x10 0x22000000 0x0 0x5e000000>;
label = "cached-high";
};
ddr_non_cached_high: memory@1412000000 {
device_type = "memory";
reg = <0x14 0x12000000 0x0 0x10000000>;
label = "non-cached-high";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hss: hss-buffer {
compatible = "shared-dma-pool";
reg = <0x10 0x3fc00000 0x0 0x400000>;
no-map;
};
dma_non_cached_low: non-cached-low-buffer {
compatible = "shared-dma-pool";
size = <0x0 0x4000000>;
no-map;
linux,dma-default;
alloc-ranges = <0x0 0xc4000000 0x0 0x4000000>;
dma-ranges = <0x0 0xc4000000 0x0 0xc4000000 0x0 0x4000000>;
};
dma_non_cached_high: non-cached-high-buffer {
compatible = "shared-dma-pool";
size = <0x0 0x10000000>;
no-map;
linux,dma-default;
alloc-ranges = <0x14 0x12000000 0x0 0x10000000>;
dma-ranges = <0x14 0x12000000 0x14 0x12000000 0x0 0x10000000>;
};
fabricbuf0ddrc: buffer@88000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x88000000 0x0 0x2000000>;
no-map;
};
fabricbuf1ddrnc: buffer@c8000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xc8000000 0x0 0x2000000>;
no-map;
};
fabricbuf2ddrncwcb: buffer@d8000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xd8000000 0x0 0x2000000>;
no-map;
};
};
udmabuf0 {
compatible = "ikwzm,u-dma-buf";
device-name = "udmabuf-ddr-c0";
minor-number = <0>;
size = <0x0 0x2000000>;
memory-region = <&fabricbuf0ddrc>;
sync-mode = <3>;
};
udmabuf1 {
compatible = "ikwzm,u-dma-buf";
device-name = "udmabuf-ddr-nc0";
minor-number = <1>;
size = <0x0 0x2000000>;
memory-region = <&fabricbuf1ddrnc>;
sync-mode = <3>;
};
udmabuf2 {
compatible = "ikwzm,u-dma-buf";
device-name = "udmabuf-ddr-nc-wcb0";
minor-number = <2>;
size = <0x0 0x2000000>;
memory-region = <&fabricbuf2ddrncwcb>;
sync-mode = <3>;
};
};
&refclk {
clock-frequency = <125000000>;
};
&uart1 {
status = "okay";
};
&mmc {
status = "okay";
bus-width = <4>;
disable-wp;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
};
&i2c1 {
status = "okay";
clock-frequency = <100000>;
pac193x: pac193x@10 {
compatible = "microchip,pac1934";
reg = <0x10>;
samp-rate = <64>;
status = "okay";
ch1: channel0 {
uohms-shunt-res = <10000>;
rail-name = "VDDREG";
channel_enabled;
};
ch2: channel1 {
uohms-shunt-res = <10000>;
rail-name = "VDDA25";
channel_enabled;
};
ch3: channel2 {
uohms-shunt-res = <10000>;
rail-name = "VDD25";
channel_enabled;
};
ch4: channel3 {
uohms-shunt-res = <10000>;
rail-name = "VDDA_REG";
channel_enabled;
};
};
};
&mac1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@9 {
reg = <9>;
};
};
&qspi {
status = "okay";
num-cs = <1>;
flash0: spi-nand@0 {
compatible = "spi-nand";
reg = <0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-max-frequency = <20000000>;
spi-cpol;
spi-cpha;
};
};