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156 lines
5.0 KiB
Plaintext
156 lines
5.0 KiB
Plaintext
1 year ago
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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#include "dt-bindings/mailbox/miv-ihc.h"
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/ {
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compatible = "microchip,mpfs-icicle-reference-rtlv2210";
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fabric-bus@40000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
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<0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
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<0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
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<0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
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<0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */
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// core_pwm0: pwm@40000000 {
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// compatible = "microchip,corepwm-rtl-v4";
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// reg = <0x0 0x40000000 0x0 0xF0>;
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// microchip,sync-update-mask = /bits/ 32 <0>;
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// #pwm-cells = <2>;
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// clocks = <&fabric_clk3>;
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// status = "disabled";
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// };
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fabric_clk3: fabric-clk3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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fabric_clk1: fabric-clk1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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cape_gpios_p8: gpio@41100000 {
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compatible = "microchip,core-gpio";
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reg = <0x0 0x41100000 0x0 0x1000>;
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clocks = <&fabric_clk3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios=<16>;
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gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34",
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"P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38",
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"P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42",
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"P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46";
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};
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cape_gpios_p9: gpio@41200000 {
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compatible = "microchip,core-gpio";
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reg = <0x0 0x41200000 0x0 0x1000>;
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clocks = <&fabric_clk3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios=<21>;
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gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14",
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"P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18",
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"P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24",
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"P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28",
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"P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42";
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};
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hsi_gpios: gpio@44000000 {
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compatible = "microchip,core-gpio";
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reg = <0x0 0x44000000 0x0 0x1000>;
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clocks = <&fabric_clk3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios=<20>;
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gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N", "B0_HSIO73N_C2P_CLKN",
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"B0_HSIO70P", "B0_HSIO71P", "B0_HSIO83P", "B0_HSIO73N_C2P_CLKP",
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"XCVR1_RX_VALID", "XCVR1_LOCK", "XCVR1_ERROR",
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"XCVR2_RX_VALID", "XCVR2_LOCK", "XCVR2_ERROR",
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"XCVR3_RX_VALID", "XCVR3_LOCK", "XCVR3_ERROR",
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"XCVR_0B_REF_CLK_PLL_LOCK", "XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N";
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};
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};
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ihc: mailbox {
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compatible = "microchip,miv-ihc";
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interrupt-parent = <&plic>;
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interrupts = <IHC_HART1_INT>;
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microchip,miv-ihc-remote-context-id = <IHC_CONTEXT_B>;
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#mbox-cells = <1>;
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status = "disabled";
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};
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fabric-pcie-bus@3000000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>,
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<0x30 0x0 0x30 0x0 0x10 0x0>;
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dma-ranges = <0x0 0x0 0x0 0x80000000 0x0 0x4000000>,
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<0x0 0x4000000 0x0 0xc4000000 0x0 0x6000000>,
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<0x0 0xa000000 0x0 0x8a000000 0x0 0x8000000>,
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<0x0 0x12000000 0x14 0x12000000 0x0 0x10000000>,
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<0x0 0x22000000 0x10 0x22000000 0x0 0x5e000000>;
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pcie: pcie@3000000000 {
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compatible = "microchip,pcie-host-1.0";
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#address-cells = <0x3>;
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#interrupt-cells = <0x1>;
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#size-cells = <0x2>;
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device_type = "pci";
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dma-noncoherent;
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reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
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reg-names = "cfg", "apb";
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bus-range = <0x0 0x7f>;
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interrupt-parent = <&plic>;
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interrupts = <119>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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interrupt-map-mask = <0 0 0 7>;
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clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
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clock-names = "fic1", "fic3";
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ranges = <0x43000000 0x0 0x9000000 0x30 0x9000000 0x0 0xf000000>,
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<0x1000000 0x0 0x8000000 0x30 0x8000000 0x0 0x1000000>,
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<0x3000000 0x0 0x18000000 0x30 0x18000000 0x0 0x70000000>;
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dma-ranges = <0x3000000 0x0 0x80000000 0x0 0x0 0x0 0x4000000>,
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<0x3000000 0x0 0x84000000 0x0 0x4000000 0x0 0x6000000>,
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<0x3000000 0x0 0x8a000000 0x0 0xa000000 0x0 0x8000000>,
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<0x3000000 0x0 0x92000000 0x0 0x12000000 0x0 0x10000000>,
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<0x3000000 0x0 0xa2000000 0x0 0x22000000 0x0 0x5e000000>;
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msi-parent = <&pcie>;
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msi-controller;
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status = "disabled";
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pcie_intc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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refclk_ccc: cccrefclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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&ccc_nw {
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clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
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<&refclk_ccc>, <&refclk_ccc>;
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clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
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"dll0_ref", "dll1_ref";
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status = "okay";
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};
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