You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
72 lines
2.0 KiB
Plaintext
72 lines
2.0 KiB
Plaintext
1 year ago
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||
|
|
/* Copyright (c) 2020-2021 Microchip Technology Inc */
|
||
|
|
|
||
|
|
/ {
|
||
|
|
compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
|
||
|
|
"microchip,mpfs";
|
||
|
|
|
||
|
|
core_pwm0: pwm@40000000 {
|
||
|
|
compatible = "microchip,corepwm-rtl-v4";
|
||
|
|
reg = <0x0 0x40000000 0x0 0xF0>;
|
||
|
|
microchip,sync-update-mask = /bits/ 32 <0>;
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c2: i2c@40000200 {
|
||
|
|
compatible = "microchip,corei2c-rtl-v7";
|
||
|
|
reg = <0x0 0x40000200 0x0 0x100>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
|
||
|
|
interrupt-parent = <&plic>;
|
||
|
|
interrupts = <122>;
|
||
|
|
clock-frequency = <100000>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
pcie: pcie@3000000000 {
|
||
|
|
compatible = "microchip,pcie-host-1.0";
|
||
|
|
#address-cells = <0x3>;
|
||
|
|
#interrupt-cells = <0x1>;
|
||
|
|
#size-cells = <0x2>;
|
||
|
|
device_type = "pci";
|
||
|
|
reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
|
||
|
|
reg-names = "cfg", "apb";
|
||
|
|
bus-range = <0x0 0x7f>;
|
||
|
|
interrupt-parent = <&plic>;
|
||
|
|
interrupts = <119>;
|
||
|
|
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||
|
|
<0 0 0 2 &pcie_intc 1>,
|
||
|
|
<0 0 0 3 &pcie_intc 2>,
|
||
|
|
<0 0 0 4 &pcie_intc 3>;
|
||
|
|
interrupt-map-mask = <0 0 0 7>;
|
||
|
|
clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
|
||
|
|
clock-names = "fic1", "fic3";
|
||
|
|
ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
|
||
|
|
dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
|
||
|
|
msi-parent = <&pcie>;
|
||
|
|
msi-controller;
|
||
|
|
status = "disabled";
|
||
|
|
pcie_intc: interrupt-controller {
|
||
|
|
#address-cells = <0>;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
refclk_ccc: cccrefclk {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&ccc_nw {
|
||
|
|
clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
|
||
|
|
<&refclk_ccc>, <&refclk_ccc>;
|
||
|
|
clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
|
||
|
|
"dll0_ref", "dll1_ref";
|
||
|
|
status = "okay";
|
||
|
|
};
|