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ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a/same54p20a_test.lss

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same54p20a_test.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000438 00000000 00000000 00010000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .relocate 00000000 20000000 20000000 00010438 2**0
CONTENTS
2 .bkupram 00000000 47000000 47000000 00010438 2**0
CONTENTS
3 .qspi 00000000 04000000 04000000 00010438 2**0
CONTENTS
4 .bss 0000001c 20000000 20000000 00020000 2**2
ALLOC
5 .stack 00010004 2000001c 2000001c 00020000 2**0
ALLOC
6 .ARM.attributes 0000002a 00000000 00000000 00010438 2**0
CONTENTS, READONLY
7 .comment 00000059 00000000 00000000 00010462 2**0
CONTENTS, READONLY
8 .debug_info 000020f7 00000000 00000000 000104bb 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_abbrev 000002bf 00000000 00000000 000125b2 2**0
CONTENTS, READONLY, DEBUGGING
10 .debug_loc 00000063 00000000 00000000 00012871 2**0
CONTENTS, READONLY, DEBUGGING
11 .debug_aranges 00000040 00000000 00000000 000128d4 2**0
CONTENTS, READONLY, DEBUGGING
12 .debug_macro 00025f3d 00000000 00000000 00012914 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_line 00001022 00000000 00000000 00038851 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_str 000f139e 00000000 00000000 00039873 2**0
CONTENTS, READONLY, DEBUGGING
15 .debug_frame 00000084 00000000 00000000 0012ac14 2**2
CONTENTS, READONLY, DEBUGGING
16 .debug_ranges 00000010 00000000 00000000 0012ac98 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00000000 <exception_table>:
0: 20 00 01 20 d3 02 00 00 d1 02 00 00 d1 02 00 00 .. ............
10: d1 02 00 00 d1 02 00 00 d1 02 00 00 00 00 00 00 ................
...
2c: d1 02 00 00 d1 02 00 00 00 00 00 00 d1 02 00 00 ................
3c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
4c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
5c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
6c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
7c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
8c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
9c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
ac: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
bc: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
cc: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
dc: d1 02 00 00 d1 02 00 00 d1 02 00 00 00 00 00 00 ................
...
f4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
104: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
114: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
124: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
134: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
144: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
154: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
164: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
174: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
184: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
194: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
1a4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
1b4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
1c4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
1d4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
1e4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
1f4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
204: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
214: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
224: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
234: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
244: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
254: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................
00000264 <__do_global_dtors_aux>:
264: b510 push {r4, lr}
266: 4c05 ldr r4, [pc, #20] ; (27c <__do_global_dtors_aux+0x18>)
268: 7823 ldrb r3, [r4, #0]
26a: b933 cbnz r3, 27a <__do_global_dtors_aux+0x16>
26c: 4b04 ldr r3, [pc, #16] ; (280 <__do_global_dtors_aux+0x1c>)
26e: b113 cbz r3, 276 <__do_global_dtors_aux+0x12>
270: 4804 ldr r0, [pc, #16] ; (284 <__do_global_dtors_aux+0x20>)
272: f3af 8000 nop.w
276: 2301 movs r3, #1
278: 7023 strb r3, [r4, #0]
27a: bd10 pop {r4, pc}
27c: 20000000 .word 0x20000000
280: 00000000 .word 0x00000000
284: 00000438 .word 0x00000438
00000288 <frame_dummy>:
288: 4b0c ldr r3, [pc, #48] ; (2bc <frame_dummy+0x34>)
28a: b143 cbz r3, 29e <frame_dummy+0x16>
28c: 480c ldr r0, [pc, #48] ; (2c0 <frame_dummy+0x38>)
28e: 490d ldr r1, [pc, #52] ; (2c4 <frame_dummy+0x3c>)
290: b510 push {r4, lr}
292: f3af 8000 nop.w
296: 480c ldr r0, [pc, #48] ; (2c8 <frame_dummy+0x40>)
298: 6803 ldr r3, [r0, #0]
29a: b923 cbnz r3, 2a6 <frame_dummy+0x1e>
29c: bd10 pop {r4, pc}
29e: 480a ldr r0, [pc, #40] ; (2c8 <frame_dummy+0x40>)
2a0: 6803 ldr r3, [r0, #0]
2a2: b933 cbnz r3, 2b2 <frame_dummy+0x2a>
2a4: 4770 bx lr
2a6: 4b09 ldr r3, [pc, #36] ; (2cc <frame_dummy+0x44>)
2a8: 2b00 cmp r3, #0
2aa: d0f7 beq.n 29c <frame_dummy+0x14>
2ac: e8bd 4010 ldmia.w sp!, {r4, lr}
2b0: 4718 bx r3
2b2: 4b06 ldr r3, [pc, #24] ; (2cc <frame_dummy+0x44>)
2b4: 2b00 cmp r3, #0
2b6: d0f5 beq.n 2a4 <frame_dummy+0x1c>
2b8: 4718 bx r3
2ba: bf00 nop
2bc: 00000000 .word 0x00000000
2c0: 00000438 .word 0x00000438
2c4: 20000004 .word 0x20000004
2c8: 00000438 .word 0x00000438
2cc: 00000000 .word 0x00000000
000002d0 <Dummy_Handler>:
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
2d0: e7fe b.n 2d0 <Dummy_Handler>
000002d2 <Reset_Handler>:
{
2d2: b508 push {r3, lr}
if (pSrc != pDest) {
2d4: 4a0f ldr r2, [pc, #60] ; (314 <Reset_Handler+0x42>)
2d6: 4b10 ldr r3, [pc, #64] ; (318 <Reset_Handler+0x46>)
2d8: 429a cmp r2, r3
2da: d10e bne.n 2fa <Reset_Handler+0x28>
{
2dc: 4b0f ldr r3, [pc, #60] ; (31c <Reset_Handler+0x4a>)
for (pDest = &_szero; pDest < &_ezero;) {
2de: 4a10 ldr r2, [pc, #64] ; (320 <Reset_Handler+0x4e>)
*pDest++ = 0;
2e0: 2100 movs r1, #0
for (pDest = &_szero; pDest < &_ezero;) {
2e2: 4293 cmp r3, r2
2e4: d312 bcc.n 30c <Reset_Handler+0x3a>
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
2e6: 4b0f ldr r3, [pc, #60] ; (324 <Reset_Handler+0x52>)
2e8: 4a0f ldr r2, [pc, #60] ; (328 <Reset_Handler+0x56>)
2ea: f023 037f bic.w r3, r3, #127 ; 0x7f
2ee: 6093 str r3, [r2, #8]
__libc_init_array();
2f0: f000 f86e bl 3d0 <__libc_init_array>
main();
2f4: f000 f81c bl 330 <main>
2f8: e7fe b.n 2f8 <Reset_Handler+0x26>
for (; pDest < &_erelocate;) {
2fa: 490c ldr r1, [pc, #48] ; (32c <Reset_Handler+0x5a>)
2fc: 3a04 subs r2, #4
2fe: 428b cmp r3, r1
300: d2ec bcs.n 2dc <Reset_Handler+0xa>
*pDest++ = *pSrc++;
302: f852 0f04 ldr.w r0, [r2, #4]!
306: f843 0b04 str.w r0, [r3], #4
30a: e7f8 b.n 2fe <Reset_Handler+0x2c>
*pDest++ = 0;
30c: f843 1b04 str.w r1, [r3], #4
310: e7e7 b.n 2e2 <Reset_Handler+0x10>
312: bf00 nop
314: 00000438 .word 0x00000438
318: 20000000 .word 0x20000000
31c: 20000000 .word 0x20000000
320: 2000001c .word 0x2000001c
324: 00000000 .word 0x00000000
328: e000ed00 .word 0xe000ed00
32c: 20000000 .word 0x20000000
00000330 <main>:
// Run with 12mhz external crystal on XOSC0
// Automatic Loop Control
// 0 - disable
// 1 - enable
OSCCTRL->XOSCCTRL[0].bit.ENALC = 1;
330: 4b24 ldr r3, [pc, #144] ; (3c4 <main+0x94>)
332: 695a ldr r2, [r3, #20]
334: f442 4200 orr.w r2, r2, #32768 ; 0x8000
338: 615a str r2, [r3, #20]
// Current Multiplier
// 6 - >24MHz to 48MHz
// 5 - >16MHz to 24MHz
// 4 - >8MHz to 16MHz
// 3 - 8MHz
OSCCTRL->XOSCCTRL[0].bit.IMULT = 4;
33a: 695a ldr r2, [r3, #20]
33c: 2104 movs r1, #4
33e: f361 22ce bfi r2, r1, #11, #4
342: 615a str r2, [r3, #20]
// 3 - >24MHz to 48MHz
// 3 - >16MHz to 24MHz
// 3 - >8MHz to 16MHz
// 2 - 8MHz
OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3;
344: 695a ldr r2, [r3, #20]
346: f442 62c0 orr.w r2, r2, #1536 ; 0x600
34a: 615a str r2, [r3, #20]
OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0;
34c: 695a ldr r2, [r3, #20]
34e: f36f 12c7 bfc r2, #7, #1
352: 615a str r2, [r3, #20]
OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1;
354: 695a ldr r2, [r3, #20]
356: 430a orrs r2, r1
358: 615a str r2, [r3, #20]
OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1;
35a: 695a ldr r2, [r3, #20]
35c: f042 0202 orr.w r2, r2, #2
360: 615a str r2, [r3, #20]
while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
362: 691a ldr r2, [r3, #16]
364: 07d2 lsls r2, r2, #31
366: d5fc bpl.n 362 <main+0x32>
OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0;
368: 6b5a ldr r2, [r3, #52] ; 0x34
36a: f36f 4214 bfc r2, #16, #5
36e: 635a str r2, [r3, #52] ; 0x34
OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119;
370: 6b5a ldr r2, [r3, #52] ; 0x34
372: 2177 movs r1, #119 ; 0x77
374: f361 020c bfi r2, r1, #0, #13
378: 635a str r2, [r3, #52] ; 0x34
OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5;
37a: 6b9a ldr r2, [r3, #56] ; 0x38
37c: 2105 movs r1, #5
37e: f361 421a bfi r2, r1, #16, #11
382: 639a str r2, [r3, #56] ; 0x38
// 0 - GCLK
// 1 - XOSC32
// 2 - XOSC0
// 3 - XOSC1
OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2;
384: 6b9a ldr r2, [r3, #56] ; 0x38
386: 2102 movs r1, #2
388: f361 1247 bfi r2, r1, #5, #3
38c: 639a str r2, [r3, #56] ; 0x38
OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
38e: f893 2030 ldrb.w r2, [r3, #48] ; 0x30
392: f36f 12c7 bfc r2, #7, #1
396: f883 2030 strb.w r2, [r3, #48] ; 0x30
OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;
39a: f893 2030 ldrb.w r2, [r3, #48] ; 0x30
39e: 430a orrs r2, r1
3a0: f883 2030 strb.w r2, [r3, #48] ; 0x30
// wait for pll to be locked and ready
while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK
3a4: 4b07 ldr r3, [pc, #28] ; (3c4 <main+0x94>)
3a6: 6c1a ldr r2, [r3, #64] ; 0x40
3a8: 07d0 lsls r0, r2, #31
3aa: d5fc bpl.n 3a6 <main+0x76>
|| 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY);
3ac: 6c1a ldr r2, [r3, #64] ; 0x40
3ae: 0791 lsls r1, r2, #30
3b0: d5f9 bpl.n 3a6 <main+0x76>
// Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB
GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;
3b2: 4b05 ldr r3, [pc, #20] ; (3c8 <main+0x98>)
3b4: 4a05 ldr r2, [pc, #20] ; (3cc <main+0x9c>)
3b6: 621a str r2, [r3, #32]
while(1 == GCLK->SYNCBUSY.bit.GENCTRL0);
3b8: 685a ldr r2, [r3, #4]
3ba: 0752 lsls r2, r2, #29
3bc: d4fc bmi.n 3b8 <main+0x88>
asm volatile("nop");
3be: bf00 nop
3c0: e7fe b.n 3c0 <main+0x90>
3c2: bf00 nop
3c4: 40001000 .word 0x40001000
3c8: 40001c00 .word 0x40001c00
3cc: 00010107 .word 0x00010107
000003d0 <__libc_init_array>:
3d0: b570 push {r4, r5, r6, lr}
3d2: 4e0d ldr r6, [pc, #52] ; (408 <__libc_init_array+0x38>)
3d4: 4c0d ldr r4, [pc, #52] ; (40c <__libc_init_array+0x3c>)
3d6: 1ba4 subs r4, r4, r6
3d8: 10a4 asrs r4, r4, #2
3da: 2500 movs r5, #0
3dc: 42a5 cmp r5, r4
3de: d109 bne.n 3f4 <__libc_init_array+0x24>
3e0: 4e0b ldr r6, [pc, #44] ; (410 <__libc_init_array+0x40>)
3e2: 4c0c ldr r4, [pc, #48] ; (414 <__libc_init_array+0x44>)
3e4: f000 f818 bl 418 <_init>
3e8: 1ba4 subs r4, r4, r6
3ea: 10a4 asrs r4, r4, #2
3ec: 2500 movs r5, #0
3ee: 42a5 cmp r5, r4
3f0: d105 bne.n 3fe <__libc_init_array+0x2e>
3f2: bd70 pop {r4, r5, r6, pc}
3f4: f856 3025 ldr.w r3, [r6, r5, lsl #2]
3f8: 4798 blx r3
3fa: 3501 adds r5, #1
3fc: e7ee b.n 3dc <__libc_init_array+0xc>
3fe: f856 3025 ldr.w r3, [r6, r5, lsl #2]
402: 4798 blx r3
404: 3501 adds r5, #1
406: e7f2 b.n 3ee <__libc_init_array+0x1e>
408: 00000424 .word 0x00000424
40c: 00000424 .word 0x00000424
410: 00000424 .word 0x00000424
414: 00000428 .word 0x00000428
00000418 <_init>:
418: b5f8 push {r3, r4, r5, r6, r7, lr}
41a: bf00 nop
41c: bcf8 pop {r3, r4, r5, r6, r7}
41e: bc08 pop {r3}
420: 469e mov lr, r3
422: 4770 bx lr
00000424 <__init_array_start>:
424: 00000289 .word 0x00000289
00000428 <_fini>:
428: b5f8 push {r3, r4, r5, r6, r7, lr}
42a: bf00 nop
42c: bcf8 pop {r3, r4, r5, r6, r7}
42e: bc08 pop {r3}
430: 469e mov lr, r3
432: 4770 bx lr
00000434 <__fini_array_start>:
434: 00000265 .word 0x00000265
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