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<div id="projectname">SAME54P20A Test Project
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<div class="header">
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Osc32kctrl Struct Reference</div> </div>
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<div class="contents">
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<p>OSC32KCTRL hardware registers.
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<a href="structOsc32kctrl.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="component_2osc32kctrl_8h_source.html">osc32kctrl.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a2cc865826e2c69780f5fbaf85e851ea1"><td class="memItemLeft" align="right" valign="top"><a id="a2cc865826e2c69780f5fbaf85e851ea1"></a>
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__IO <a class="el" href="unionOSC32KCTRL__INTENCLR__Type.html">OSC32KCTRL_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOsc32kctrl.html#a2cc865826e2c69780f5fbaf85e851ea1">INTENCLR</a></td></tr>
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<tr class="memdesc:a2cc865826e2c69780f5fbaf85e851ea1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 32) Interrupt Enable Clear. <br /></td></tr>
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__IO <a class="el" href="unionOSC32KCTRL__INTENSET__Type.html">OSC32KCTRL_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOsc32kctrl.html#aae1184bb6b2cdaab784b0189726db80a">INTENSET</a></td></tr>
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<tr class="memdesc:aae1184bb6b2cdaab784b0189726db80a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 32) Interrupt Enable Set. <br /></td></tr>
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<tr class="separator:aae1184bb6b2cdaab784b0189726db80a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a15de0aa5c22b436baf5d2fc6a1f5aab6"><td class="memItemLeft" align="right" valign="top"><a id="a15de0aa5c22b436baf5d2fc6a1f5aab6"></a>
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__IO <a class="el" href="unionOSC32KCTRL__INTFLAG__Type.html">OSC32KCTRL_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOsc32kctrl.html#a15de0aa5c22b436baf5d2fc6a1f5aab6">INTFLAG</a></td></tr>
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<tr class="memdesc:a15de0aa5c22b436baf5d2fc6a1f5aab6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear. <br /></td></tr>
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<tr class="separator:a15de0aa5c22b436baf5d2fc6a1f5aab6"><td class="memSeparator" colspan="2"> </td></tr>
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__I <a class="el" href="unionOSC32KCTRL__STATUS__Type.html">OSC32KCTRL_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOsc32kctrl.html#aa6eb5a48bfc45b5127e57bec50d7fb7f">STATUS</a></td></tr>
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<tr class="memdesc:aa6eb5a48bfc45b5127e57bec50d7fb7f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/ 32) Power and Clocks Status. <br /></td></tr>
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<tr class="separator:aa6eb5a48bfc45b5127e57bec50d7fb7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a602070e4ec0aa0925797e3028646717f"><td class="memItemLeft" align="right" valign="top"><a id="a602070e4ec0aa0925797e3028646717f"></a>
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__IO <a class="el" href="unionOSC32KCTRL__RTCCTRL__Type.html">OSC32KCTRL_RTCCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOsc32kctrl.html#a602070e4ec0aa0925797e3028646717f">RTCCTRL</a></td></tr>
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<tr class="memdesc:a602070e4ec0aa0925797e3028646717f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/W 8) RTC Clock Selection. <br /></td></tr>
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<tr class="separator:a602070e4ec0aa0925797e3028646717f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a71752a9d85cf7503207247ed0b23033f"><td class="memItemLeft" align="right" valign="top"><a id="a71752a9d85cf7503207247ed0b23033f"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x3]</td></tr>
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<tr class="separator:a71752a9d85cf7503207247ed0b23033f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc6f2c7fed0114a0843284a4656e8afe"><td class="memItemLeft" align="right" valign="top"><a id="abc6f2c7fed0114a0843284a4656e8afe"></a>
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__IO <a class="el" href="unionOSC32KCTRL__XOSC32K__Type.html">OSC32KCTRL_XOSC32K_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOsc32kctrl.html#abc6f2c7fed0114a0843284a4656e8afe">XOSC32K</a></td></tr>
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<tr class="memdesc:abc6f2c7fed0114a0843284a4656e8afe"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control. <br /></td></tr>
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<tr class="separator:abc6f2c7fed0114a0843284a4656e8afe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae586021076bafc6e93fced5df3606c92"><td class="memItemLeft" align="right" valign="top"><a id="ae586021076bafc6e93fced5df3606c92"></a>
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__IO <a class="el" href="unionOSC32KCTRL__CFDCTRL__Type.html">OSC32KCTRL_CFDCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOsc32kctrl.html#ae586021076bafc6e93fced5df3606c92">CFDCTRL</a></td></tr>
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<tr class="memdesc:ae586021076bafc6e93fced5df3606c92"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x16 (R/W 8) Clock Failure Detector Control. <br /></td></tr>
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<tr class="separator:ae586021076bafc6e93fced5df3606c92"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5866ff04be545ff911a0f068da688c09"><td class="memItemLeft" align="right" valign="top"><a id="a5866ff04be545ff911a0f068da688c09"></a>
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__IO <a class="el" href="unionOSC32KCTRL__EVCTRL__Type.html">OSC32KCTRL_EVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOsc32kctrl.html#a5866ff04be545ff911a0f068da688c09">EVCTRL</a></td></tr>
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<tr class="memdesc:a5866ff04be545ff911a0f068da688c09"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x17 (R/W 8) Event Control. <br /></td></tr>
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<tr class="separator:a5866ff04be545ff911a0f068da688c09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a51eb95ae7d40095bcf31b09103e6a444"><td class="memItemLeft" align="right" valign="top"><a id="a51eb95ae7d40095bcf31b09103e6a444"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x4]</td></tr>
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<tr class="separator:a51eb95ae7d40095bcf31b09103e6a444"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9bc8e06d5efac5d925b97fe81de80415"><td class="memItemLeft" align="right" valign="top"><a id="a9bc8e06d5efac5d925b97fe81de80415"></a>
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__IO <a class="el" href="unionOSC32KCTRL__OSCULP32K__Type.html">OSC32KCTRL_OSCULP32K_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOsc32kctrl.html#a9bc8e06d5efac5d925b97fe81de80415">OSCULP32K</a></td></tr>
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<tr class="memdesc:a9bc8e06d5efac5d925b97fe81de80415"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control. <br /></td></tr>
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<tr class="separator:a9bc8e06d5efac5d925b97fe81de80415"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>OSC32KCTRL hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="component_2osc32kctrl_8h_source.html#l00286">286</a> of file <a class="el" href="component_2osc32kctrl_8h_source.html">osc32kctrl.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2osc32kctrl_8h_source.html">osc32kctrl.h</a></li>
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