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425 lines
11 KiB
C
425 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
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/* exynos_drm.h
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* Authors:
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* Inki Dae <inki.dae@samsung.com>
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* Joonyoung Shim <jy0922.shim@samsung.com>
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* Seung-Woo Kim <sw0312.kim@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _EXYNOS_DRM_H_
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#define _EXYNOS_DRM_H_
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/**
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* User-desired buffer creation information structure.
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*
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* @size: user-desired memory allocation size.
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* - this size value would be page-aligned internally.
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* @flags: user request for setting memory type or cache attributes.
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* @handle: returned a handle to created gem object.
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* - this handle will be set by gem module of kernel side.
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*/
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struct drm_exynos_gem_create {
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__u64 size;
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__u32 flags;
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__u32 handle;
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};
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/**
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* A structure for getting a fake-offset that can be used with mmap.
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*
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* @handle: handle of gem object.
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* @reserved: just padding to be 64-bit aligned.
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* @offset: a fake-offset of gem object.
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*/
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struct drm_exynos_gem_map {
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__u32 handle;
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__u32 reserved;
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__u64 offset;
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};
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/**
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* A structure to gem information.
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*
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* @handle: a handle to gem object created.
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* @flags: flag value including memory type and cache attribute and
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* this value would be set by driver.
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* @size: size to memory region allocated by gem and this size would
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* be set by driver.
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*/
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struct drm_exynos_gem_info {
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__u32 handle;
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__u32 flags;
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__u64 size;
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};
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/**
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* A structure for user connection request of virtual display.
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*
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* @connection: indicate whether doing connetion or not by user.
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* @extensions: if this value is 1 then the vidi driver would need additional
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* 128bytes edid data.
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* @edid: the edid data pointer from user side.
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*/
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struct drm_exynos_vidi_connection {
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__u32 connection;
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__u32 extensions;
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__u64 edid;
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};
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/* memory type definitions. */
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enum e_drm_exynos_gem_mem_type {
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/* Physically Continuous memory and used as default. */
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EXYNOS_BO_CONTIG = 0 << 0,
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/* Physically Non-Continuous memory. */
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EXYNOS_BO_NONCONTIG = 1 << 0,
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/* non-cachable mapping and used as default. */
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EXYNOS_BO_NONCACHABLE = 0 << 1,
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/* cachable mapping. */
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EXYNOS_BO_CACHABLE = 1 << 1,
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/* write-combine mapping. */
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EXYNOS_BO_WC = 1 << 2,
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EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
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EXYNOS_BO_WC
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};
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struct drm_exynos_g2d_get_ver {
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__u32 major;
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__u32 minor;
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};
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struct drm_exynos_g2d_cmd {
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__u32 offset;
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__u32 data;
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};
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enum drm_exynos_g2d_buf_type {
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G2D_BUF_USERPTR = 1 << 31,
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};
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enum drm_exynos_g2d_event_type {
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G2D_EVENT_NOT,
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G2D_EVENT_NONSTOP,
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G2D_EVENT_STOP, /* not yet */
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};
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struct drm_exynos_g2d_userptr {
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unsigned long userptr;
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unsigned long size;
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};
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struct drm_exynos_g2d_set_cmdlist {
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__u64 cmd;
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__u64 cmd_buf;
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__u32 cmd_nr;
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__u32 cmd_buf_nr;
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/* for g2d event */
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__u64 event_type;
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__u64 user_data;
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};
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struct drm_exynos_g2d_exec {
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__u64 async;
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};
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/* Exynos DRM IPP v2 API */
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/**
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* Enumerate available IPP hardware modules.
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*
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* @count_ipps: size of ipp_id array / number of ipp modules (set by driver)
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* @reserved: padding
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* @ipp_id_ptr: pointer to ipp_id array or NULL
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*/
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struct drm_exynos_ioctl_ipp_get_res {
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__u32 count_ipps;
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__u32 reserved;
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__u64 ipp_id_ptr;
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};
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enum drm_exynos_ipp_format_type {
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DRM_EXYNOS_IPP_FORMAT_SOURCE = 0x01,
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DRM_EXYNOS_IPP_FORMAT_DESTINATION = 0x02,
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};
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struct drm_exynos_ipp_format {
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__u32 fourcc;
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__u32 type;
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__u64 modifier;
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};
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enum drm_exynos_ipp_capability {
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DRM_EXYNOS_IPP_CAP_CROP = 0x01,
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DRM_EXYNOS_IPP_CAP_ROTATE = 0x02,
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DRM_EXYNOS_IPP_CAP_SCALE = 0x04,
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DRM_EXYNOS_IPP_CAP_CONVERT = 0x08,
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};
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/**
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* Get IPP hardware capabilities and supported image formats.
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*
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* @ipp_id: id of IPP module to query
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* @capabilities: bitmask of drm_exynos_ipp_capability (set by driver)
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* @reserved: padding
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* @formats_count: size of formats array (in entries) / number of filled
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* formats (set by driver)
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* @formats_ptr: pointer to formats array or NULL
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*/
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struct drm_exynos_ioctl_ipp_get_caps {
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__u32 ipp_id;
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__u32 capabilities;
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__u32 reserved;
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__u32 formats_count;
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__u64 formats_ptr;
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};
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enum drm_exynos_ipp_limit_type {
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/* size (horizontal/vertial) limits, in pixels (min, max, alignment) */
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DRM_EXYNOS_IPP_LIMIT_TYPE_SIZE = 0x0001,
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/* scale ratio (horizonta/vertial), 16.16 fixed point (min, max) */
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DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE = 0x0002,
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/* image buffer area */
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DRM_EXYNOS_IPP_LIMIT_SIZE_BUFFER = 0x0001 << 16,
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/* src/dst rectangle area */
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DRM_EXYNOS_IPP_LIMIT_SIZE_AREA = 0x0002 << 16,
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/* src/dst rectangle area when rotation enabled */
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DRM_EXYNOS_IPP_LIMIT_SIZE_ROTATED = 0x0003 << 16,
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DRM_EXYNOS_IPP_LIMIT_TYPE_MASK = 0x000f,
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DRM_EXYNOS_IPP_LIMIT_SIZE_MASK = 0x000f << 16,
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};
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struct drm_exynos_ipp_limit_val {
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__u32 min;
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__u32 max;
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__u32 align;
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__u32 reserved;
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};
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/**
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* IPP module limitation.
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*
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* @type: limit type (see drm_exynos_ipp_limit_type enum)
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* @reserved: padding
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* @h: horizontal limits
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* @v: vertical limits
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*/
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struct drm_exynos_ipp_limit {
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__u32 type;
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__u32 reserved;
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struct drm_exynos_ipp_limit_val h;
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struct drm_exynos_ipp_limit_val v;
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};
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/**
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* Get IPP limits for given image format.
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*
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* @ipp_id: id of IPP module to query
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* @fourcc: image format code (see DRM_FORMAT_* in drm_fourcc.h)
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* @modifier: image format modifier (see DRM_FORMAT_MOD_* in drm_fourcc.h)
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* @type: source/destination identifier (drm_exynos_ipp_format_flag enum)
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* @limits_count: size of limits array (in entries) / number of filled entries
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* (set by driver)
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* @limits_ptr: pointer to limits array or NULL
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*/
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struct drm_exynos_ioctl_ipp_get_limits {
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__u32 ipp_id;
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__u32 fourcc;
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__u64 modifier;
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__u32 type;
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__u32 limits_count;
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__u64 limits_ptr;
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};
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enum drm_exynos_ipp_task_id {
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/* buffer described by struct drm_exynos_ipp_task_buffer */
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DRM_EXYNOS_IPP_TASK_BUFFER = 0x0001,
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/* rectangle described by struct drm_exynos_ipp_task_rect */
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DRM_EXYNOS_IPP_TASK_RECTANGLE = 0x0002,
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/* transformation described by struct drm_exynos_ipp_task_transform */
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DRM_EXYNOS_IPP_TASK_TRANSFORM = 0x0003,
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/* alpha configuration described by struct drm_exynos_ipp_task_alpha */
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DRM_EXYNOS_IPP_TASK_ALPHA = 0x0004,
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/* source image data (for buffer and rectangle chunks) */
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DRM_EXYNOS_IPP_TASK_TYPE_SOURCE = 0x0001 << 16,
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/* destination image data (for buffer and rectangle chunks) */
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DRM_EXYNOS_IPP_TASK_TYPE_DESTINATION = 0x0002 << 16,
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};
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/**
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* Memory buffer with image data.
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*
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* @id: must be DRM_EXYNOS_IPP_TASK_BUFFER
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* other parameters are same as for AddFB2 generic DRM ioctl
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*/
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struct drm_exynos_ipp_task_buffer {
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__u32 id;
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__u32 fourcc;
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__u32 width, height;
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__u32 gem_id[4];
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__u32 offset[4];
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__u32 pitch[4];
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__u64 modifier;
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};
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/**
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* Rectangle for processing.
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*
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* @id: must be DRM_EXYNOS_IPP_TASK_RECTANGLE
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* @reserved: padding
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* @x,@y: left corner in pixels
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* @w,@h: width/height in pixels
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*/
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struct drm_exynos_ipp_task_rect {
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__u32 id;
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__u32 reserved;
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__u32 x;
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__u32 y;
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__u32 w;
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__u32 h;
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};
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/**
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* Image tranformation description.
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*
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* @id: must be DRM_EXYNOS_IPP_TASK_TRANSFORM
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* @rotation: DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* values
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*/
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struct drm_exynos_ipp_task_transform {
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__u32 id;
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__u32 rotation;
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};
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/**
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* Image global alpha configuration for formats without alpha values.
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*
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* @id: must be DRM_EXYNOS_IPP_TASK_ALPHA
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* @value: global alpha value (0-255)
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*/
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struct drm_exynos_ipp_task_alpha {
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__u32 id;
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__u32 value;
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};
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enum drm_exynos_ipp_flag {
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/* generate DRM event after processing */
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DRM_EXYNOS_IPP_FLAG_EVENT = 0x01,
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/* dry run, only check task parameters */
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DRM_EXYNOS_IPP_FLAG_TEST_ONLY = 0x02,
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/* non-blocking processing */
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DRM_EXYNOS_IPP_FLAG_NONBLOCK = 0x04,
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};
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#define DRM_EXYNOS_IPP_FLAGS (DRM_EXYNOS_IPP_FLAG_EVENT |\
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DRM_EXYNOS_IPP_FLAG_TEST_ONLY | DRM_EXYNOS_IPP_FLAG_NONBLOCK)
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/**
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* Perform image processing described by array of drm_exynos_ipp_task_*
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* structures (parameters array).
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*
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* @ipp_id: id of IPP module to run the task
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* @flags: bitmask of drm_exynos_ipp_flag values
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* @reserved: padding
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* @params_size: size of parameters array (in bytes)
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* @params_ptr: pointer to parameters array or NULL
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* @user_data: (optional) data for drm event
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*/
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struct drm_exynos_ioctl_ipp_commit {
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__u32 ipp_id;
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__u32 flags;
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__u32 reserved;
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__u32 params_size;
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__u64 params_ptr;
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__u64 user_data;
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};
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#define DRM_EXYNOS_GEM_CREATE 0x00
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#define DRM_EXYNOS_GEM_MAP 0x01
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/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
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#define DRM_EXYNOS_GEM_GET 0x04
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#define DRM_EXYNOS_VIDI_CONNECTION 0x07
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/* G2D */
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#define DRM_EXYNOS_G2D_GET_VER 0x20
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#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
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#define DRM_EXYNOS_G2D_EXEC 0x22
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/* Reserved 0x30 ~ 0x33 for obsolete Exynos IPP ioctls */
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/* IPP - Image Post Processing */
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#define DRM_EXYNOS_IPP_GET_RESOURCES 0x40
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#define DRM_EXYNOS_IPP_GET_CAPS 0x41
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#define DRM_EXYNOS_IPP_GET_LIMITS 0x42
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#define DRM_EXYNOS_IPP_COMMIT 0x43
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#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
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#define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map)
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#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
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#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
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#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
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#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
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#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
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#define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_IPP_GET_RESOURCES, \
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struct drm_exynos_ioctl_ipp_get_res)
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#define DRM_IOCTL_EXYNOS_IPP_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_IPP_GET_CAPS, struct drm_exynos_ioctl_ipp_get_caps)
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#define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_IPP_GET_LIMITS, \
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struct drm_exynos_ioctl_ipp_get_limits)
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#define DRM_IOCTL_EXYNOS_IPP_COMMIT DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_IPP_COMMIT, struct drm_exynos_ioctl_ipp_commit)
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/* EXYNOS specific events */
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#define DRM_EXYNOS_G2D_EVENT 0x80000000
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#define DRM_EXYNOS_IPP_EVENT 0x80000002
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struct drm_exynos_g2d_event {
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struct drm_event base;
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__u64 user_data;
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__u32 tv_sec;
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__u32 tv_usec;
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__u32 cmdlist_no;
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__u32 reserved;
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};
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struct drm_exynos_ipp_event {
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struct drm_event base;
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__u64 user_data;
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__u32 tv_sec;
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__u32 tv_usec;
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__u32 ipp_id;
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__u32 sequence;
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__u64 reserved;
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};
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#if defined(__cplusplus)
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}
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#endif
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#endif /* _EXYNOS_DRM_H_ */
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