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<p>Component description for QSPI.
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Data Structures</h2></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__CTRLA__Type.html">QSPI_CTRLA_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__CTRLB__Type.html">QSPI_CTRLB_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__BAUD__Type.html">QSPI_BAUD_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__RXDATA__Type.html">QSPI_RXDATA_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__TXDATA__Type.html">QSPI_TXDATA_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__INTENCLR__Type.html">QSPI_INTENCLR_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__INTENSET__Type.html">QSPI_INTENSET_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__INTFLAG__Type.html">QSPI_INTFLAG_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__STATUS__Type.html">QSPI_STATUS_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__INSTRADDR__Type.html">QSPI_INSTRADDR_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__INSTRCTRL__Type.html">QSPI_INSTRCTRL_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__INSTRFRAME__Type.html">QSPI_INSTRFRAME_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__SCRAMBCTRL__Type.html">QSPI_SCRAMBCTRL_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionQSPI__SCRAMBKEY__Type.html">QSPI_SCRAMBKEY_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html">Qspi</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">QSPI APB hardware registers. <a href="structQspi.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:abe02cda8bf40bd55426907b07d976c87"><td class="memItemLeft" align="right" valign="top"><a id="abe02cda8bf40bd55426907b07d976c87"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_U2008</b></td></tr>
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<tr class="separator:abe02cda8bf40bd55426907b07d976c87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac51089e3ee8dbdc4b76e3293760a4e9a"><td class="memItemLeft" align="right" valign="top"><a id="ac51089e3ee8dbdc4b76e3293760a4e9a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>REV_QSPI</b>   0x163</td></tr>
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<tr class="separator:ac51089e3ee8dbdc4b76e3293760a4e9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3c85ecdbf2e9a83baa5c02c477e2d219"><td class="memItemLeft" align="right" valign="top"><a id="a3c85ecdbf2e9a83baa5c02c477e2d219"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a3c85ecdbf2e9a83baa5c02c477e2d219">QSPI_CTRLA_OFFSET</a>   0x00</td></tr>
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<tr class="memdesc:a3c85ecdbf2e9a83baa5c02c477e2d219"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLA offset) Control A <br /></td></tr>
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<tr class="separator:a3c85ecdbf2e9a83baa5c02c477e2d219"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a07465827fd18264d444500bdb55286ce"><td class="memItemLeft" align="right" valign="top"><a id="a07465827fd18264d444500bdb55286ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a07465827fd18264d444500bdb55286ce">QSPI_CTRLA_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a07465827fd18264d444500bdb55286ce"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLA reset_value) Control A <br /></td></tr>
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<tr class="separator:a07465827fd18264d444500bdb55286ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac61b8c6799b93af4b19eb1cc8c1060ad"><td class="memItemLeft" align="right" valign="top"><a id="ac61b8c6799b93af4b19eb1cc8c1060ad"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ac61b8c6799b93af4b19eb1cc8c1060ad">QSPI_CTRLA_SWRST_Pos</a>   0</td></tr>
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<tr class="memdesc:ac61b8c6799b93af4b19eb1cc8c1060ad"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLA) Software Reset <br /></td></tr>
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<tr class="separator:ac61b8c6799b93af4b19eb1cc8c1060ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5033501689437c08181f809455713c3d"><td class="memItemLeft" align="right" valign="top"><a id="a5033501689437c08181f809455713c3d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLA_SWRST</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#ac61b8c6799b93af4b19eb1cc8c1060ad">QSPI_CTRLA_SWRST_Pos</a>)</td></tr>
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<tr class="separator:a5033501689437c08181f809455713c3d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a102905a5d5179136df4a67e14b6694b1"><td class="memItemLeft" align="right" valign="top"><a id="a102905a5d5179136df4a67e14b6694b1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a102905a5d5179136df4a67e14b6694b1">QSPI_CTRLA_ENABLE_Pos</a>   1</td></tr>
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<tr class="memdesc:a102905a5d5179136df4a67e14b6694b1"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLA) Enable <br /></td></tr>
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<tr class="separator:a102905a5d5179136df4a67e14b6694b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5ec7e0394e3f4ddfce88e8652b0b913d"><td class="memItemLeft" align="right" valign="top"><a id="a5ec7e0394e3f4ddfce88e8652b0b913d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLA_ENABLE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a102905a5d5179136df4a67e14b6694b1">QSPI_CTRLA_ENABLE_Pos</a>)</td></tr>
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<tr class="separator:a5ec7e0394e3f4ddfce88e8652b0b913d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a33e902d88b6c5b91eeacc0019d6ae36f"><td class="memItemLeft" align="right" valign="top"><a id="a33e902d88b6c5b91eeacc0019d6ae36f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a33e902d88b6c5b91eeacc0019d6ae36f">QSPI_CTRLA_LASTXFER_Pos</a>   24</td></tr>
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<tr class="memdesc:a33e902d88b6c5b91eeacc0019d6ae36f"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLA) Last Transfer <br /></td></tr>
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<tr class="separator:a33e902d88b6c5b91eeacc0019d6ae36f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a47714a8ee9e5c88e919549803ac23f8b"><td class="memItemLeft" align="right" valign="top"><a id="a47714a8ee9e5c88e919549803ac23f8b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLA_LASTXFER</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a33e902d88b6c5b91eeacc0019d6ae36f">QSPI_CTRLA_LASTXFER_Pos</a>)</td></tr>
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<tr class="separator:a47714a8ee9e5c88e919549803ac23f8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac433c9f1f4db34c9891f589daf7d3f8b"><td class="memItemLeft" align="right" valign="top"><a id="ac433c9f1f4db34c9891f589daf7d3f8b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ac433c9f1f4db34c9891f589daf7d3f8b">QSPI_CTRLA_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x01000003)</td></tr>
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<tr class="memdesc:ac433c9f1f4db34c9891f589daf7d3f8b"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLA) MASK Register <br /></td></tr>
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<tr class="separator:ac433c9f1f4db34c9891f589daf7d3f8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a86b6ab4b906b5c6aefa6c0ebd5d60224"><td class="memItemLeft" align="right" valign="top"><a id="a86b6ab4b906b5c6aefa6c0ebd5d60224"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a86b6ab4b906b5c6aefa6c0ebd5d60224">QSPI_CTRLB_OFFSET</a>   0x04</td></tr>
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<tr class="memdesc:a86b6ab4b906b5c6aefa6c0ebd5d60224"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB offset) Control B <br /></td></tr>
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<tr class="separator:a86b6ab4b906b5c6aefa6c0ebd5d60224"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5d56bf1cfa14015b777b28f2fa09fb1e"><td class="memItemLeft" align="right" valign="top"><a id="a5d56bf1cfa14015b777b28f2fa09fb1e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a5d56bf1cfa14015b777b28f2fa09fb1e">QSPI_CTRLB_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a5d56bf1cfa14015b777b28f2fa09fb1e"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB reset_value) Control B <br /></td></tr>
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<tr class="separator:a5d56bf1cfa14015b777b28f2fa09fb1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a79698078d30d3cb7fd87b60982a61ad9"><td class="memItemLeft" align="right" valign="top"><a id="a79698078d30d3cb7fd87b60982a61ad9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a79698078d30d3cb7fd87b60982a61ad9">QSPI_CTRLB_MODE_Pos</a>   0</td></tr>
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<tr class="memdesc:a79698078d30d3cb7fd87b60982a61ad9"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) Serial Memory Mode <br /></td></tr>
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<tr class="separator:a79698078d30d3cb7fd87b60982a61ad9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa2c5c8d7be678b795fe742488207555b"><td class="memItemLeft" align="right" valign="top"><a id="aa2c5c8d7be678b795fe742488207555b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_MODE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a79698078d30d3cb7fd87b60982a61ad9">QSPI_CTRLB_MODE_Pos</a>)</td></tr>
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<tr class="separator:aa2c5c8d7be678b795fe742488207555b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a29d105cadb9ae4f52d8cb4ad48e6dceb"><td class="memItemLeft" align="right" valign="top"><a id="a29d105cadb9ae4f52d8cb4ad48e6dceb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a29d105cadb9ae4f52d8cb4ad48e6dceb">QSPI_CTRLB_MODE_SPI_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0)</td></tr>
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<tr class="memdesc:a29d105cadb9ae4f52d8cb4ad48e6dceb"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) SPI operating mode <br /></td></tr>
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<tr class="separator:a29d105cadb9ae4f52d8cb4ad48e6dceb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5c39c83034ab25732435350864217682"><td class="memItemLeft" align="right" valign="top"><a id="a5c39c83034ab25732435350864217682"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a5c39c83034ab25732435350864217682">QSPI_CTRLB_MODE_MEMORY_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1)</td></tr>
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<tr class="memdesc:a5c39c83034ab25732435350864217682"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) Serial Memory operating mode <br /></td></tr>
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<tr class="memitem:ab3d0e6c1b4649808b322875ebe8514c5"><td class="memItemLeft" align="right" valign="top"><a id="ab3d0e6c1b4649808b322875ebe8514c5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_MODE_SPI</b>   (<a class="el" href="component_2qspi_8h.html#a29d105cadb9ae4f52d8cb4ad48e6dceb">QSPI_CTRLB_MODE_SPI_Val</a> << <a class="el" href="component_2qspi_8h.html#a79698078d30d3cb7fd87b60982a61ad9">QSPI_CTRLB_MODE_Pos</a>)</td></tr>
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<tr class="memitem:a75dee24ba695dd9a17317df6dc41fe16"><td class="memItemLeft" align="right" valign="top"><a id="a75dee24ba695dd9a17317df6dc41fe16"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_MODE_MEMORY</b>   (<a class="el" href="component_2qspi_8h.html#a5c39c83034ab25732435350864217682">QSPI_CTRLB_MODE_MEMORY_Val</a> << <a class="el" href="component_2qspi_8h.html#a79698078d30d3cb7fd87b60982a61ad9">QSPI_CTRLB_MODE_Pos</a>)</td></tr>
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<tr class="separator:a75dee24ba695dd9a17317df6dc41fe16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a14f661b36ae775aa061f37807a3aa7d7"><td class="memItemLeft" align="right" valign="top"><a id="a14f661b36ae775aa061f37807a3aa7d7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a14f661b36ae775aa061f37807a3aa7d7">QSPI_CTRLB_LOOPEN_Pos</a>   1</td></tr>
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<tr class="memdesc:a14f661b36ae775aa061f37807a3aa7d7"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) Local Loopback Enable <br /></td></tr>
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<tr class="separator:a14f661b36ae775aa061f37807a3aa7d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afe7d4f3f9d53861fde2e7ef039f20e55"><td class="memItemLeft" align="right" valign="top"><a id="afe7d4f3f9d53861fde2e7ef039f20e55"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_LOOPEN</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a14f661b36ae775aa061f37807a3aa7d7">QSPI_CTRLB_LOOPEN_Pos</a>)</td></tr>
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<tr class="separator:afe7d4f3f9d53861fde2e7ef039f20e55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a45256d78ae287f4e5fcf0a645ba4c539"><td class="memItemLeft" align="right" valign="top"><a id="a45256d78ae287f4e5fcf0a645ba4c539"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a45256d78ae287f4e5fcf0a645ba4c539">QSPI_CTRLB_WDRBT_Pos</a>   2</td></tr>
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<tr class="memdesc:a45256d78ae287f4e5fcf0a645ba4c539"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) Wait Data Read Before Transfer <br /></td></tr>
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<tr class="memitem:aa6bcfeecfd0e773712492e155b4872c9"><td class="memItemLeft" align="right" valign="top"><a id="aa6bcfeecfd0e773712492e155b4872c9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_WDRBT</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a45256d78ae287f4e5fcf0a645ba4c539">QSPI_CTRLB_WDRBT_Pos</a>)</td></tr>
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<tr class="separator:aa6bcfeecfd0e773712492e155b4872c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a15fc44efc7860a14e05bca369ddc4410"><td class="memItemLeft" align="right" valign="top"><a id="a15fc44efc7860a14e05bca369ddc4410"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a15fc44efc7860a14e05bca369ddc4410">QSPI_CTRLB_SMEMREG_Pos</a>   3</td></tr>
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<tr class="memdesc:a15fc44efc7860a14e05bca369ddc4410"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) Serial Memory reg <br /></td></tr>
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<tr class="memitem:a6d9850bbe68eb3c08f1e1435c82508fd"><td class="memItemLeft" align="right" valign="top"><a id="a6d9850bbe68eb3c08f1e1435c82508fd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_SMEMREG</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a15fc44efc7860a14e05bca369ddc4410">QSPI_CTRLB_SMEMREG_Pos</a>)</td></tr>
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<tr class="separator:a6d9850bbe68eb3c08f1e1435c82508fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0f5424f9db41af3e52e84645a0873d39"><td class="memItemLeft" align="right" valign="top"><a id="a0f5424f9db41af3e52e84645a0873d39"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a0f5424f9db41af3e52e84645a0873d39">QSPI_CTRLB_CSMODE_Pos</a>   4</td></tr>
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<tr class="memdesc:a0f5424f9db41af3e52e84645a0873d39"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) Chip Select Mode <br /></td></tr>
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<tr class="separator:a0f5424f9db41af3e52e84645a0873d39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a233175726101f4a5fe885d23b8848113"><td class="memItemLeft" align="right" valign="top"><a id="a233175726101f4a5fe885d23b8848113"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_CSMODE_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3) << <a class="el" href="component_2qspi_8h.html#a0f5424f9db41af3e52e84645a0873d39">QSPI_CTRLB_CSMODE_Pos</a>)</td></tr>
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<tr class="separator:a233175726101f4a5fe885d23b8848113"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4a8c9819bddc63cb4d5aba6b333e0912"><td class="memItemLeft" align="right" valign="top"><a id="a4a8c9819bddc63cb4d5aba6b333e0912"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_CSMODE</b>(value)   (QSPI_CTRLB_CSMODE_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#a0f5424f9db41af3e52e84645a0873d39">QSPI_CTRLB_CSMODE_Pos</a>))</td></tr>
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<tr class="separator:a4a8c9819bddc63cb4d5aba6b333e0912"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad0df34874d30309d93969a5483e3d0e5"><td class="memItemLeft" align="right" valign="top"><a id="ad0df34874d30309d93969a5483e3d0e5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ad0df34874d30309d93969a5483e3d0e5">QSPI_CTRLB_CSMODE_NORELOAD_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0)</td></tr>
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<tr class="memdesc:ad0df34874d30309d93969a5483e3d0e5"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. <br /></td></tr>
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<tr class="separator:ad0df34874d30309d93969a5483e3d0e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aea301858cab20b7bd4623300b017ea5f"><td class="memItemLeft" align="right" valign="top"><a id="aea301858cab20b7bd4623300b017ea5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#aea301858cab20b7bd4623300b017ea5f">QSPI_CTRLB_CSMODE_LASTXFER_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1)</td></tr>
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<tr class="memdesc:aea301858cab20b7bd4623300b017ea5f"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. <br /></td></tr>
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<tr class="separator:aea301858cab20b7bd4623300b017ea5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1396d5436eea5bde0a7ebccb2c0c1e58"><td class="memItemLeft" align="right" valign="top"><a id="a1396d5436eea5bde0a7ebccb2c0c1e58"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a1396d5436eea5bde0a7ebccb2c0c1e58">QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x2)</td></tr>
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<tr class="memdesc:a1396d5436eea5bde0a7ebccb2c0c1e58"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) The chip select is deasserted systematically after each transfer. <br /></td></tr>
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<tr class="memitem:a175f73fa3a3f6c0aaf80cd8395f5b75e"><td class="memItemLeft" align="right" valign="top"><a id="a175f73fa3a3f6c0aaf80cd8395f5b75e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_CSMODE_NORELOAD</b>   (<a class="el" href="component_2qspi_8h.html#ad0df34874d30309d93969a5483e3d0e5">QSPI_CTRLB_CSMODE_NORELOAD_Val</a> << <a class="el" href="component_2qspi_8h.html#a0f5424f9db41af3e52e84645a0873d39">QSPI_CTRLB_CSMODE_Pos</a>)</td></tr>
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<tr class="separator:a175f73fa3a3f6c0aaf80cd8395f5b75e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa776abc8603703060226d9b7fe4640d0"><td class="memItemLeft" align="right" valign="top"><a id="aa776abc8603703060226d9b7fe4640d0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_CSMODE_LASTXFER</b>   (<a class="el" href="component_2qspi_8h.html#aea301858cab20b7bd4623300b017ea5f">QSPI_CTRLB_CSMODE_LASTXFER_Val</a> << <a class="el" href="component_2qspi_8h.html#a0f5424f9db41af3e52e84645a0873d39">QSPI_CTRLB_CSMODE_Pos</a>)</td></tr>
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<tr class="separator:aa776abc8603703060226d9b7fe4640d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0937c4c32bc4bb9b8f68b92a7409c42d"><td class="memItemLeft" align="right" valign="top"><a id="a0937c4c32bc4bb9b8f68b92a7409c42d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_CSMODE_SYSTEMATICALLY</b>   (<a class="el" href="component_2qspi_8h.html#a1396d5436eea5bde0a7ebccb2c0c1e58">QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val</a> << <a class="el" href="component_2qspi_8h.html#a0f5424f9db41af3e52e84645a0873d39">QSPI_CTRLB_CSMODE_Pos</a>)</td></tr>
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<tr class="separator:a0937c4c32bc4bb9b8f68b92a7409c42d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aef938bb6cc8a3c3838d48bc5d6201c6b"><td class="memItemLeft" align="right" valign="top"><a id="aef938bb6cc8a3c3838d48bc5d6201c6b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b">QSPI_CTRLB_DATALEN_Pos</a>   8</td></tr>
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<tr class="memdesc:aef938bb6cc8a3c3838d48bc5d6201c6b"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) Data Length <br /></td></tr>
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<tr class="separator:aef938bb6cc8a3c3838d48bc5d6201c6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:affb2368ca647be901bbb54d2a62369ef"><td class="memItemLeft" align="right" valign="top"><a id="affb2368ca647be901bbb54d2a62369ef"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DATALEN_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b">QSPI_CTRLB_DATALEN_Pos</a>)</td></tr>
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<tr class="separator:affb2368ca647be901bbb54d2a62369ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeb5463f1826387b01e139e7b52b0f65f"><td class="memItemLeft" align="right" valign="top"><a id="aeb5463f1826387b01e139e7b52b0f65f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DATALEN</b>(value)   (QSPI_CTRLB_DATALEN_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b">QSPI_CTRLB_DATALEN_Pos</a>))</td></tr>
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<tr class="separator:aeb5463f1826387b01e139e7b52b0f65f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad539db686ab592cc39c9c59378b18edf"><td class="memItemLeft" align="right" valign="top"><a id="ad539db686ab592cc39c9c59378b18edf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ad539db686ab592cc39c9c59378b18edf">QSPI_CTRLB_DATALEN_8BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0)</td></tr>
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<tr class="memdesc:ad539db686ab592cc39c9c59378b18edf"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) 8-bits transfer <br /></td></tr>
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<tr class="separator:ad539db686ab592cc39c9c59378b18edf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9aa55203ef83894f7cc3d38187b61373"><td class="memItemLeft" align="right" valign="top"><a id="a9aa55203ef83894f7cc3d38187b61373"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a9aa55203ef83894f7cc3d38187b61373">QSPI_CTRLB_DATALEN_9BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1)</td></tr>
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<tr class="memdesc:a9aa55203ef83894f7cc3d38187b61373"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) 9 bits transfer <br /></td></tr>
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<tr class="separator:a9aa55203ef83894f7cc3d38187b61373"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7c65a21275cd48e354f63841fcc0d686"><td class="memItemLeft" align="right" valign="top"><a id="a7c65a21275cd48e354f63841fcc0d686"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a7c65a21275cd48e354f63841fcc0d686">QSPI_CTRLB_DATALEN_10BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x2)</td></tr>
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<tr class="memdesc:a7c65a21275cd48e354f63841fcc0d686"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) 10-bits transfer <br /></td></tr>
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<tr class="separator:a7c65a21275cd48e354f63841fcc0d686"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0cf11534e7b532b44c2b04d8942cb9f5"><td class="memItemLeft" align="right" valign="top"><a id="a0cf11534e7b532b44c2b04d8942cb9f5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a0cf11534e7b532b44c2b04d8942cb9f5">QSPI_CTRLB_DATALEN_11BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3)</td></tr>
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<tr class="memdesc:a0cf11534e7b532b44c2b04d8942cb9f5"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) 11-bits transfer <br /></td></tr>
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<tr class="separator:a0cf11534e7b532b44c2b04d8942cb9f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a485e5774639d6c9aec32a24a3a03bef5"><td class="memItemLeft" align="right" valign="top"><a id="a485e5774639d6c9aec32a24a3a03bef5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a485e5774639d6c9aec32a24a3a03bef5">QSPI_CTRLB_DATALEN_12BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x4)</td></tr>
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<tr class="memdesc:a485e5774639d6c9aec32a24a3a03bef5"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) 12-bits transfer <br /></td></tr>
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<tr class="separator:a485e5774639d6c9aec32a24a3a03bef5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1993041aeb88652286ed5a9110bc9433"><td class="memItemLeft" align="right" valign="top"><a id="a1993041aeb88652286ed5a9110bc9433"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a1993041aeb88652286ed5a9110bc9433">QSPI_CTRLB_DATALEN_13BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x5)</td></tr>
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<tr class="memdesc:a1993041aeb88652286ed5a9110bc9433"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) 13-bits transfer <br /></td></tr>
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<tr class="memitem:a014c5a76b1890913ca8ea610c508f0c3"><td class="memItemLeft" align="right" valign="top"><a id="a014c5a76b1890913ca8ea610c508f0c3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a014c5a76b1890913ca8ea610c508f0c3">QSPI_CTRLB_DATALEN_14BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x6)</td></tr>
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<tr class="memdesc:a014c5a76b1890913ca8ea610c508f0c3"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) 14-bits transfer <br /></td></tr>
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<tr class="memitem:ab8603426bf9532ca41c619ac1780315f"><td class="memItemLeft" align="right" valign="top"><a id="ab8603426bf9532ca41c619ac1780315f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ab8603426bf9532ca41c619ac1780315f">QSPI_CTRLB_DATALEN_15BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x7)</td></tr>
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<tr class="memdesc:ab8603426bf9532ca41c619ac1780315f"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) 15-bits transfer <br /></td></tr>
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<tr class="memitem:afebcc48c02889a870025933a4775cfb7"><td class="memItemLeft" align="right" valign="top"><a id="afebcc48c02889a870025933a4775cfb7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#afebcc48c02889a870025933a4775cfb7">QSPI_CTRLB_DATALEN_16BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x8)</td></tr>
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<tr class="memdesc:afebcc48c02889a870025933a4775cfb7"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) 16-bits transfer <br /></td></tr>
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<tr class="memitem:a61ad797a70ceef8de1ab7acbb5b41290"><td class="memItemLeft" align="right" valign="top"><a id="a61ad797a70ceef8de1ab7acbb5b41290"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DATALEN_8BITS</b>   (<a class="el" href="component_2qspi_8h.html#ad539db686ab592cc39c9c59378b18edf">QSPI_CTRLB_DATALEN_8BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b">QSPI_CTRLB_DATALEN_Pos</a>)</td></tr>
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<tr class="memitem:aa735e42d1dd84d16583f4d1995ce6516"><td class="memItemLeft" align="right" valign="top"><a id="aa735e42d1dd84d16583f4d1995ce6516"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DATALEN_9BITS</b>   (<a class="el" href="component_2qspi_8h.html#a9aa55203ef83894f7cc3d38187b61373">QSPI_CTRLB_DATALEN_9BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b">QSPI_CTRLB_DATALEN_Pos</a>)</td></tr>
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<tr class="memitem:a51681c755bf2b541fd7314e5a2f2e6eb"><td class="memItemLeft" align="right" valign="top"><a id="a51681c755bf2b541fd7314e5a2f2e6eb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DATALEN_10BITS</b>   (<a class="el" href="component_2qspi_8h.html#a7c65a21275cd48e354f63841fcc0d686">QSPI_CTRLB_DATALEN_10BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b">QSPI_CTRLB_DATALEN_Pos</a>)</td></tr>
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<tr class="memitem:ac6da7830234e849955b9538390f80263"><td class="memItemLeft" align="right" valign="top"><a id="ac6da7830234e849955b9538390f80263"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DATALEN_11BITS</b>   (<a class="el" href="component_2qspi_8h.html#a0cf11534e7b532b44c2b04d8942cb9f5">QSPI_CTRLB_DATALEN_11BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b">QSPI_CTRLB_DATALEN_Pos</a>)</td></tr>
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<tr class="memitem:aa1eb61f719e35887b22c9fb401975ced"><td class="memItemLeft" align="right" valign="top"><a id="aa1eb61f719e35887b22c9fb401975ced"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DATALEN_12BITS</b>   (<a class="el" href="component_2qspi_8h.html#a485e5774639d6c9aec32a24a3a03bef5">QSPI_CTRLB_DATALEN_12BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b">QSPI_CTRLB_DATALEN_Pos</a>)</td></tr>
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<tr class="separator:aa1eb61f719e35887b22c9fb401975ced"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f6ab8630279c0f5b902cf339ee5758c"><td class="memItemLeft" align="right" valign="top"><a id="a3f6ab8630279c0f5b902cf339ee5758c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DATALEN_13BITS</b>   (<a class="el" href="component_2qspi_8h.html#a1993041aeb88652286ed5a9110bc9433">QSPI_CTRLB_DATALEN_13BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b">QSPI_CTRLB_DATALEN_Pos</a>)</td></tr>
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<tr class="separator:a3f6ab8630279c0f5b902cf339ee5758c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeb846bf8c9f1071c3017ffcb733d2736"><td class="memItemLeft" align="right" valign="top"><a id="aeb846bf8c9f1071c3017ffcb733d2736"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DATALEN_14BITS</b>   (<a class="el" href="component_2qspi_8h.html#a014c5a76b1890913ca8ea610c508f0c3">QSPI_CTRLB_DATALEN_14BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b">QSPI_CTRLB_DATALEN_Pos</a>)</td></tr>
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<tr class="separator:aeb846bf8c9f1071c3017ffcb733d2736"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a36b03d36c8ce888b9fe22b1aa7114a8b"><td class="memItemLeft" align="right" valign="top"><a id="a36b03d36c8ce888b9fe22b1aa7114a8b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DATALEN_15BITS</b>   (<a class="el" href="component_2qspi_8h.html#ab8603426bf9532ca41c619ac1780315f">QSPI_CTRLB_DATALEN_15BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b">QSPI_CTRLB_DATALEN_Pos</a>)</td></tr>
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<tr class="separator:a36b03d36c8ce888b9fe22b1aa7114a8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a384c0b756ac7b9790c24779fa173106c"><td class="memItemLeft" align="right" valign="top"><a id="a384c0b756ac7b9790c24779fa173106c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DATALEN_16BITS</b>   (<a class="el" href="component_2qspi_8h.html#afebcc48c02889a870025933a4775cfb7">QSPI_CTRLB_DATALEN_16BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b">QSPI_CTRLB_DATALEN_Pos</a>)</td></tr>
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<tr class="separator:a384c0b756ac7b9790c24779fa173106c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a824a62193678245b9bdb100eabc7ae0b"><td class="memItemLeft" align="right" valign="top"><a id="a824a62193678245b9bdb100eabc7ae0b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a824a62193678245b9bdb100eabc7ae0b">QSPI_CTRLB_DLYBCT_Pos</a>   16</td></tr>
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<tr class="memdesc:a824a62193678245b9bdb100eabc7ae0b"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) Delay Between Consecutive Transfers <br /></td></tr>
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<tr class="memitem:af9e4de18fab433d9a210322d8bb3b74c"><td class="memItemLeft" align="right" valign="top"><a id="af9e4de18fab433d9a210322d8bb3b74c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DLYBCT_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFF) << <a class="el" href="component_2qspi_8h.html#a824a62193678245b9bdb100eabc7ae0b">QSPI_CTRLB_DLYBCT_Pos</a>)</td></tr>
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<tr class="separator:af9e4de18fab433d9a210322d8bb3b74c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac9cddc06b0994f789feddecae1a4188f"><td class="memItemLeft" align="right" valign="top"><a id="ac9cddc06b0994f789feddecae1a4188f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DLYBCT</b>(value)   (QSPI_CTRLB_DLYBCT_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#a824a62193678245b9bdb100eabc7ae0b">QSPI_CTRLB_DLYBCT_Pos</a>))</td></tr>
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<tr class="separator:ac9cddc06b0994f789feddecae1a4188f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a85d8473d6936ea535e4af9eb23b519aa"><td class="memItemLeft" align="right" valign="top"><a id="a85d8473d6936ea535e4af9eb23b519aa"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a85d8473d6936ea535e4af9eb23b519aa">QSPI_CTRLB_DLYCS_Pos</a>   24</td></tr>
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<tr class="memdesc:a85d8473d6936ea535e4af9eb23b519aa"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) Minimum Inactive CS Delay <br /></td></tr>
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<tr class="separator:a85d8473d6936ea535e4af9eb23b519aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab06d578b4d6deca19c44fbcf8e53e9e6"><td class="memItemLeft" align="right" valign="top"><a id="ab06d578b4d6deca19c44fbcf8e53e9e6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DLYCS_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFF) << <a class="el" href="component_2qspi_8h.html#a85d8473d6936ea535e4af9eb23b519aa">QSPI_CTRLB_DLYCS_Pos</a>)</td></tr>
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<tr class="separator:ab06d578b4d6deca19c44fbcf8e53e9e6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a93ef765a81450f3dd4e881e4cbac50ad"><td class="memItemLeft" align="right" valign="top"><a id="a93ef765a81450f3dd4e881e4cbac50ad"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_CTRLB_DLYCS</b>(value)   (QSPI_CTRLB_DLYCS_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#a85d8473d6936ea535e4af9eb23b519aa">QSPI_CTRLB_DLYCS_Pos</a>))</td></tr>
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<tr class="separator:a93ef765a81450f3dd4e881e4cbac50ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a81d90a83f5b714371ebd7f2192b5a039"><td class="memItemLeft" align="right" valign="top"><a id="a81d90a83f5b714371ebd7f2192b5a039"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a81d90a83f5b714371ebd7f2192b5a039">QSPI_CTRLB_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFF0F3F)</td></tr>
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<tr class="memdesc:a81d90a83f5b714371ebd7f2192b5a039"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_CTRLB) MASK Register <br /></td></tr>
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<tr class="separator:a81d90a83f5b714371ebd7f2192b5a039"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a91864e8b4413f0c0b3ee02bc1adad69d"><td class="memItemLeft" align="right" valign="top"><a id="a91864e8b4413f0c0b3ee02bc1adad69d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a91864e8b4413f0c0b3ee02bc1adad69d">QSPI_BAUD_OFFSET</a>   0x08</td></tr>
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<tr class="memdesc:a91864e8b4413f0c0b3ee02bc1adad69d"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_BAUD offset) Baud Rate <br /></td></tr>
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<tr class="separator:a91864e8b4413f0c0b3ee02bc1adad69d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3d6ec16e0db1129c9a9ba80cac0a4c9e"><td class="memItemLeft" align="right" valign="top"><a id="a3d6ec16e0db1129c9a9ba80cac0a4c9e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a3d6ec16e0db1129c9a9ba80cac0a4c9e">QSPI_BAUD_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a3d6ec16e0db1129c9a9ba80cac0a4c9e"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_BAUD reset_value) Baud Rate <br /></td></tr>
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<tr class="separator:a3d6ec16e0db1129c9a9ba80cac0a4c9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4ad7ad10245db652c86b15531aa8b17d"><td class="memItemLeft" align="right" valign="top"><a id="a4ad7ad10245db652c86b15531aa8b17d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a4ad7ad10245db652c86b15531aa8b17d">QSPI_BAUD_CPOL_Pos</a>   0</td></tr>
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<tr class="memdesc:a4ad7ad10245db652c86b15531aa8b17d"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_BAUD) Clock Polarity <br /></td></tr>
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<tr class="separator:a4ad7ad10245db652c86b15531aa8b17d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a261f77f7c35b3b11d2a19ff9c96e9205"><td class="memItemLeft" align="right" valign="top"><a id="a261f77f7c35b3b11d2a19ff9c96e9205"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_BAUD_CPOL</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a4ad7ad10245db652c86b15531aa8b17d">QSPI_BAUD_CPOL_Pos</a>)</td></tr>
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<tr class="separator:a261f77f7c35b3b11d2a19ff9c96e9205"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a84d3cf60569cc949d27b2087ccac6760"><td class="memItemLeft" align="right" valign="top"><a id="a84d3cf60569cc949d27b2087ccac6760"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a84d3cf60569cc949d27b2087ccac6760">QSPI_BAUD_CPHA_Pos</a>   1</td></tr>
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<tr class="memdesc:a84d3cf60569cc949d27b2087ccac6760"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_BAUD) Clock Phase <br /></td></tr>
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<tr class="separator:a84d3cf60569cc949d27b2087ccac6760"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae745548290644c2eb946534fe00ad803"><td class="memItemLeft" align="right" valign="top"><a id="ae745548290644c2eb946534fe00ad803"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_BAUD_CPHA</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a84d3cf60569cc949d27b2087ccac6760">QSPI_BAUD_CPHA_Pos</a>)</td></tr>
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<tr class="separator:ae745548290644c2eb946534fe00ad803"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a58218959c2dabde357d38efcc1b83d76"><td class="memItemLeft" align="right" valign="top"><a id="a58218959c2dabde357d38efcc1b83d76"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a58218959c2dabde357d38efcc1b83d76">QSPI_BAUD_BAUD_Pos</a>   8</td></tr>
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<tr class="memdesc:a58218959c2dabde357d38efcc1b83d76"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_BAUD) Serial Clock Baud Rate <br /></td></tr>
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<tr class="memitem:a0fc78359e452869e4f8b430098300d10"><td class="memItemLeft" align="right" valign="top"><a id="a0fc78359e452869e4f8b430098300d10"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_BAUD_BAUD_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFF) << <a class="el" href="component_2qspi_8h.html#a58218959c2dabde357d38efcc1b83d76">QSPI_BAUD_BAUD_Pos</a>)</td></tr>
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<tr class="separator:a0fc78359e452869e4f8b430098300d10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a99495be2db141ca15b386785734b6481"><td class="memItemLeft" align="right" valign="top"><a id="a99495be2db141ca15b386785734b6481"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_BAUD_BAUD</b>(value)   (QSPI_BAUD_BAUD_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#a58218959c2dabde357d38efcc1b83d76">QSPI_BAUD_BAUD_Pos</a>))</td></tr>
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<tr class="memitem:a3e441fa461541cedde2d9cebff18806f"><td class="memItemLeft" align="right" valign="top"><a id="a3e441fa461541cedde2d9cebff18806f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a3e441fa461541cedde2d9cebff18806f">QSPI_BAUD_DLYBS_Pos</a>   16</td></tr>
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<tr class="memdesc:a3e441fa461541cedde2d9cebff18806f"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_BAUD) Delay Before SCK <br /></td></tr>
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<tr class="memitem:a1bbcc1e6bc153faab4169b91afad6fdb"><td class="memItemLeft" align="right" valign="top"><a id="a1bbcc1e6bc153faab4169b91afad6fdb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_BAUD_DLYBS_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFF) << <a class="el" href="component_2qspi_8h.html#a3e441fa461541cedde2d9cebff18806f">QSPI_BAUD_DLYBS_Pos</a>)</td></tr>
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<tr class="separator:a1bbcc1e6bc153faab4169b91afad6fdb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4ff96b914b166ce527a4ac3380bbc905"><td class="memItemLeft" align="right" valign="top"><a id="a4ff96b914b166ce527a4ac3380bbc905"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_BAUD_DLYBS</b>(value)   (QSPI_BAUD_DLYBS_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#a3e441fa461541cedde2d9cebff18806f">QSPI_BAUD_DLYBS_Pos</a>))</td></tr>
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<tr class="memitem:ad1b5f1c147c5c49bdb3ee765aa452ff4"><td class="memItemLeft" align="right" valign="top"><a id="ad1b5f1c147c5c49bdb3ee765aa452ff4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ad1b5f1c147c5c49bdb3ee765aa452ff4">QSPI_BAUD_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00FFFF03)</td></tr>
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<tr class="memdesc:ad1b5f1c147c5c49bdb3ee765aa452ff4"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_BAUD) MASK Register <br /></td></tr>
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<tr class="separator:ad1b5f1c147c5c49bdb3ee765aa452ff4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a87be3956bd37543321c112cbb877e782"><td class="memItemLeft" align="right" valign="top"><a id="a87be3956bd37543321c112cbb877e782"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a87be3956bd37543321c112cbb877e782">QSPI_RXDATA_OFFSET</a>   0x0C</td></tr>
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<tr class="memdesc:a87be3956bd37543321c112cbb877e782"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_RXDATA offset) Receive Data <br /></td></tr>
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<tr class="separator:a87be3956bd37543321c112cbb877e782"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9cd293dea7e9832403612f95104ed613"><td class="memItemLeft" align="right" valign="top"><a id="a9cd293dea7e9832403612f95104ed613"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a9cd293dea7e9832403612f95104ed613">QSPI_RXDATA_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a9cd293dea7e9832403612f95104ed613"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_RXDATA reset_value) Receive Data <br /></td></tr>
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<tr class="memitem:ad47fc7a9b32733011d0cbbf53b974aeb"><td class="memItemLeft" align="right" valign="top"><a id="ad47fc7a9b32733011d0cbbf53b974aeb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ad47fc7a9b32733011d0cbbf53b974aeb">QSPI_RXDATA_DATA_Pos</a>   0</td></tr>
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<tr class="memdesc:ad47fc7a9b32733011d0cbbf53b974aeb"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_RXDATA) Receive Data <br /></td></tr>
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<tr class="memitem:a94901ed068d0cf4e40efb719f4beff8d"><td class="memItemLeft" align="right" valign="top"><a id="a94901ed068d0cf4e40efb719f4beff8d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_RXDATA_DATA_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFF) << <a class="el" href="component_2qspi_8h.html#ad47fc7a9b32733011d0cbbf53b974aeb">QSPI_RXDATA_DATA_Pos</a>)</td></tr>
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<tr class="memitem:a1efac4503457d87c25cfb18ea248c488"><td class="memItemLeft" align="right" valign="top"><a id="a1efac4503457d87c25cfb18ea248c488"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_RXDATA_DATA</b>(value)   (QSPI_RXDATA_DATA_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#ad47fc7a9b32733011d0cbbf53b974aeb">QSPI_RXDATA_DATA_Pos</a>))</td></tr>
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<tr class="separator:a1efac4503457d87c25cfb18ea248c488"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3fd4ee385b606854e969ddc1e60ad209"><td class="memItemLeft" align="right" valign="top"><a id="a3fd4ee385b606854e969ddc1e60ad209"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a3fd4ee385b606854e969ddc1e60ad209">QSPI_RXDATA_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0000FFFF)</td></tr>
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<tr class="memdesc:a3fd4ee385b606854e969ddc1e60ad209"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_RXDATA) MASK Register <br /></td></tr>
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<tr class="memitem:a0ca429506a8e6b03fb928b3a26c20bfc"><td class="memItemLeft" align="right" valign="top"><a id="a0ca429506a8e6b03fb928b3a26c20bfc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a0ca429506a8e6b03fb928b3a26c20bfc">QSPI_TXDATA_OFFSET</a>   0x10</td></tr>
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<tr class="memdesc:a0ca429506a8e6b03fb928b3a26c20bfc"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_TXDATA offset) Transmit Data <br /></td></tr>
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<tr class="separator:a0ca429506a8e6b03fb928b3a26c20bfc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3477e070bac8c154a985baae65233b38"><td class="memItemLeft" align="right" valign="top"><a id="a3477e070bac8c154a985baae65233b38"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a3477e070bac8c154a985baae65233b38">QSPI_TXDATA_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a3477e070bac8c154a985baae65233b38"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_TXDATA reset_value) Transmit Data <br /></td></tr>
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<tr class="separator:a3477e070bac8c154a985baae65233b38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aebe5e7d967560044c44c7c65b4420e69"><td class="memItemLeft" align="right" valign="top"><a id="aebe5e7d967560044c44c7c65b4420e69"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#aebe5e7d967560044c44c7c65b4420e69">QSPI_TXDATA_DATA_Pos</a>   0</td></tr>
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<tr class="memdesc:aebe5e7d967560044c44c7c65b4420e69"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_TXDATA) Transmit Data <br /></td></tr>
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<tr class="separator:aebe5e7d967560044c44c7c65b4420e69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4f2a0922ce22a07cfc4322a95dc08a38"><td class="memItemLeft" align="right" valign="top"><a id="a4f2a0922ce22a07cfc4322a95dc08a38"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_TXDATA_DATA_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFF) << <a class="el" href="component_2qspi_8h.html#aebe5e7d967560044c44c7c65b4420e69">QSPI_TXDATA_DATA_Pos</a>)</td></tr>
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<tr class="separator:a4f2a0922ce22a07cfc4322a95dc08a38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2b6fabf4b6ba29ed0a2c4e47e058d368"><td class="memItemLeft" align="right" valign="top"><a id="a2b6fabf4b6ba29ed0a2c4e47e058d368"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_TXDATA_DATA</b>(value)   (QSPI_TXDATA_DATA_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#aebe5e7d967560044c44c7c65b4420e69">QSPI_TXDATA_DATA_Pos</a>))</td></tr>
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<tr class="separator:a2b6fabf4b6ba29ed0a2c4e47e058d368"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1da1b467d64f72334eb2797919ceec36"><td class="memItemLeft" align="right" valign="top"><a id="a1da1b467d64f72334eb2797919ceec36"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a1da1b467d64f72334eb2797919ceec36">QSPI_TXDATA_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0000FFFF)</td></tr>
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<tr class="memdesc:a1da1b467d64f72334eb2797919ceec36"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_TXDATA) MASK Register <br /></td></tr>
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<tr class="separator:a1da1b467d64f72334eb2797919ceec36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4321f52defba88894f82de95c788061c"><td class="memItemLeft" align="right" valign="top"><a id="a4321f52defba88894f82de95c788061c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a4321f52defba88894f82de95c788061c">QSPI_INTENCLR_OFFSET</a>   0x14</td></tr>
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<tr class="memdesc:a4321f52defba88894f82de95c788061c"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENCLR offset) Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a4321f52defba88894f82de95c788061c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab73ffd7857c52aaaaf917fa1d84d0328"><td class="memItemLeft" align="right" valign="top"><a id="ab73ffd7857c52aaaaf917fa1d84d0328"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ab73ffd7857c52aaaaf917fa1d84d0328">QSPI_INTENCLR_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:ab73ffd7857c52aaaaf917fa1d84d0328"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENCLR reset_value) Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:ab73ffd7857c52aaaaf917fa1d84d0328"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5b9805de8712962cc9135be72b0b5d71"><td class="memItemLeft" align="right" valign="top"><a id="a5b9805de8712962cc9135be72b0b5d71"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a5b9805de8712962cc9135be72b0b5d71">QSPI_INTENCLR_RXC_Pos</a>   0</td></tr>
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<tr class="memdesc:a5b9805de8712962cc9135be72b0b5d71"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENCLR) Receive Data Register Full Interrupt Disable <br /></td></tr>
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<tr class="separator:a5b9805de8712962cc9135be72b0b5d71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9a9d6395d2a29a881d2a028d7b8ce1d4"><td class="memItemLeft" align="right" valign="top"><a id="a9a9d6395d2a29a881d2a028d7b8ce1d4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTENCLR_RXC</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a5b9805de8712962cc9135be72b0b5d71">QSPI_INTENCLR_RXC_Pos</a>)</td></tr>
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<tr class="separator:a9a9d6395d2a29a881d2a028d7b8ce1d4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac563a4fd687c21fa4afae3ef903fe85b"><td class="memItemLeft" align="right" valign="top"><a id="ac563a4fd687c21fa4afae3ef903fe85b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ac563a4fd687c21fa4afae3ef903fe85b">QSPI_INTENCLR_DRE_Pos</a>   1</td></tr>
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<tr class="memdesc:ac563a4fd687c21fa4afae3ef903fe85b"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable <br /></td></tr>
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<tr class="separator:ac563a4fd687c21fa4afae3ef903fe85b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a44eef3d58814f8f2248d2582188a6404"><td class="memItemLeft" align="right" valign="top"><a id="a44eef3d58814f8f2248d2582188a6404"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTENCLR_DRE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#ac563a4fd687c21fa4afae3ef903fe85b">QSPI_INTENCLR_DRE_Pos</a>)</td></tr>
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<tr class="separator:a44eef3d58814f8f2248d2582188a6404"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae24c24d43074574f48a3b4d3286ff8cd"><td class="memItemLeft" align="right" valign="top"><a id="ae24c24d43074574f48a3b4d3286ff8cd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ae24c24d43074574f48a3b4d3286ff8cd">QSPI_INTENCLR_TXC_Pos</a>   2</td></tr>
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<tr class="memdesc:ae24c24d43074574f48a3b4d3286ff8cd"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENCLR) Transmission Complete Interrupt Disable <br /></td></tr>
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<tr class="separator:ae24c24d43074574f48a3b4d3286ff8cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a94384a15f8cec516ce4ef8ff73083c4e"><td class="memItemLeft" align="right" valign="top"><a id="a94384a15f8cec516ce4ef8ff73083c4e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTENCLR_TXC</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#ae24c24d43074574f48a3b4d3286ff8cd">QSPI_INTENCLR_TXC_Pos</a>)</td></tr>
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<tr class="separator:a94384a15f8cec516ce4ef8ff73083c4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1d86a274a38b2658da8dfbc529929172"><td class="memItemLeft" align="right" valign="top"><a id="a1d86a274a38b2658da8dfbc529929172"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a1d86a274a38b2658da8dfbc529929172">QSPI_INTENCLR_ERROR_Pos</a>   3</td></tr>
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<tr class="memdesc:a1d86a274a38b2658da8dfbc529929172"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENCLR) Overrun Error Interrupt Disable <br /></td></tr>
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<tr class="separator:a1d86a274a38b2658da8dfbc529929172"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a35d77d0438760acb12bc2e22126325ad"><td class="memItemLeft" align="right" valign="top"><a id="a35d77d0438760acb12bc2e22126325ad"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTENCLR_ERROR</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a1d86a274a38b2658da8dfbc529929172">QSPI_INTENCLR_ERROR_Pos</a>)</td></tr>
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<tr class="separator:a35d77d0438760acb12bc2e22126325ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aba20d5848fc2b9b010b84e2c28c6ca81"><td class="memItemLeft" align="right" valign="top"><a id="aba20d5848fc2b9b010b84e2c28c6ca81"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#aba20d5848fc2b9b010b84e2c28c6ca81">QSPI_INTENCLR_CSRISE_Pos</a>   8</td></tr>
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<tr class="memdesc:aba20d5848fc2b9b010b84e2c28c6ca81"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENCLR) Chip Select Rise Interrupt Disable <br /></td></tr>
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<tr class="separator:aba20d5848fc2b9b010b84e2c28c6ca81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3678807fa5957eacccfcc3b624511aa3"><td class="memItemLeft" align="right" valign="top"><a id="a3678807fa5957eacccfcc3b624511aa3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTENCLR_CSRISE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#aba20d5848fc2b9b010b84e2c28c6ca81">QSPI_INTENCLR_CSRISE_Pos</a>)</td></tr>
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<tr class="memitem:a89c51cbaa84c36e63aab68f6ff9c7e8c"><td class="memItemLeft" align="right" valign="top"><a id="a89c51cbaa84c36e63aab68f6ff9c7e8c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a89c51cbaa84c36e63aab68f6ff9c7e8c">QSPI_INTENCLR_INSTREND_Pos</a>   10</td></tr>
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<tr class="memdesc:a89c51cbaa84c36e63aab68f6ff9c7e8c"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENCLR) Instruction End Interrupt Disable <br /></td></tr>
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<tr class="separator:a89c51cbaa84c36e63aab68f6ff9c7e8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af7bd75d4a2926fb436b24949b04f76a2"><td class="memItemLeft" align="right" valign="top"><a id="af7bd75d4a2926fb436b24949b04f76a2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTENCLR_INSTREND</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a89c51cbaa84c36e63aab68f6ff9c7e8c">QSPI_INTENCLR_INSTREND_Pos</a>)</td></tr>
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<tr class="separator:af7bd75d4a2926fb436b24949b04f76a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a22f05d7b924c11eb3ff9aa1539a70e4e"><td class="memItemLeft" align="right" valign="top"><a id="a22f05d7b924c11eb3ff9aa1539a70e4e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a22f05d7b924c11eb3ff9aa1539a70e4e">QSPI_INTENCLR_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0000050F)</td></tr>
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<tr class="memdesc:a22f05d7b924c11eb3ff9aa1539a70e4e"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENCLR) MASK Register <br /></td></tr>
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<tr class="separator:a22f05d7b924c11eb3ff9aa1539a70e4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2a63dd66c5cb383bb8084b64937c3558"><td class="memItemLeft" align="right" valign="top"><a id="a2a63dd66c5cb383bb8084b64937c3558"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a2a63dd66c5cb383bb8084b64937c3558">QSPI_INTENSET_OFFSET</a>   0x18</td></tr>
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<tr class="memdesc:a2a63dd66c5cb383bb8084b64937c3558"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENSET offset) Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a2a63dd66c5cb383bb8084b64937c3558"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a408d2403d145db488089cbfbb0943b2c"><td class="memItemLeft" align="right" valign="top"><a id="a408d2403d145db488089cbfbb0943b2c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a408d2403d145db488089cbfbb0943b2c">QSPI_INTENSET_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a408d2403d145db488089cbfbb0943b2c"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENSET reset_value) Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a408d2403d145db488089cbfbb0943b2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a651a6fd970141862c48f631cbe357722"><td class="memItemLeft" align="right" valign="top"><a id="a651a6fd970141862c48f631cbe357722"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a651a6fd970141862c48f631cbe357722">QSPI_INTENSET_RXC_Pos</a>   0</td></tr>
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<tr class="memdesc:a651a6fd970141862c48f631cbe357722"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENSET) Receive Data Register Full Interrupt Enable <br /></td></tr>
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<tr class="separator:a651a6fd970141862c48f631cbe357722"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac6e2c7cb02886227da41ee1a0f80402d"><td class="memItemLeft" align="right" valign="top"><a id="ac6e2c7cb02886227da41ee1a0f80402d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTENSET_RXC</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a651a6fd970141862c48f631cbe357722">QSPI_INTENSET_RXC_Pos</a>)</td></tr>
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<tr class="separator:ac6e2c7cb02886227da41ee1a0f80402d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1ee4feba51c2d52059d91c847816c461"><td class="memItemLeft" align="right" valign="top"><a id="a1ee4feba51c2d52059d91c847816c461"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a1ee4feba51c2d52059d91c847816c461">QSPI_INTENSET_DRE_Pos</a>   1</td></tr>
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<tr class="memdesc:a1ee4feba51c2d52059d91c847816c461"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable <br /></td></tr>
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<tr class="separator:a1ee4feba51c2d52059d91c847816c461"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaeef6590f4fd5e7cc053cf4d7cd13cd6"><td class="memItemLeft" align="right" valign="top"><a id="aaeef6590f4fd5e7cc053cf4d7cd13cd6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTENSET_DRE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a1ee4feba51c2d52059d91c847816c461">QSPI_INTENSET_DRE_Pos</a>)</td></tr>
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<tr class="separator:aaeef6590f4fd5e7cc053cf4d7cd13cd6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa632d7c75c0c176136f760243fc92ecc"><td class="memItemLeft" align="right" valign="top"><a id="aa632d7c75c0c176136f760243fc92ecc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#aa632d7c75c0c176136f760243fc92ecc">QSPI_INTENSET_TXC_Pos</a>   2</td></tr>
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<tr class="memdesc:aa632d7c75c0c176136f760243fc92ecc"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENSET) Transmission Complete Interrupt Enable <br /></td></tr>
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<tr class="separator:aa632d7c75c0c176136f760243fc92ecc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab5f8cbb154bcb5ee250d922973f13b37"><td class="memItemLeft" align="right" valign="top"><a id="ab5f8cbb154bcb5ee250d922973f13b37"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTENSET_TXC</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#aa632d7c75c0c176136f760243fc92ecc">QSPI_INTENSET_TXC_Pos</a>)</td></tr>
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<tr class="separator:ab5f8cbb154bcb5ee250d922973f13b37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae56879a2c995c8759c94236e6b225fbd"><td class="memItemLeft" align="right" valign="top"><a id="ae56879a2c995c8759c94236e6b225fbd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ae56879a2c995c8759c94236e6b225fbd">QSPI_INTENSET_ERROR_Pos</a>   3</td></tr>
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<tr class="memdesc:ae56879a2c995c8759c94236e6b225fbd"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENSET) Overrun Error Interrupt Enable <br /></td></tr>
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<tr class="separator:ae56879a2c995c8759c94236e6b225fbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8848e7d0f33c9e7f3cb05cdd73710428"><td class="memItemLeft" align="right" valign="top"><a id="a8848e7d0f33c9e7f3cb05cdd73710428"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTENSET_ERROR</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#ae56879a2c995c8759c94236e6b225fbd">QSPI_INTENSET_ERROR_Pos</a>)</td></tr>
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<tr class="separator:a8848e7d0f33c9e7f3cb05cdd73710428"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7a39ce2779333876efea464eb8abd6a6"><td class="memItemLeft" align="right" valign="top"><a id="a7a39ce2779333876efea464eb8abd6a6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a7a39ce2779333876efea464eb8abd6a6">QSPI_INTENSET_CSRISE_Pos</a>   8</td></tr>
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<tr class="memdesc:a7a39ce2779333876efea464eb8abd6a6"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENSET) Chip Select Rise Interrupt Enable <br /></td></tr>
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<tr class="separator:a7a39ce2779333876efea464eb8abd6a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af9b32a567b6af3b9b7cd7b615c229ab9"><td class="memItemLeft" align="right" valign="top"><a id="af9b32a567b6af3b9b7cd7b615c229ab9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTENSET_CSRISE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a7a39ce2779333876efea464eb8abd6a6">QSPI_INTENSET_CSRISE_Pos</a>)</td></tr>
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<tr class="separator:af9b32a567b6af3b9b7cd7b615c229ab9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a28af271389d49bba36a16e773053afbc"><td class="memItemLeft" align="right" valign="top"><a id="a28af271389d49bba36a16e773053afbc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a28af271389d49bba36a16e773053afbc">QSPI_INTENSET_INSTREND_Pos</a>   10</td></tr>
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<tr class="memdesc:a28af271389d49bba36a16e773053afbc"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENSET) Instruction End Interrupt Enable <br /></td></tr>
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<tr class="separator:a28af271389d49bba36a16e773053afbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeee7c33192423c84c1f78c1be0f336c7"><td class="memItemLeft" align="right" valign="top"><a id="aeee7c33192423c84c1f78c1be0f336c7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTENSET_INSTREND</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a28af271389d49bba36a16e773053afbc">QSPI_INTENSET_INSTREND_Pos</a>)</td></tr>
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<tr class="separator:aeee7c33192423c84c1f78c1be0f336c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a363a82e8a3a1262e9894d537d3269a80"><td class="memItemLeft" align="right" valign="top"><a id="a363a82e8a3a1262e9894d537d3269a80"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a363a82e8a3a1262e9894d537d3269a80">QSPI_INTENSET_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0000050F)</td></tr>
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<tr class="memdesc:a363a82e8a3a1262e9894d537d3269a80"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTENSET) MASK Register <br /></td></tr>
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<tr class="separator:a363a82e8a3a1262e9894d537d3269a80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0295b33774924d3c333739f5f9b205ff"><td class="memItemLeft" align="right" valign="top"><a id="a0295b33774924d3c333739f5f9b205ff"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a0295b33774924d3c333739f5f9b205ff">QSPI_INTFLAG_OFFSET</a>   0x1C</td></tr>
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<tr class="memdesc:a0295b33774924d3c333739f5f9b205ff"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTFLAG offset) Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:a0295b33774924d3c333739f5f9b205ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a405437e73598fcb9f2465bac8aeef3fe"><td class="memItemLeft" align="right" valign="top"><a id="a405437e73598fcb9f2465bac8aeef3fe"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a405437e73598fcb9f2465bac8aeef3fe">QSPI_INTFLAG_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a405437e73598fcb9f2465bac8aeef3fe"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTFLAG reset_value) Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:a405437e73598fcb9f2465bac8aeef3fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a98f549e10ec9cf4e071155feaa20b73d"><td class="memItemLeft" align="right" valign="top"><a id="a98f549e10ec9cf4e071155feaa20b73d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a98f549e10ec9cf4e071155feaa20b73d">QSPI_INTFLAG_RXC_Pos</a>   0</td></tr>
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<tr class="memdesc:a98f549e10ec9cf4e071155feaa20b73d"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTFLAG) Receive Data Register Full <br /></td></tr>
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<tr class="separator:a98f549e10ec9cf4e071155feaa20b73d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5ab795066cf8f7a99466f9b2f71743f8"><td class="memItemLeft" align="right" valign="top"><a id="a5ab795066cf8f7a99466f9b2f71743f8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTFLAG_RXC</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a98f549e10ec9cf4e071155feaa20b73d">QSPI_INTFLAG_RXC_Pos</a>)</td></tr>
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<tr class="separator:a5ab795066cf8f7a99466f9b2f71743f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7a4cdfdde32baa8545e768a00980777f"><td class="memItemLeft" align="right" valign="top"><a id="a7a4cdfdde32baa8545e768a00980777f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a7a4cdfdde32baa8545e768a00980777f">QSPI_INTFLAG_DRE_Pos</a>   1</td></tr>
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<tr class="memdesc:a7a4cdfdde32baa8545e768a00980777f"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTFLAG) Transmit Data Register Empty <br /></td></tr>
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<tr class="separator:a7a4cdfdde32baa8545e768a00980777f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9f7d60d1f8fc77a5ca2394d1cfd15e7e"><td class="memItemLeft" align="right" valign="top"><a id="a9f7d60d1f8fc77a5ca2394d1cfd15e7e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTFLAG_DRE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a7a4cdfdde32baa8545e768a00980777f">QSPI_INTFLAG_DRE_Pos</a>)</td></tr>
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<tr class="separator:a9f7d60d1f8fc77a5ca2394d1cfd15e7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aae8ba2dd8ab5ade39b7d2ea19f3ac535"><td class="memItemLeft" align="right" valign="top"><a id="aae8ba2dd8ab5ade39b7d2ea19f3ac535"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#aae8ba2dd8ab5ade39b7d2ea19f3ac535">QSPI_INTFLAG_TXC_Pos</a>   2</td></tr>
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<tr class="memdesc:aae8ba2dd8ab5ade39b7d2ea19f3ac535"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTFLAG) Transmission Complete <br /></td></tr>
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<tr class="separator:aae8ba2dd8ab5ade39b7d2ea19f3ac535"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aafa31d1c20c8587ee97cc7414107d139"><td class="memItemLeft" align="right" valign="top"><a id="aafa31d1c20c8587ee97cc7414107d139"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTFLAG_TXC</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#aae8ba2dd8ab5ade39b7d2ea19f3ac535">QSPI_INTFLAG_TXC_Pos</a>)</td></tr>
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<tr class="separator:aafa31d1c20c8587ee97cc7414107d139"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6f575f7d2c7bb689dc601da3aa22350c"><td class="memItemLeft" align="right" valign="top"><a id="a6f575f7d2c7bb689dc601da3aa22350c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a6f575f7d2c7bb689dc601da3aa22350c">QSPI_INTFLAG_ERROR_Pos</a>   3</td></tr>
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<tr class="memdesc:a6f575f7d2c7bb689dc601da3aa22350c"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTFLAG) Overrun Error <br /></td></tr>
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<tr class="separator:a6f575f7d2c7bb689dc601da3aa22350c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3735b7c25b40088c31dabe9df71d5253"><td class="memItemLeft" align="right" valign="top"><a id="a3735b7c25b40088c31dabe9df71d5253"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTFLAG_ERROR</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a6f575f7d2c7bb689dc601da3aa22350c">QSPI_INTFLAG_ERROR_Pos</a>)</td></tr>
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<tr class="separator:a3735b7c25b40088c31dabe9df71d5253"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8adf0a69720752ce53f38530e723d4f8"><td class="memItemLeft" align="right" valign="top"><a id="a8adf0a69720752ce53f38530e723d4f8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a8adf0a69720752ce53f38530e723d4f8">QSPI_INTFLAG_CSRISE_Pos</a>   8</td></tr>
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<tr class="memdesc:a8adf0a69720752ce53f38530e723d4f8"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTFLAG) Chip Select Rise <br /></td></tr>
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<tr class="separator:a8adf0a69720752ce53f38530e723d4f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0b223dd2bc1f3532743fcee1a1657146"><td class="memItemLeft" align="right" valign="top"><a id="a0b223dd2bc1f3532743fcee1a1657146"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTFLAG_CSRISE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a8adf0a69720752ce53f38530e723d4f8">QSPI_INTFLAG_CSRISE_Pos</a>)</td></tr>
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<tr class="separator:a0b223dd2bc1f3532743fcee1a1657146"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2630fdda56c7f0cd4c6a96c68963d933"><td class="memItemLeft" align="right" valign="top"><a id="a2630fdda56c7f0cd4c6a96c68963d933"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a2630fdda56c7f0cd4c6a96c68963d933">QSPI_INTFLAG_INSTREND_Pos</a>   10</td></tr>
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<tr class="memdesc:a2630fdda56c7f0cd4c6a96c68963d933"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTFLAG) Instruction End <br /></td></tr>
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<tr class="memitem:a1535b3fb91a02d03c098ea1e652e1150"><td class="memItemLeft" align="right" valign="top"><a id="a1535b3fb91a02d03c098ea1e652e1150"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INTFLAG_INSTREND</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a2630fdda56c7f0cd4c6a96c68963d933">QSPI_INTFLAG_INSTREND_Pos</a>)</td></tr>
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<tr class="separator:a1535b3fb91a02d03c098ea1e652e1150"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae24f836c5679c8d2b3ac47ca6834aa17"><td class="memItemLeft" align="right" valign="top"><a id="ae24f836c5679c8d2b3ac47ca6834aa17"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ae24f836c5679c8d2b3ac47ca6834aa17">QSPI_INTFLAG_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0000050F)</td></tr>
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<tr class="memdesc:ae24f836c5679c8d2b3ac47ca6834aa17"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INTFLAG) MASK Register <br /></td></tr>
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<tr class="separator:ae24f836c5679c8d2b3ac47ca6834aa17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7e6800de30b18ee1c16a17e8c3683b7d"><td class="memItemLeft" align="right" valign="top"><a id="a7e6800de30b18ee1c16a17e8c3683b7d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a7e6800de30b18ee1c16a17e8c3683b7d">QSPI_STATUS_OFFSET</a>   0x20</td></tr>
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<tr class="memdesc:a7e6800de30b18ee1c16a17e8c3683b7d"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_STATUS offset) Status Register <br /></td></tr>
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<tr class="separator:a7e6800de30b18ee1c16a17e8c3683b7d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af605ee4eedd56fe75b161ca047fe240f"><td class="memItemLeft" align="right" valign="top"><a id="af605ee4eedd56fe75b161ca047fe240f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#af605ee4eedd56fe75b161ca047fe240f">QSPI_STATUS_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000200)</td></tr>
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<tr class="memdesc:af605ee4eedd56fe75b161ca047fe240f"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_STATUS reset_value) Status Register <br /></td></tr>
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<tr class="separator:af605ee4eedd56fe75b161ca047fe240f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaa88fd251eb3cf0fb4d9654ee7e3d0b1"><td class="memItemLeft" align="right" valign="top"><a id="aaa88fd251eb3cf0fb4d9654ee7e3d0b1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#aaa88fd251eb3cf0fb4d9654ee7e3d0b1">QSPI_STATUS_ENABLE_Pos</a>   1</td></tr>
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<tr class="memdesc:aaa88fd251eb3cf0fb4d9654ee7e3d0b1"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_STATUS) Enable <br /></td></tr>
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<tr class="separator:aaa88fd251eb3cf0fb4d9654ee7e3d0b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7a45b4c08fc13dd4a450969380301327"><td class="memItemLeft" align="right" valign="top"><a id="a7a45b4c08fc13dd4a450969380301327"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_STATUS_ENABLE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#aaa88fd251eb3cf0fb4d9654ee7e3d0b1">QSPI_STATUS_ENABLE_Pos</a>)</td></tr>
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<tr class="separator:a7a45b4c08fc13dd4a450969380301327"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1c5b8b83243125a3d95ef7cf08405528"><td class="memItemLeft" align="right" valign="top"><a id="a1c5b8b83243125a3d95ef7cf08405528"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a1c5b8b83243125a3d95ef7cf08405528">QSPI_STATUS_CSSTATUS_Pos</a>   9</td></tr>
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<tr class="memdesc:a1c5b8b83243125a3d95ef7cf08405528"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_STATUS) Chip Select <br /></td></tr>
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<tr class="separator:a1c5b8b83243125a3d95ef7cf08405528"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a732a535ffbab1dd05af95ef000df1932"><td class="memItemLeft" align="right" valign="top"><a id="a732a535ffbab1dd05af95ef000df1932"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_STATUS_CSSTATUS</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a1c5b8b83243125a3d95ef7cf08405528">QSPI_STATUS_CSSTATUS_Pos</a>)</td></tr>
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<tr class="separator:a732a535ffbab1dd05af95ef000df1932"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2e8ceb017e15659067e5a0290bc3aae0"><td class="memItemLeft" align="right" valign="top"><a id="a2e8ceb017e15659067e5a0290bc3aae0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a2e8ceb017e15659067e5a0290bc3aae0">QSPI_STATUS_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000202)</td></tr>
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<tr class="memdesc:a2e8ceb017e15659067e5a0290bc3aae0"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_STATUS) MASK Register <br /></td></tr>
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<tr class="separator:a2e8ceb017e15659067e5a0290bc3aae0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a53d53b732b99eb81d9fa21610fccf04f"><td class="memItemLeft" align="right" valign="top"><a id="a53d53b732b99eb81d9fa21610fccf04f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a53d53b732b99eb81d9fa21610fccf04f">QSPI_INSTRADDR_OFFSET</a>   0x30</td></tr>
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<tr class="memdesc:a53d53b732b99eb81d9fa21610fccf04f"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRADDR offset) Instruction Address <br /></td></tr>
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<tr class="separator:a53d53b732b99eb81d9fa21610fccf04f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8041535b7b3cd42eb509b610555c5d02"><td class="memItemLeft" align="right" valign="top"><a id="a8041535b7b3cd42eb509b610555c5d02"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a8041535b7b3cd42eb509b610555c5d02">QSPI_INSTRADDR_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a8041535b7b3cd42eb509b610555c5d02"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRADDR reset_value) Instruction Address <br /></td></tr>
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<tr class="separator:a8041535b7b3cd42eb509b610555c5d02"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4d2a4b67a0a69a68bfd8580f8e32ae0"><td class="memItemLeft" align="right" valign="top"><a id="ab4d2a4b67a0a69a68bfd8580f8e32ae0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ab4d2a4b67a0a69a68bfd8580f8e32ae0">QSPI_INSTRADDR_ADDR_Pos</a>   0</td></tr>
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<tr class="memdesc:ab4d2a4b67a0a69a68bfd8580f8e32ae0"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRADDR) Instruction Address <br /></td></tr>
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<tr class="separator:ab4d2a4b67a0a69a68bfd8580f8e32ae0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a552f1aa7c0ade80ba261e9e4488c0f86"><td class="memItemLeft" align="right" valign="top"><a id="a552f1aa7c0ade80ba261e9e4488c0f86"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRADDR_ADDR_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFF) << <a class="el" href="component_2qspi_8h.html#ab4d2a4b67a0a69a68bfd8580f8e32ae0">QSPI_INSTRADDR_ADDR_Pos</a>)</td></tr>
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<tr class="separator:a552f1aa7c0ade80ba261e9e4488c0f86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a74fe052d4647878fa868a8f2d7e051be"><td class="memItemLeft" align="right" valign="top"><a id="a74fe052d4647878fa868a8f2d7e051be"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRADDR_ADDR</b>(value)   (QSPI_INSTRADDR_ADDR_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#ab4d2a4b67a0a69a68bfd8580f8e32ae0">QSPI_INSTRADDR_ADDR_Pos</a>))</td></tr>
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<tr class="separator:a74fe052d4647878fa868a8f2d7e051be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af657506ed36c42c07169c45d1a81afa0"><td class="memItemLeft" align="right" valign="top"><a id="af657506ed36c42c07169c45d1a81afa0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#af657506ed36c42c07169c45d1a81afa0">QSPI_INSTRADDR_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFF)</td></tr>
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<tr class="memdesc:af657506ed36c42c07169c45d1a81afa0"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRADDR) MASK Register <br /></td></tr>
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<tr class="separator:af657506ed36c42c07169c45d1a81afa0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a74728d0912c0a270c705e0416893f7ce"><td class="memItemLeft" align="right" valign="top"><a id="a74728d0912c0a270c705e0416893f7ce"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a74728d0912c0a270c705e0416893f7ce">QSPI_INSTRCTRL_OFFSET</a>   0x34</td></tr>
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<tr class="memdesc:a74728d0912c0a270c705e0416893f7ce"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRCTRL offset) Instruction Code <br /></td></tr>
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<tr class="separator:a74728d0912c0a270c705e0416893f7ce"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa1ce0ee489840800779fa57320d9e7f0"><td class="memItemLeft" align="right" valign="top"><a id="aa1ce0ee489840800779fa57320d9e7f0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#aa1ce0ee489840800779fa57320d9e7f0">QSPI_INSTRCTRL_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:aa1ce0ee489840800779fa57320d9e7f0"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRCTRL reset_value) Instruction Code <br /></td></tr>
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<tr class="separator:aa1ce0ee489840800779fa57320d9e7f0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5737034b6cd99686ed0476d8139c14f3"><td class="memItemLeft" align="right" valign="top"><a id="a5737034b6cd99686ed0476d8139c14f3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a5737034b6cd99686ed0476d8139c14f3">QSPI_INSTRCTRL_INSTR_Pos</a>   0</td></tr>
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<tr class="memdesc:a5737034b6cd99686ed0476d8139c14f3"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRCTRL) Instruction Code <br /></td></tr>
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<tr class="separator:a5737034b6cd99686ed0476d8139c14f3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a395b2d7a669e40c26f6558b906c5e6db"><td class="memItemLeft" align="right" valign="top"><a id="a395b2d7a669e40c26f6558b906c5e6db"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRCTRL_INSTR_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFF) << <a class="el" href="component_2qspi_8h.html#a5737034b6cd99686ed0476d8139c14f3">QSPI_INSTRCTRL_INSTR_Pos</a>)</td></tr>
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<tr class="separator:a395b2d7a669e40c26f6558b906c5e6db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af0483b0543f521db27dffabcbcfd153c"><td class="memItemLeft" align="right" valign="top"><a id="af0483b0543f521db27dffabcbcfd153c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRCTRL_INSTR</b>(value)   (QSPI_INSTRCTRL_INSTR_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#a5737034b6cd99686ed0476d8139c14f3">QSPI_INSTRCTRL_INSTR_Pos</a>))</td></tr>
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<tr class="separator:af0483b0543f521db27dffabcbcfd153c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f78f87325cc59f720d3c5d731ae9dfd"><td class="memItemLeft" align="right" valign="top"><a id="a3f78f87325cc59f720d3c5d731ae9dfd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a3f78f87325cc59f720d3c5d731ae9dfd">QSPI_INSTRCTRL_OPTCODE_Pos</a>   16</td></tr>
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<tr class="memdesc:a3f78f87325cc59f720d3c5d731ae9dfd"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRCTRL) Option Code <br /></td></tr>
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<tr class="separator:a3f78f87325cc59f720d3c5d731ae9dfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5fb164e85c4edbe55fd197a5feeefa9b"><td class="memItemLeft" align="right" valign="top"><a id="a5fb164e85c4edbe55fd197a5feeefa9b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRCTRL_OPTCODE_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFF) << <a class="el" href="component_2qspi_8h.html#a3f78f87325cc59f720d3c5d731ae9dfd">QSPI_INSTRCTRL_OPTCODE_Pos</a>)</td></tr>
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<tr class="separator:a5fb164e85c4edbe55fd197a5feeefa9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a30b34672d05a49afe69887bbb69df36d"><td class="memItemLeft" align="right" valign="top"><a id="a30b34672d05a49afe69887bbb69df36d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRCTRL_OPTCODE</b>(value)   (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#a3f78f87325cc59f720d3c5d731ae9dfd">QSPI_INSTRCTRL_OPTCODE_Pos</a>))</td></tr>
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<tr class="separator:a30b34672d05a49afe69887bbb69df36d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad1e2bfa26c544c940adf6d484e4c5631"><td class="memItemLeft" align="right" valign="top"><a id="ad1e2bfa26c544c940adf6d484e4c5631"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ad1e2bfa26c544c940adf6d484e4c5631">QSPI_INSTRCTRL_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00FF00FF)</td></tr>
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<tr class="memdesc:ad1e2bfa26c544c940adf6d484e4c5631"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRCTRL) MASK Register <br /></td></tr>
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<tr class="separator:ad1e2bfa26c544c940adf6d484e4c5631"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab66ce90540b377e88cc87ff352c536a4"><td class="memItemLeft" align="right" valign="top"><a id="ab66ce90540b377e88cc87ff352c536a4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ab66ce90540b377e88cc87ff352c536a4">QSPI_INSTRFRAME_OFFSET</a>   0x38</td></tr>
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<tr class="memdesc:ab66ce90540b377e88cc87ff352c536a4"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME offset) Instruction Frame <br /></td></tr>
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<tr class="memitem:aedcbbeea8784cb67427cb06f00b9b73e"><td class="memItemLeft" align="right" valign="top"><a id="aedcbbeea8784cb67427cb06f00b9b73e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#aedcbbeea8784cb67427cb06f00b9b73e">QSPI_INSTRFRAME_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:aedcbbeea8784cb67427cb06f00b9b73e"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME reset_value) Instruction Frame <br /></td></tr>
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<tr class="memitem:a5f6b8cb121eb8e171b4a864252c6e837"><td class="memItemLeft" align="right" valign="top"><a id="a5f6b8cb121eb8e171b4a864252c6e837"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a5f6b8cb121eb8e171b4a864252c6e837">QSPI_INSTRFRAME_WIDTH_Pos</a>   0</td></tr>
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<tr class="memdesc:a5f6b8cb121eb8e171b4a864252c6e837"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width <br /></td></tr>
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<tr class="memitem:aa7e8bdc975b4677521f937a18cd31435"><td class="memItemLeft" align="right" valign="top"><a id="aa7e8bdc975b4677521f937a18cd31435"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_WIDTH_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x7) << <a class="el" href="component_2qspi_8h.html#a5f6b8cb121eb8e171b4a864252c6e837">QSPI_INSTRFRAME_WIDTH_Pos</a>)</td></tr>
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<tr class="memitem:ae4197ec00cc09192fb3ea9088c32b157"><td class="memItemLeft" align="right" valign="top"><a id="ae4197ec00cc09192fb3ea9088c32b157"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_WIDTH</b>(value)   (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#a5f6b8cb121eb8e171b4a864252c6e837">QSPI_INSTRFRAME_WIDTH_Pos</a>))</td></tr>
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<tr class="memitem:ab8b427909c7320d8ca41e0ff6034ffcf"><td class="memItemLeft" align="right" valign="top"><a id="ab8b427909c7320d8ca41e0ff6034ffcf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ab8b427909c7320d8ca41e0ff6034ffcf">QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0)</td></tr>
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<tr class="memdesc:ab8b427909c7320d8ca41e0ff6034ffcf"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI <br /></td></tr>
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<tr class="memitem:a03c466b6e763fa6d75f18b88536bcef6"><td class="memItemLeft" align="right" valign="top"><a id="a03c466b6e763fa6d75f18b88536bcef6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a03c466b6e763fa6d75f18b88536bcef6">QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1)</td></tr>
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<tr class="memdesc:a03c466b6e763fa6d75f18b88536bcef6"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI <br /></td></tr>
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<tr class="memitem:a28a462a81538156bd39098f8f1f4c908"><td class="memItemLeft" align="right" valign="top"><a id="a28a462a81538156bd39098f8f1f4c908"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a28a462a81538156bd39098f8f1f4c908">QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x2)</td></tr>
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<tr class="memdesc:a28a462a81538156bd39098f8f1f4c908"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI <br /></td></tr>
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<tr class="memitem:a64363c446a0322ad48abc9115f7a4073"><td class="memItemLeft" align="right" valign="top"><a id="a64363c446a0322ad48abc9115f7a4073"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a64363c446a0322ad48abc9115f7a4073">QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3)</td></tr>
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<tr class="memdesc:a64363c446a0322ad48abc9115f7a4073"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI <br /></td></tr>
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<tr class="memitem:a8082139abf8aea1bf61d2d73417e0d63"><td class="memItemLeft" align="right" valign="top"><a id="a8082139abf8aea1bf61d2d73417e0d63"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a8082139abf8aea1bf61d2d73417e0d63">QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x4)</td></tr>
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<tr class="memdesc:a8082139abf8aea1bf61d2d73417e0d63"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI <br /></td></tr>
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<tr class="memitem:a0c9c48a46e4243e666f5d2778616d5fd"><td class="memItemLeft" align="right" valign="top"><a id="a0c9c48a46e4243e666f5d2778616d5fd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a0c9c48a46e4243e666f5d2778616d5fd">QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x5)</td></tr>
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<tr class="memdesc:a0c9c48a46e4243e666f5d2778616d5fd"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI <br /></td></tr>
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<tr class="memitem:a4b16ae5f4120aba8080c2075c0c85107"><td class="memItemLeft" align="right" valign="top"><a id="a4b16ae5f4120aba8080c2075c0c85107"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a4b16ae5f4120aba8080c2075c0c85107">QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x6)</td></tr>
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<tr class="memdesc:a4b16ae5f4120aba8080c2075c0c85107"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI <br /></td></tr>
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<tr class="memitem:a639d247b7edc8af835eb6c9695bad01d"><td class="memItemLeft" align="right" valign="top"><a id="a639d247b7edc8af835eb6c9695bad01d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI</b>   (<a class="el" href="component_2qspi_8h.html#ab8b427909c7320d8ca41e0ff6034ffcf">QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val</a> << <a class="el" href="component_2qspi_8h.html#a5f6b8cb121eb8e171b4a864252c6e837">QSPI_INSTRFRAME_WIDTH_Pos</a>)</td></tr>
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<tr class="memitem:aca0c34ddc7199f006ac90b99b38b589e"><td class="memItemLeft" align="right" valign="top"><a id="aca0c34ddc7199f006ac90b99b38b589e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT</b>   (<a class="el" href="component_2qspi_8h.html#a03c466b6e763fa6d75f18b88536bcef6">QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val</a> << <a class="el" href="component_2qspi_8h.html#a5f6b8cb121eb8e171b4a864252c6e837">QSPI_INSTRFRAME_WIDTH_Pos</a>)</td></tr>
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<tr class="memitem:a998887275210a99f2492c32b03d32b17"><td class="memItemLeft" align="right" valign="top"><a id="a998887275210a99f2492c32b03d32b17"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT</b>   (<a class="el" href="component_2qspi_8h.html#a28a462a81538156bd39098f8f1f4c908">QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val</a> << <a class="el" href="component_2qspi_8h.html#a5f6b8cb121eb8e171b4a864252c6e837">QSPI_INSTRFRAME_WIDTH_Pos</a>)</td></tr>
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<tr class="memitem:aa3b71de76268ba350a5049e72ef4d748"><td class="memItemLeft" align="right" valign="top"><a id="aa3b71de76268ba350a5049e72ef4d748"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_WIDTH_DUAL_IO</b>   (<a class="el" href="component_2qspi_8h.html#a64363c446a0322ad48abc9115f7a4073">QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val</a> << <a class="el" href="component_2qspi_8h.html#a5f6b8cb121eb8e171b4a864252c6e837">QSPI_INSTRFRAME_WIDTH_Pos</a>)</td></tr>
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<tr class="separator:aa3b71de76268ba350a5049e72ef4d748"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b105680d1fbf85cc7426e29b78f8d32"><td class="memItemLeft" align="right" valign="top"><a id="a8b105680d1fbf85cc7426e29b78f8d32"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_WIDTH_QUAD_IO</b>   (<a class="el" href="component_2qspi_8h.html#a8082139abf8aea1bf61d2d73417e0d63">QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val</a> << <a class="el" href="component_2qspi_8h.html#a5f6b8cb121eb8e171b4a864252c6e837">QSPI_INSTRFRAME_WIDTH_Pos</a>)</td></tr>
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<tr class="separator:a8b105680d1fbf85cc7426e29b78f8d32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a30257d007608868f9d1cb897bdbaff28"><td class="memItemLeft" align="right" valign="top"><a id="a30257d007608868f9d1cb897bdbaff28"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_WIDTH_DUAL_CMD</b>   (<a class="el" href="component_2qspi_8h.html#a0c9c48a46e4243e666f5d2778616d5fd">QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val</a> << <a class="el" href="component_2qspi_8h.html#a5f6b8cb121eb8e171b4a864252c6e837">QSPI_INSTRFRAME_WIDTH_Pos</a>)</td></tr>
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<tr class="separator:a30257d007608868f9d1cb897bdbaff28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aec7bffdfa44747ed296ec03cb51cb1bf"><td class="memItemLeft" align="right" valign="top"><a id="aec7bffdfa44747ed296ec03cb51cb1bf"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_WIDTH_QUAD_CMD</b>   (<a class="el" href="component_2qspi_8h.html#a4b16ae5f4120aba8080c2075c0c85107">QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val</a> << <a class="el" href="component_2qspi_8h.html#a5f6b8cb121eb8e171b4a864252c6e837">QSPI_INSTRFRAME_WIDTH_Pos</a>)</td></tr>
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<tr class="separator:aec7bffdfa44747ed296ec03cb51cb1bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0843a1698c23e27569fb71b0b3ae02ba"><td class="memItemLeft" align="right" valign="top"><a id="a0843a1698c23e27569fb71b0b3ae02ba"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a0843a1698c23e27569fb71b0b3ae02ba">QSPI_INSTRFRAME_INSTREN_Pos</a>   4</td></tr>
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<tr class="memdesc:a0843a1698c23e27569fb71b0b3ae02ba"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Instruction Enable <br /></td></tr>
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<tr class="separator:a0843a1698c23e27569fb71b0b3ae02ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a62c891ebc16a4013f39cca674fb0fe7a"><td class="memItemLeft" align="right" valign="top"><a id="a62c891ebc16a4013f39cca674fb0fe7a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_INSTREN</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a0843a1698c23e27569fb71b0b3ae02ba">QSPI_INSTRFRAME_INSTREN_Pos</a>)</td></tr>
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<tr class="separator:a62c891ebc16a4013f39cca674fb0fe7a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac6406ae6a861ba312ba41d9431bf52a7"><td class="memItemLeft" align="right" valign="top"><a id="ac6406ae6a861ba312ba41d9431bf52a7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ac6406ae6a861ba312ba41d9431bf52a7">QSPI_INSTRFRAME_ADDREN_Pos</a>   5</td></tr>
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<tr class="memdesc:ac6406ae6a861ba312ba41d9431bf52a7"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Address Enable <br /></td></tr>
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<tr class="separator:ac6406ae6a861ba312ba41d9431bf52a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa8a3298f63c0745e14be5e9c17b3ca71"><td class="memItemLeft" align="right" valign="top"><a id="aa8a3298f63c0745e14be5e9c17b3ca71"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_ADDREN</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#ac6406ae6a861ba312ba41d9431bf52a7">QSPI_INSTRFRAME_ADDREN_Pos</a>)</td></tr>
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<tr class="separator:aa8a3298f63c0745e14be5e9c17b3ca71"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af7ff4d7f4f670762eba7a59aa22e9c29"><td class="memItemLeft" align="right" valign="top"><a id="af7ff4d7f4f670762eba7a59aa22e9c29"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#af7ff4d7f4f670762eba7a59aa22e9c29">QSPI_INSTRFRAME_OPTCODEEN_Pos</a>   6</td></tr>
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<tr class="memdesc:af7ff4d7f4f670762eba7a59aa22e9c29"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Option Enable <br /></td></tr>
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<tr class="separator:af7ff4d7f4f670762eba7a59aa22e9c29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9638ccb4ea87155430b07ca695a9f6eb"><td class="memItemLeft" align="right" valign="top"><a id="a9638ccb4ea87155430b07ca695a9f6eb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_OPTCODEEN</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#af7ff4d7f4f670762eba7a59aa22e9c29">QSPI_INSTRFRAME_OPTCODEEN_Pos</a>)</td></tr>
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<tr class="separator:a9638ccb4ea87155430b07ca695a9f6eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adee8fa29957db9951e7c5fd33a406695"><td class="memItemLeft" align="right" valign="top"><a id="adee8fa29957db9951e7c5fd33a406695"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#adee8fa29957db9951e7c5fd33a406695">QSPI_INSTRFRAME_DATAEN_Pos</a>   7</td></tr>
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<tr class="memdesc:adee8fa29957db9951e7c5fd33a406695"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Data Enable <br /></td></tr>
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<tr class="separator:adee8fa29957db9951e7c5fd33a406695"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab1f31a2524c3838ce33f71f35eea36b9"><td class="memItemLeft" align="right" valign="top"><a id="ab1f31a2524c3838ce33f71f35eea36b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_DATAEN</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#adee8fa29957db9951e7c5fd33a406695">QSPI_INSTRFRAME_DATAEN_Pos</a>)</td></tr>
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<tr class="memitem:a923187fc9942a4915faf4044178d1a05"><td class="memItemLeft" align="right" valign="top"><a id="a923187fc9942a4915faf4044178d1a05"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a923187fc9942a4915faf4044178d1a05">QSPI_INSTRFRAME_OPTCODELEN_Pos</a>   8</td></tr>
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<tr class="memdesc:a923187fc9942a4915faf4044178d1a05"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Option Code Length <br /></td></tr>
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<tr class="memitem:a8fed63f36fc5a1d491a2a266d2a73f35"><td class="memItemLeft" align="right" valign="top"><a id="a8fed63f36fc5a1d491a2a266d2a73f35"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_OPTCODELEN_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3) << <a class="el" href="component_2qspi_8h.html#a923187fc9942a4915faf4044178d1a05">QSPI_INSTRFRAME_OPTCODELEN_Pos</a>)</td></tr>
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<tr class="memitem:aa11175420c02d501e6c6669fb427e6e7"><td class="memItemLeft" align="right" valign="top"><a id="aa11175420c02d501e6c6669fb427e6e7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_OPTCODELEN</b>(value)   (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#a923187fc9942a4915faf4044178d1a05">QSPI_INSTRFRAME_OPTCODELEN_Pos</a>))</td></tr>
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<tr class="memitem:a64f49c3e874ab484109880274c45d2eb"><td class="memItemLeft" align="right" valign="top"><a id="a64f49c3e874ab484109880274c45d2eb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a64f49c3e874ab484109880274c45d2eb">QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0)</td></tr>
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<tr class="memdesc:a64f49c3e874ab484109880274c45d2eb"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) 1-bit length option code <br /></td></tr>
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<tr class="memitem:acf488437ecfe7c0c0aa186c7080dda5f"><td class="memItemLeft" align="right" valign="top"><a id="acf488437ecfe7c0c0aa186c7080dda5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#acf488437ecfe7c0c0aa186c7080dda5f">QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1)</td></tr>
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<tr class="memdesc:acf488437ecfe7c0c0aa186c7080dda5f"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) 2-bits length option code <br /></td></tr>
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<tr class="memitem:ac74f989f9c35449db596e47892d8ebdd"><td class="memItemLeft" align="right" valign="top"><a id="ac74f989f9c35449db596e47892d8ebdd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ac74f989f9c35449db596e47892d8ebdd">QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x2)</td></tr>
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<tr class="memdesc:ac74f989f9c35449db596e47892d8ebdd"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) 4-bits length option code <br /></td></tr>
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<tr class="memitem:aafeff47fb7739c3048d6be6f3f10d490"><td class="memItemLeft" align="right" valign="top"><a id="aafeff47fb7739c3048d6be6f3f10d490"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#aafeff47fb7739c3048d6be6f3f10d490">QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3)</td></tr>
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<tr class="memdesc:aafeff47fb7739c3048d6be6f3f10d490"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) 8-bits length option code <br /></td></tr>
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<tr class="memitem:a0cb2bf8f89634e770cf48640d849399e"><td class="memItemLeft" align="right" valign="top"><a id="a0cb2bf8f89634e770cf48640d849399e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_OPTCODELEN_1BIT</b>   (<a class="el" href="component_2qspi_8h.html#a64f49c3e874ab484109880274c45d2eb">QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val</a> << <a class="el" href="component_2qspi_8h.html#a923187fc9942a4915faf4044178d1a05">QSPI_INSTRFRAME_OPTCODELEN_Pos</a>)</td></tr>
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<tr class="memitem:a83b6fa835e6fc09ccf2c2ec97a011ef1"><td class="memItemLeft" align="right" valign="top"><a id="a83b6fa835e6fc09ccf2c2ec97a011ef1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_OPTCODELEN_2BITS</b>   (<a class="el" href="component_2qspi_8h.html#acf488437ecfe7c0c0aa186c7080dda5f">QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#a923187fc9942a4915faf4044178d1a05">QSPI_INSTRFRAME_OPTCODELEN_Pos</a>)</td></tr>
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<tr class="memitem:a45b513f46b3220da8a7a0db7a93b763d"><td class="memItemLeft" align="right" valign="top"><a id="a45b513f46b3220da8a7a0db7a93b763d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_OPTCODELEN_4BITS</b>   (<a class="el" href="component_2qspi_8h.html#ac74f989f9c35449db596e47892d8ebdd">QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#a923187fc9942a4915faf4044178d1a05">QSPI_INSTRFRAME_OPTCODELEN_Pos</a>)</td></tr>
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<tr class="memitem:abe171b6a7622389da8fcff94d6be7b3a"><td class="memItemLeft" align="right" valign="top"><a id="abe171b6a7622389da8fcff94d6be7b3a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_OPTCODELEN_8BITS</b>   (<a class="el" href="component_2qspi_8h.html#aafeff47fb7739c3048d6be6f3f10d490">QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#a923187fc9942a4915faf4044178d1a05">QSPI_INSTRFRAME_OPTCODELEN_Pos</a>)</td></tr>
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<tr class="memitem:a440d902fc7241e1108aeb3d50e700624"><td class="memItemLeft" align="right" valign="top"><a id="a440d902fc7241e1108aeb3d50e700624"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a440d902fc7241e1108aeb3d50e700624">QSPI_INSTRFRAME_ADDRLEN_Pos</a>   10</td></tr>
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<tr class="memdesc:a440d902fc7241e1108aeb3d50e700624"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Address Length <br /></td></tr>
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<tr class="memitem:aab48e8ebd939357cead914187375e224"><td class="memItemLeft" align="right" valign="top"><a id="aab48e8ebd939357cead914187375e224"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_ADDRLEN</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a440d902fc7241e1108aeb3d50e700624">QSPI_INSTRFRAME_ADDRLEN_Pos</a>)</td></tr>
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<tr class="separator:aab48e8ebd939357cead914187375e224"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8727889d2a96d4323b9c96d03e53e451"><td class="memItemLeft" align="right" valign="top"><a id="a8727889d2a96d4323b9c96d03e53e451"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a8727889d2a96d4323b9c96d03e53e451">QSPI_INSTRFRAME_ADDRLEN_24BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0)</td></tr>
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<tr class="memdesc:a8727889d2a96d4323b9c96d03e53e451"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) 24-bits address length <br /></td></tr>
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<tr class="memitem:ada34328fde3d54c15380cd1c5e5ca3a9"><td class="memItemLeft" align="right" valign="top"><a id="ada34328fde3d54c15380cd1c5e5ca3a9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ada34328fde3d54c15380cd1c5e5ca3a9">QSPI_INSTRFRAME_ADDRLEN_32BITS_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1)</td></tr>
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<tr class="memdesc:ada34328fde3d54c15380cd1c5e5ca3a9"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) 32-bits address length <br /></td></tr>
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<tr class="memitem:a654534e226fee899c1dbeb9c52e07954"><td class="memItemLeft" align="right" valign="top"><a id="a654534e226fee899c1dbeb9c52e07954"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_ADDRLEN_24BITS</b>   (<a class="el" href="component_2qspi_8h.html#a8727889d2a96d4323b9c96d03e53e451">QSPI_INSTRFRAME_ADDRLEN_24BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#a440d902fc7241e1108aeb3d50e700624">QSPI_INSTRFRAME_ADDRLEN_Pos</a>)</td></tr>
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<tr class="memitem:ad18c4ae8e2f9ae5e1ee851ee14b71a9d"><td class="memItemLeft" align="right" valign="top"><a id="ad18c4ae8e2f9ae5e1ee851ee14b71a9d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_ADDRLEN_32BITS</b>   (<a class="el" href="component_2qspi_8h.html#ada34328fde3d54c15380cd1c5e5ca3a9">QSPI_INSTRFRAME_ADDRLEN_32BITS_Val</a> << <a class="el" href="component_2qspi_8h.html#a440d902fc7241e1108aeb3d50e700624">QSPI_INSTRFRAME_ADDRLEN_Pos</a>)</td></tr>
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<tr class="memitem:aa72d8939be0af6821a1593d0597af785"><td class="memItemLeft" align="right" valign="top"><a id="aa72d8939be0af6821a1593d0597af785"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#aa72d8939be0af6821a1593d0597af785">QSPI_INSTRFRAME_TFRTYPE_Pos</a>   12</td></tr>
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<tr class="memdesc:aa72d8939be0af6821a1593d0597af785"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Data Transfer Type <br /></td></tr>
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<tr class="memitem:a16b0a1e2b04667bb61c931c65e4ca090"><td class="memItemLeft" align="right" valign="top"><a id="a16b0a1e2b04667bb61c931c65e4ca090"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_TFRTYPE_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3) << <a class="el" href="component_2qspi_8h.html#aa72d8939be0af6821a1593d0597af785">QSPI_INSTRFRAME_TFRTYPE_Pos</a>)</td></tr>
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<tr class="separator:a16b0a1e2b04667bb61c931c65e4ca090"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7d5ba51eb425148add30f65f2499bb15"><td class="memItemLeft" align="right" valign="top"><a id="a7d5ba51eb425148add30f65f2499bb15"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_TFRTYPE</b>(value)   (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#aa72d8939be0af6821a1593d0597af785">QSPI_INSTRFRAME_TFRTYPE_Pos</a>))</td></tr>
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<tr class="separator:a7d5ba51eb425148add30f65f2499bb15"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab8537a06c56a445da40d0947edba99b7"><td class="memItemLeft" align="right" valign="top"><a id="ab8537a06c56a445da40d0947edba99b7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ab8537a06c56a445da40d0947edba99b7">QSPI_INSTRFRAME_TFRTYPE_READ_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0)</td></tr>
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<tr class="memdesc:ab8537a06c56a445da40d0947edba99b7"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. <br /></td></tr>
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<tr class="separator:ab8537a06c56a445da40d0947edba99b7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afe76dd530506516ca7ab6756bea3d23e"><td class="memItemLeft" align="right" valign="top"><a id="afe76dd530506516ca7ab6756bea3d23e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#afe76dd530506516ca7ab6756bea3d23e">QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1)</td></tr>
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<tr class="memdesc:afe76dd530506516ca7ab6756bea3d23e"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. <br /></td></tr>
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<tr class="memitem:ab78f113a8fe8b4fc0fd056f2f49eeb04"><td class="memItemLeft" align="right" valign="top"><a id="ab78f113a8fe8b4fc0fd056f2f49eeb04"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ab78f113a8fe8b4fc0fd056f2f49eeb04">QSPI_INSTRFRAME_TFRTYPE_WRITE_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x2)</td></tr>
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<tr class="memdesc:ab78f113a8fe8b4fc0fd056f2f49eeb04"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed. <br /></td></tr>
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<tr class="separator:ab78f113a8fe8b4fc0fd056f2f49eeb04"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a836f913b830e6d77f2e89a5034a79f84"><td class="memItemLeft" align="right" valign="top"><a id="a836f913b830e6d77f2e89a5034a79f84"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a836f913b830e6d77f2e89a5034a79f84">QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3)</td></tr>
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<tr class="memdesc:a836f913b830e6d77f2e89a5034a79f84"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed. <br /></td></tr>
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<tr class="separator:a836f913b830e6d77f2e89a5034a79f84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaa0874b2abb48d096acb8d1cf1281792"><td class="memItemLeft" align="right" valign="top"><a id="aaa0874b2abb48d096acb8d1cf1281792"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_TFRTYPE_READ</b>   (<a class="el" href="component_2qspi_8h.html#ab8537a06c56a445da40d0947edba99b7">QSPI_INSTRFRAME_TFRTYPE_READ_Val</a> << <a class="el" href="component_2qspi_8h.html#aa72d8939be0af6821a1593d0597af785">QSPI_INSTRFRAME_TFRTYPE_Pos</a>)</td></tr>
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<tr class="separator:aaa0874b2abb48d096acb8d1cf1281792"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9b50b059752d02a97c76a6bdb12af75c"><td class="memItemLeft" align="right" valign="top"><a id="a9b50b059752d02a97c76a6bdb12af75c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_TFRTYPE_READMEMORY</b>   (<a class="el" href="component_2qspi_8h.html#afe76dd530506516ca7ab6756bea3d23e">QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val</a> << <a class="el" href="component_2qspi_8h.html#aa72d8939be0af6821a1593d0597af785">QSPI_INSTRFRAME_TFRTYPE_Pos</a>)</td></tr>
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<tr class="separator:a9b50b059752d02a97c76a6bdb12af75c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1c9ba19492d0d73a0031848eb146d91d"><td class="memItemLeft" align="right" valign="top"><a id="a1c9ba19492d0d73a0031848eb146d91d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_TFRTYPE_WRITE</b>   (<a class="el" href="component_2qspi_8h.html#ab78f113a8fe8b4fc0fd056f2f49eeb04">QSPI_INSTRFRAME_TFRTYPE_WRITE_Val</a> << <a class="el" href="component_2qspi_8h.html#aa72d8939be0af6821a1593d0597af785">QSPI_INSTRFRAME_TFRTYPE_Pos</a>)</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY</b>   (<a class="el" href="component_2qspi_8h.html#a836f913b830e6d77f2e89a5034a79f84">QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val</a> << <a class="el" href="component_2qspi_8h.html#aa72d8939be0af6821a1593d0597af785">QSPI_INSTRFRAME_TFRTYPE_Pos</a>)</td></tr>
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<tr class="memitem:a476f3ff950fefce63da315c5bdf86ec5"><td class="memItemLeft" align="right" valign="top"><a id="a476f3ff950fefce63da315c5bdf86ec5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a476f3ff950fefce63da315c5bdf86ec5">QSPI_INSTRFRAME_CRMODE_Pos</a>   14</td></tr>
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<tr class="memdesc:a476f3ff950fefce63da315c5bdf86ec5"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Continuous Read Mode <br /></td></tr>
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<tr class="memitem:a18268dae335a147fa60d054119633637"><td class="memItemLeft" align="right" valign="top"><a id="a18268dae335a147fa60d054119633637"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_CRMODE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a476f3ff950fefce63da315c5bdf86ec5">QSPI_INSTRFRAME_CRMODE_Pos</a>)</td></tr>
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<tr class="memitem:a26ec5331c17d1fdcb0b29af957828a14"><td class="memItemLeft" align="right" valign="top"><a id="a26ec5331c17d1fdcb0b29af957828a14"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a26ec5331c17d1fdcb0b29af957828a14">QSPI_INSTRFRAME_DDREN_Pos</a>   15</td></tr>
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<tr class="memdesc:a26ec5331c17d1fdcb0b29af957828a14"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Double Data Rate Enable <br /></td></tr>
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<tr class="memitem:a30ec3a99cda3ee060067f11cea8582f5"><td class="memItemLeft" align="right" valign="top"><a id="a30ec3a99cda3ee060067f11cea8582f5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_DDREN</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a26ec5331c17d1fdcb0b29af957828a14">QSPI_INSTRFRAME_DDREN_Pos</a>)</td></tr>
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<tr class="memitem:af0ca18bc8af0098f38b5a7f536d8cab9"><td class="memItemLeft" align="right" valign="top"><a id="af0ca18bc8af0098f38b5a7f536d8cab9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#af0ca18bc8af0098f38b5a7f536d8cab9">QSPI_INSTRFRAME_DUMMYLEN_Pos</a>   16</td></tr>
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<tr class="memdesc:af0ca18bc8af0098f38b5a7f536d8cab9"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) Dummy Cycles Length <br /></td></tr>
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<tr class="memitem:a3e0e1a2d178308136fdade58d6306b1a"><td class="memItemLeft" align="right" valign="top"><a id="a3e0e1a2d178308136fdade58d6306b1a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_DUMMYLEN_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1F) << <a class="el" href="component_2qspi_8h.html#af0ca18bc8af0098f38b5a7f536d8cab9">QSPI_INSTRFRAME_DUMMYLEN_Pos</a>)</td></tr>
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<tr class="memitem:a67bb326b1dfc41ffd9b7aace2331506c"><td class="memItemLeft" align="right" valign="top"><a id="a67bb326b1dfc41ffd9b7aace2331506c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_INSTRFRAME_DUMMYLEN</b>(value)   (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#af0ca18bc8af0098f38b5a7f536d8cab9">QSPI_INSTRFRAME_DUMMYLEN_Pos</a>))</td></tr>
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<tr class="memitem:a45edf136a4e4b5219cda1aed53461ad1"><td class="memItemLeft" align="right" valign="top"><a id="a45edf136a4e4b5219cda1aed53461ad1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a45edf136a4e4b5219cda1aed53461ad1">QSPI_INSTRFRAME_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x001FF7F7)</td></tr>
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<tr class="memdesc:a45edf136a4e4b5219cda1aed53461ad1"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_INSTRFRAME) MASK Register <br /></td></tr>
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<tr class="separator:a45edf136a4e4b5219cda1aed53461ad1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9f7acff6060bd153c03ee375a416abc1"><td class="memItemLeft" align="right" valign="top"><a id="a9f7acff6060bd153c03ee375a416abc1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a9f7acff6060bd153c03ee375a416abc1">QSPI_SCRAMBCTRL_OFFSET</a>   0x40</td></tr>
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<tr class="memdesc:a9f7acff6060bd153c03ee375a416abc1"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_SCRAMBCTRL offset) Scrambling Mode <br /></td></tr>
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<tr class="memitem:a6da38b6cbd11e1d96dc9ad1e2222b8bd"><td class="memItemLeft" align="right" valign="top"><a id="a6da38b6cbd11e1d96dc9ad1e2222b8bd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a6da38b6cbd11e1d96dc9ad1e2222b8bd">QSPI_SCRAMBCTRL_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a6da38b6cbd11e1d96dc9ad1e2222b8bd"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_SCRAMBCTRL reset_value) Scrambling Mode <br /></td></tr>
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<tr class="separator:a6da38b6cbd11e1d96dc9ad1e2222b8bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2f232227955f50262bddc1e61a89ff84"><td class="memItemLeft" align="right" valign="top"><a id="a2f232227955f50262bddc1e61a89ff84"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a2f232227955f50262bddc1e61a89ff84">QSPI_SCRAMBCTRL_ENABLE_Pos</a>   0</td></tr>
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<tr class="memdesc:a2f232227955f50262bddc1e61a89ff84"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable <br /></td></tr>
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<tr class="separator:a2f232227955f50262bddc1e61a89ff84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0478ddf67a383c76f8ae550d223831d8"><td class="memItemLeft" align="right" valign="top"><a id="a0478ddf67a383c76f8ae550d223831d8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_SCRAMBCTRL_ENABLE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#a2f232227955f50262bddc1e61a89ff84">QSPI_SCRAMBCTRL_ENABLE_Pos</a>)</td></tr>
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<tr class="separator:a0478ddf67a383c76f8ae550d223831d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae0be1ea93dedc3ea78044e7689027215"><td class="memItemLeft" align="right" valign="top"><a id="ae0be1ea93dedc3ea78044e7689027215"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ae0be1ea93dedc3ea78044e7689027215">QSPI_SCRAMBCTRL_RANDOMDIS_Pos</a>   1</td></tr>
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<tr class="memdesc:ae0be1ea93dedc3ea78044e7689027215"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable <br /></td></tr>
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<tr class="separator:ae0be1ea93dedc3ea78044e7689027215"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac944922a048b24c292827cbc6ba3eb7e"><td class="memItemLeft" align="right" valign="top"><a id="ac944922a048b24c292827cbc6ba3eb7e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_SCRAMBCTRL_RANDOMDIS</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2qspi_8h.html#ae0be1ea93dedc3ea78044e7689027215">QSPI_SCRAMBCTRL_RANDOMDIS_Pos</a>)</td></tr>
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<tr class="separator:ac944922a048b24c292827cbc6ba3eb7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad22d15dfb114dc6a1a1ed5fd883336db"><td class="memItemLeft" align="right" valign="top"><a id="ad22d15dfb114dc6a1a1ed5fd883336db"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ad22d15dfb114dc6a1a1ed5fd883336db">QSPI_SCRAMBCTRL_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000003)</td></tr>
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<tr class="memdesc:ad22d15dfb114dc6a1a1ed5fd883336db"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_SCRAMBCTRL) MASK Register <br /></td></tr>
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<tr class="separator:ad22d15dfb114dc6a1a1ed5fd883336db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b2884969f43bf3ab836cc58f80c6f60"><td class="memItemLeft" align="right" valign="top"><a id="a8b2884969f43bf3ab836cc58f80c6f60"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a8b2884969f43bf3ab836cc58f80c6f60">QSPI_SCRAMBKEY_OFFSET</a>   0x44</td></tr>
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<tr class="memdesc:a8b2884969f43bf3ab836cc58f80c6f60"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_SCRAMBKEY offset) Scrambling Key <br /></td></tr>
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<tr class="separator:a8b2884969f43bf3ab836cc58f80c6f60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab7bf6ac11510711a9128d215c055bc53"><td class="memItemLeft" align="right" valign="top"><a id="ab7bf6ac11510711a9128d215c055bc53"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#ab7bf6ac11510711a9128d215c055bc53">QSPI_SCRAMBKEY_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:ab7bf6ac11510711a9128d215c055bc53"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_SCRAMBKEY reset_value) Scrambling Key <br /></td></tr>
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<tr class="separator:ab7bf6ac11510711a9128d215c055bc53"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2b83fe892cc0b989a9b1790ba647eff9"><td class="memItemLeft" align="right" valign="top"><a id="a2b83fe892cc0b989a9b1790ba647eff9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#a2b83fe892cc0b989a9b1790ba647eff9">QSPI_SCRAMBKEY_KEY_Pos</a>   0</td></tr>
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<tr class="memdesc:a2b83fe892cc0b989a9b1790ba647eff9"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_SCRAMBKEY) Scrambling User Key <br /></td></tr>
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<tr class="separator:a2b83fe892cc0b989a9b1790ba647eff9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9b09f903c6d661bd63e5374eb132d6d7"><td class="memItemLeft" align="right" valign="top"><a id="a9b09f903c6d661bd63e5374eb132d6d7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_SCRAMBKEY_KEY_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFF) << <a class="el" href="component_2qspi_8h.html#a2b83fe892cc0b989a9b1790ba647eff9">QSPI_SCRAMBKEY_KEY_Pos</a>)</td></tr>
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<tr class="separator:a9b09f903c6d661bd63e5374eb132d6d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa182e776d9acfaa11080750993c9af63"><td class="memItemLeft" align="right" valign="top"><a id="aa182e776d9acfaa11080750993c9af63"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>QSPI_SCRAMBKEY_KEY</b>(value)   (QSPI_SCRAMBKEY_KEY_Msk & ((value) << <a class="el" href="component_2qspi_8h.html#a2b83fe892cc0b989a9b1790ba647eff9">QSPI_SCRAMBKEY_KEY_Pos</a>))</td></tr>
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<tr class="separator:aa182e776d9acfaa11080750993c9af63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af89ee04ceeef535fbe3d6167c7ae040a"><td class="memItemLeft" align="right" valign="top"><a id="af89ee04ceeef535fbe3d6167c7ae040a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2qspi_8h.html#af89ee04ceeef535fbe3d6167c7ae040a">QSPI_SCRAMBKEY_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFF)</td></tr>
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<tr class="memdesc:af89ee04ceeef535fbe3d6167c7ae040a"><td class="mdescLeft"> </td><td class="mdescRight">(QSPI_SCRAMBKEY) MASK Register <br /></td></tr>
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<tr class="separator:af89ee04ceeef535fbe3d6167c7ae040a"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Component description for QSPI. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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