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425 lines
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<div class="title">gclk.h File Reference</div> </div>
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</div><!--header-->
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<div class="contents">
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<p>Instance description for GCLK.
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<a href="#details">More...</a></p>
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<p><a href="instance_2gclk_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a4b78d03bf9a16178a366c10a9df50f46"><td class="memItemLeft" align="right" valign="top"><a id="a4b78d03bf9a16178a366c10a9df50f46"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a4b78d03bf9a16178a366c10a9df50f46">REG_GCLK_CTRLA</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40001C00UL)</td></tr>
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<tr class="memdesc:a4b78d03bf9a16178a366c10a9df50f46"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Control <br /></td></tr>
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<tr class="separator:a4b78d03bf9a16178a366c10a9df50f46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a019f805046bd8fbce07db4ff58608123"><td class="memItemLeft" align="right" valign="top"><a id="a019f805046bd8fbce07db4ff58608123"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a019f805046bd8fbce07db4ff58608123">REG_GCLK_SYNCBUSY</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x40001C04UL)</td></tr>
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<tr class="memdesc:a019f805046bd8fbce07db4ff58608123"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Synchronization Busy <br /></td></tr>
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<tr class="separator:a019f805046bd8fbce07db4ff58608123"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4994fd8500fda53023cd224b105b0f4e"><td class="memItemLeft" align="right" valign="top"><a id="a4994fd8500fda53023cd224b105b0f4e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a4994fd8500fda53023cd224b105b0f4e">REG_GCLK_GENCTRL0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C20UL)</td></tr>
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<tr class="memdesc:a4994fd8500fda53023cd224b105b0f4e"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Generic Clock Generator Control 0 <br /></td></tr>
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<tr class="separator:a4994fd8500fda53023cd224b105b0f4e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a63217ed3209856895f367b0f796a7257"><td class="memItemLeft" align="right" valign="top"><a id="a63217ed3209856895f367b0f796a7257"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a63217ed3209856895f367b0f796a7257">REG_GCLK_GENCTRL1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C24UL)</td></tr>
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<tr class="memdesc:a63217ed3209856895f367b0f796a7257"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Generic Clock Generator Control 1 <br /></td></tr>
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<tr class="separator:a63217ed3209856895f367b0f796a7257"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a20fd0ac484281f177e034b6fcb1f83b0"><td class="memItemLeft" align="right" valign="top"><a id="a20fd0ac484281f177e034b6fcb1f83b0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a20fd0ac484281f177e034b6fcb1f83b0">REG_GCLK_GENCTRL2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C28UL)</td></tr>
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<tr class="memdesc:a20fd0ac484281f177e034b6fcb1f83b0"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Generic Clock Generator Control 2 <br /></td></tr>
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<tr class="separator:a20fd0ac484281f177e034b6fcb1f83b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a249c18ab8d2c25b90284a97de2decf2f"><td class="memItemLeft" align="right" valign="top"><a id="a249c18ab8d2c25b90284a97de2decf2f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a249c18ab8d2c25b90284a97de2decf2f">REG_GCLK_GENCTRL3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C2CUL)</td></tr>
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<tr class="memdesc:a249c18ab8d2c25b90284a97de2decf2f"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Generic Clock Generator Control 3 <br /></td></tr>
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<tr class="separator:a249c18ab8d2c25b90284a97de2decf2f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae30fecf468d8a76bac62e54f5e257c8c"><td class="memItemLeft" align="right" valign="top"><a id="ae30fecf468d8a76bac62e54f5e257c8c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#ae30fecf468d8a76bac62e54f5e257c8c">REG_GCLK_GENCTRL4</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C30UL)</td></tr>
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<tr class="memdesc:ae30fecf468d8a76bac62e54f5e257c8c"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Generic Clock Generator Control 4 <br /></td></tr>
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<tr class="separator:ae30fecf468d8a76bac62e54f5e257c8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5141d184ba677110d14f71e25ef16299"><td class="memItemLeft" align="right" valign="top"><a id="a5141d184ba677110d14f71e25ef16299"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a5141d184ba677110d14f71e25ef16299">REG_GCLK_GENCTRL5</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C34UL)</td></tr>
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<tr class="memdesc:a5141d184ba677110d14f71e25ef16299"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Generic Clock Generator Control 5 <br /></td></tr>
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<tr class="separator:a5141d184ba677110d14f71e25ef16299"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0e8fbb6cc2c27931dbe1e8616e24d3b3"><td class="memItemLeft" align="right" valign="top"><a id="a0e8fbb6cc2c27931dbe1e8616e24d3b3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a0e8fbb6cc2c27931dbe1e8616e24d3b3">REG_GCLK_GENCTRL6</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C38UL)</td></tr>
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<tr class="memdesc:a0e8fbb6cc2c27931dbe1e8616e24d3b3"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Generic Clock Generator Control 6 <br /></td></tr>
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<tr class="separator:a0e8fbb6cc2c27931dbe1e8616e24d3b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a35107e472bd3c74f83309431fe709d16"><td class="memItemLeft" align="right" valign="top"><a id="a35107e472bd3c74f83309431fe709d16"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a35107e472bd3c74f83309431fe709d16">REG_GCLK_GENCTRL7</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C3CUL)</td></tr>
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<tr class="memdesc:a35107e472bd3c74f83309431fe709d16"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Generic Clock Generator Control 7 <br /></td></tr>
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<tr class="separator:a35107e472bd3c74f83309431fe709d16"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af40fdcc1355dd2308781309d704da2c4"><td class="memItemLeft" align="right" valign="top"><a id="af40fdcc1355dd2308781309d704da2c4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#af40fdcc1355dd2308781309d704da2c4">REG_GCLK_GENCTRL8</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C40UL)</td></tr>
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<tr class="memdesc:af40fdcc1355dd2308781309d704da2c4"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Generic Clock Generator Control 8 <br /></td></tr>
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<tr class="separator:af40fdcc1355dd2308781309d704da2c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a15b366d4d6d8b63328066824a2ceafec"><td class="memItemLeft" align="right" valign="top"><a id="a15b366d4d6d8b63328066824a2ceafec"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a15b366d4d6d8b63328066824a2ceafec">REG_GCLK_GENCTRL9</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C44UL)</td></tr>
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<tr class="memdesc:a15b366d4d6d8b63328066824a2ceafec"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Generic Clock Generator Control 9 <br /></td></tr>
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<tr class="separator:a15b366d4d6d8b63328066824a2ceafec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad6448160aa13502d2b397cd90635e097"><td class="memItemLeft" align="right" valign="top"><a id="ad6448160aa13502d2b397cd90635e097"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#ad6448160aa13502d2b397cd90635e097">REG_GCLK_GENCTRL10</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C48UL)</td></tr>
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<tr class="memdesc:ad6448160aa13502d2b397cd90635e097"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Generic Clock Generator Control 10 <br /></td></tr>
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<tr class="separator:ad6448160aa13502d2b397cd90635e097"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa7600f9958b0aaef42b908a19cac80e7"><td class="memItemLeft" align="right" valign="top"><a id="aa7600f9958b0aaef42b908a19cac80e7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aa7600f9958b0aaef42b908a19cac80e7">REG_GCLK_GENCTRL11</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C4CUL)</td></tr>
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<tr class="memdesc:aa7600f9958b0aaef42b908a19cac80e7"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Generic Clock Generator Control 11 <br /></td></tr>
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<tr class="separator:aa7600f9958b0aaef42b908a19cac80e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a58895086e0b84dfc78840ebfdc30da6a"><td class="memItemLeft" align="right" valign="top"><a id="a58895086e0b84dfc78840ebfdc30da6a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a58895086e0b84dfc78840ebfdc30da6a">REG_GCLK_PCHCTRL0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C80UL)</td></tr>
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<tr class="memdesc:a58895086e0b84dfc78840ebfdc30da6a"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 0 <br /></td></tr>
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<tr class="separator:a58895086e0b84dfc78840ebfdc30da6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad8f8fb8af22562a833d585b8fbc27ede"><td class="memItemLeft" align="right" valign="top"><a id="ad8f8fb8af22562a833d585b8fbc27ede"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#ad8f8fb8af22562a833d585b8fbc27ede">REG_GCLK_PCHCTRL1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C84UL)</td></tr>
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<tr class="memdesc:ad8f8fb8af22562a833d585b8fbc27ede"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 1 <br /></td></tr>
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<tr class="separator:ad8f8fb8af22562a833d585b8fbc27ede"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a013dbb8ad928386ddc3ddecfe8e04d56"><td class="memItemLeft" align="right" valign="top"><a id="a013dbb8ad928386ddc3ddecfe8e04d56"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a013dbb8ad928386ddc3ddecfe8e04d56">REG_GCLK_PCHCTRL2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C88UL)</td></tr>
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<tr class="memdesc:a013dbb8ad928386ddc3ddecfe8e04d56"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 2 <br /></td></tr>
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<tr class="separator:a013dbb8ad928386ddc3ddecfe8e04d56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a26b8085f82bb521d848204b4dfbd6274"><td class="memItemLeft" align="right" valign="top"><a id="a26b8085f82bb521d848204b4dfbd6274"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a26b8085f82bb521d848204b4dfbd6274">REG_GCLK_PCHCTRL3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C8CUL)</td></tr>
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<tr class="memdesc:a26b8085f82bb521d848204b4dfbd6274"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 3 <br /></td></tr>
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<tr class="separator:a26b8085f82bb521d848204b4dfbd6274"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3e8445c5d18a4c8aaaae5e5b3adf42c4"><td class="memItemLeft" align="right" valign="top"><a id="a3e8445c5d18a4c8aaaae5e5b3adf42c4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a3e8445c5d18a4c8aaaae5e5b3adf42c4">REG_GCLK_PCHCTRL4</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C90UL)</td></tr>
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<tr class="memdesc:a3e8445c5d18a4c8aaaae5e5b3adf42c4"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 4 <br /></td></tr>
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<tr class="separator:a3e8445c5d18a4c8aaaae5e5b3adf42c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa7d29690fa4d2fa847dc7a0d13068288"><td class="memItemLeft" align="right" valign="top"><a id="aa7d29690fa4d2fa847dc7a0d13068288"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aa7d29690fa4d2fa847dc7a0d13068288">REG_GCLK_PCHCTRL5</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C94UL)</td></tr>
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<tr class="memdesc:aa7d29690fa4d2fa847dc7a0d13068288"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 5 <br /></td></tr>
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<tr class="separator:aa7d29690fa4d2fa847dc7a0d13068288"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeb3d53736271cb7fb71e082289106c29"><td class="memItemLeft" align="right" valign="top"><a id="aeb3d53736271cb7fb71e082289106c29"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aeb3d53736271cb7fb71e082289106c29">REG_GCLK_PCHCTRL6</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C98UL)</td></tr>
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<tr class="memdesc:aeb3d53736271cb7fb71e082289106c29"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 6 <br /></td></tr>
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<tr class="separator:aeb3d53736271cb7fb71e082289106c29"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8177a0843f0d5642ad35bb00b10ab3ba"><td class="memItemLeft" align="right" valign="top"><a id="a8177a0843f0d5642ad35bb00b10ab3ba"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a8177a0843f0d5642ad35bb00b10ab3ba">REG_GCLK_PCHCTRL7</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001C9CUL)</td></tr>
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<tr class="memdesc:a8177a0843f0d5642ad35bb00b10ab3ba"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 7 <br /></td></tr>
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<tr class="separator:a8177a0843f0d5642ad35bb00b10ab3ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac9af071c06faf2fa23245ecf5124ca9b"><td class="memItemLeft" align="right" valign="top"><a id="ac9af071c06faf2fa23245ecf5124ca9b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#ac9af071c06faf2fa23245ecf5124ca9b">REG_GCLK_PCHCTRL8</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CA0UL)</td></tr>
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<tr class="memdesc:ac9af071c06faf2fa23245ecf5124ca9b"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 8 <br /></td></tr>
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<tr class="separator:ac9af071c06faf2fa23245ecf5124ca9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa5aa7f7a4080f237572e378d5474c160"><td class="memItemLeft" align="right" valign="top"><a id="aa5aa7f7a4080f237572e378d5474c160"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aa5aa7f7a4080f237572e378d5474c160">REG_GCLK_PCHCTRL9</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CA4UL)</td></tr>
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<tr class="memdesc:aa5aa7f7a4080f237572e378d5474c160"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 9 <br /></td></tr>
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<tr class="separator:aa5aa7f7a4080f237572e378d5474c160"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad6ab9c73b7ae7e8194fde27f5e4007c5"><td class="memItemLeft" align="right" valign="top"><a id="ad6ab9c73b7ae7e8194fde27f5e4007c5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#ad6ab9c73b7ae7e8194fde27f5e4007c5">REG_GCLK_PCHCTRL10</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CA8UL)</td></tr>
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<tr class="memdesc:ad6ab9c73b7ae7e8194fde27f5e4007c5"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 10 <br /></td></tr>
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<tr class="separator:ad6ab9c73b7ae7e8194fde27f5e4007c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac84db93a1a6c1298b3fdd2f3e93ee29d"><td class="memItemLeft" align="right" valign="top"><a id="ac84db93a1a6c1298b3fdd2f3e93ee29d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#ac84db93a1a6c1298b3fdd2f3e93ee29d">REG_GCLK_PCHCTRL11</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CACUL)</td></tr>
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<tr class="memdesc:ac84db93a1a6c1298b3fdd2f3e93ee29d"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 11 <br /></td></tr>
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<tr class="separator:ac84db93a1a6c1298b3fdd2f3e93ee29d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aafc09510ccab672e86927352b0cb83ea"><td class="memItemLeft" align="right" valign="top"><a id="aafc09510ccab672e86927352b0cb83ea"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aafc09510ccab672e86927352b0cb83ea">REG_GCLK_PCHCTRL12</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CB0UL)</td></tr>
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<tr class="memdesc:aafc09510ccab672e86927352b0cb83ea"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 12 <br /></td></tr>
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<tr class="separator:aafc09510ccab672e86927352b0cb83ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1b5a9c8069da10ad29ba4b412f3b3c2a"><td class="memItemLeft" align="right" valign="top"><a id="a1b5a9c8069da10ad29ba4b412f3b3c2a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a1b5a9c8069da10ad29ba4b412f3b3c2a">REG_GCLK_PCHCTRL13</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CB4UL)</td></tr>
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<tr class="memdesc:a1b5a9c8069da10ad29ba4b412f3b3c2a"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 13 <br /></td></tr>
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<tr class="separator:a1b5a9c8069da10ad29ba4b412f3b3c2a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aed544e3afe62f3965f5e7b5561e98fde"><td class="memItemLeft" align="right" valign="top"><a id="aed544e3afe62f3965f5e7b5561e98fde"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aed544e3afe62f3965f5e7b5561e98fde">REG_GCLK_PCHCTRL14</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CB8UL)</td></tr>
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<tr class="memdesc:aed544e3afe62f3965f5e7b5561e98fde"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 14 <br /></td></tr>
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<tr class="separator:aed544e3afe62f3965f5e7b5561e98fde"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6dfaf3392e69e07202c3fef193fed9bd"><td class="memItemLeft" align="right" valign="top"><a id="a6dfaf3392e69e07202c3fef193fed9bd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a6dfaf3392e69e07202c3fef193fed9bd">REG_GCLK_PCHCTRL15</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CBCUL)</td></tr>
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<tr class="memdesc:a6dfaf3392e69e07202c3fef193fed9bd"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 15 <br /></td></tr>
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<tr class="separator:a6dfaf3392e69e07202c3fef193fed9bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7f6d7828383e5a6037bdce5279f80386"><td class="memItemLeft" align="right" valign="top"><a id="a7f6d7828383e5a6037bdce5279f80386"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a7f6d7828383e5a6037bdce5279f80386">REG_GCLK_PCHCTRL16</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CC0UL)</td></tr>
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<tr class="memdesc:a7f6d7828383e5a6037bdce5279f80386"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 16 <br /></td></tr>
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<tr class="separator:a7f6d7828383e5a6037bdce5279f80386"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3fbfbf28be0bfbca42cbf941965caa0b"><td class="memItemLeft" align="right" valign="top"><a id="a3fbfbf28be0bfbca42cbf941965caa0b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a3fbfbf28be0bfbca42cbf941965caa0b">REG_GCLK_PCHCTRL17</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CC4UL)</td></tr>
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<tr class="memdesc:a3fbfbf28be0bfbca42cbf941965caa0b"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 17 <br /></td></tr>
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<tr class="separator:a3fbfbf28be0bfbca42cbf941965caa0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7f5c46c305f770a1dd8015a25be1958e"><td class="memItemLeft" align="right" valign="top"><a id="a7f5c46c305f770a1dd8015a25be1958e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a7f5c46c305f770a1dd8015a25be1958e">REG_GCLK_PCHCTRL18</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CC8UL)</td></tr>
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<tr class="memdesc:a7f5c46c305f770a1dd8015a25be1958e"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 18 <br /></td></tr>
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<tr class="separator:a7f5c46c305f770a1dd8015a25be1958e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aca16b236929e87900de1099c5912f366"><td class="memItemLeft" align="right" valign="top"><a id="aca16b236929e87900de1099c5912f366"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aca16b236929e87900de1099c5912f366">REG_GCLK_PCHCTRL19</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CCCUL)</td></tr>
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<tr class="memdesc:aca16b236929e87900de1099c5912f366"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 19 <br /></td></tr>
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<tr class="separator:aca16b236929e87900de1099c5912f366"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a249d05c3eed9a920337e75b875c73e1a"><td class="memItemLeft" align="right" valign="top"><a id="a249d05c3eed9a920337e75b875c73e1a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a249d05c3eed9a920337e75b875c73e1a">REG_GCLK_PCHCTRL20</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CD0UL)</td></tr>
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<tr class="memdesc:a249d05c3eed9a920337e75b875c73e1a"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 20 <br /></td></tr>
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<tr class="separator:a249d05c3eed9a920337e75b875c73e1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7c36c0c7e052503bbcd0a05093d4b6c1"><td class="memItemLeft" align="right" valign="top"><a id="a7c36c0c7e052503bbcd0a05093d4b6c1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a7c36c0c7e052503bbcd0a05093d4b6c1">REG_GCLK_PCHCTRL21</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CD4UL)</td></tr>
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<tr class="memdesc:a7c36c0c7e052503bbcd0a05093d4b6c1"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 21 <br /></td></tr>
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<tr class="separator:a7c36c0c7e052503bbcd0a05093d4b6c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1b7aa108f4136e624bc8890dff130b6b"><td class="memItemLeft" align="right" valign="top"><a id="a1b7aa108f4136e624bc8890dff130b6b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a1b7aa108f4136e624bc8890dff130b6b">REG_GCLK_PCHCTRL22</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CD8UL)</td></tr>
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<tr class="memdesc:a1b7aa108f4136e624bc8890dff130b6b"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 22 <br /></td></tr>
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<tr class="separator:a1b7aa108f4136e624bc8890dff130b6b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7cef6610d6e8c92e454b3f6e5f68e2ea"><td class="memItemLeft" align="right" valign="top"><a id="a7cef6610d6e8c92e454b3f6e5f68e2ea"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a7cef6610d6e8c92e454b3f6e5f68e2ea">REG_GCLK_PCHCTRL23</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CDCUL)</td></tr>
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<tr class="memdesc:a7cef6610d6e8c92e454b3f6e5f68e2ea"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 23 <br /></td></tr>
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<tr class="separator:a7cef6610d6e8c92e454b3f6e5f68e2ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aac7cd80a6b247992d7078f072c3e1f19"><td class="memItemLeft" align="right" valign="top"><a id="aac7cd80a6b247992d7078f072c3e1f19"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aac7cd80a6b247992d7078f072c3e1f19">REG_GCLK_PCHCTRL24</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CE0UL)</td></tr>
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<tr class="memdesc:aac7cd80a6b247992d7078f072c3e1f19"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 24 <br /></td></tr>
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<tr class="separator:aac7cd80a6b247992d7078f072c3e1f19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab59d4364e257d7ff86627a3ea07a5300"><td class="memItemLeft" align="right" valign="top"><a id="ab59d4364e257d7ff86627a3ea07a5300"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#ab59d4364e257d7ff86627a3ea07a5300">REG_GCLK_PCHCTRL25</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CE4UL)</td></tr>
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<tr class="memdesc:ab59d4364e257d7ff86627a3ea07a5300"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 25 <br /></td></tr>
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<tr class="separator:ab59d4364e257d7ff86627a3ea07a5300"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a153a610d59ecefea456e4adcfca00083"><td class="memItemLeft" align="right" valign="top"><a id="a153a610d59ecefea456e4adcfca00083"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a153a610d59ecefea456e4adcfca00083">REG_GCLK_PCHCTRL26</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CE8UL)</td></tr>
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<tr class="memdesc:a153a610d59ecefea456e4adcfca00083"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 26 <br /></td></tr>
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<tr class="separator:a153a610d59ecefea456e4adcfca00083"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa172f895e20d15e584815f7ccc20957e"><td class="memItemLeft" align="right" valign="top"><a id="aa172f895e20d15e584815f7ccc20957e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aa172f895e20d15e584815f7ccc20957e">REG_GCLK_PCHCTRL27</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CECUL)</td></tr>
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<tr class="memdesc:aa172f895e20d15e584815f7ccc20957e"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 27 <br /></td></tr>
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<tr class="separator:aa172f895e20d15e584815f7ccc20957e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad3a02a7b3e794861b32d06ba3118af6"><td class="memItemLeft" align="right" valign="top"><a id="aad3a02a7b3e794861b32d06ba3118af6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aad3a02a7b3e794861b32d06ba3118af6">REG_GCLK_PCHCTRL28</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CF0UL)</td></tr>
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<tr class="memdesc:aad3a02a7b3e794861b32d06ba3118af6"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 28 <br /></td></tr>
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<tr class="separator:aad3a02a7b3e794861b32d06ba3118af6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa1277f923c4300cf7c408bd30dca8a56"><td class="memItemLeft" align="right" valign="top"><a id="aa1277f923c4300cf7c408bd30dca8a56"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aa1277f923c4300cf7c408bd30dca8a56">REG_GCLK_PCHCTRL29</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CF4UL)</td></tr>
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<tr class="memdesc:aa1277f923c4300cf7c408bd30dca8a56"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 29 <br /></td></tr>
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<tr class="separator:aa1277f923c4300cf7c408bd30dca8a56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:add7b8311064bcb9ba1aab2c687b7727e"><td class="memItemLeft" align="right" valign="top"><a id="add7b8311064bcb9ba1aab2c687b7727e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#add7b8311064bcb9ba1aab2c687b7727e">REG_GCLK_PCHCTRL30</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CF8UL)</td></tr>
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<tr class="memdesc:add7b8311064bcb9ba1aab2c687b7727e"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 30 <br /></td></tr>
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<tr class="separator:add7b8311064bcb9ba1aab2c687b7727e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeccc0556009c0c86b4aa767400bef8f9"><td class="memItemLeft" align="right" valign="top"><a id="aeccc0556009c0c86b4aa767400bef8f9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aeccc0556009c0c86b4aa767400bef8f9">REG_GCLK_PCHCTRL31</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001CFCUL)</td></tr>
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<tr class="memdesc:aeccc0556009c0c86b4aa767400bef8f9"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 31 <br /></td></tr>
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<tr class="separator:aeccc0556009c0c86b4aa767400bef8f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab94e84e6668b16780098619f7bfe8c12"><td class="memItemLeft" align="right" valign="top"><a id="ab94e84e6668b16780098619f7bfe8c12"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#ab94e84e6668b16780098619f7bfe8c12">REG_GCLK_PCHCTRL32</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D00UL)</td></tr>
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<tr class="memdesc:ab94e84e6668b16780098619f7bfe8c12"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 32 <br /></td></tr>
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<tr class="separator:ab94e84e6668b16780098619f7bfe8c12"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a45b1d2b16810bb3bc2443ba1b5011df0"><td class="memItemLeft" align="right" valign="top"><a id="a45b1d2b16810bb3bc2443ba1b5011df0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a45b1d2b16810bb3bc2443ba1b5011df0">REG_GCLK_PCHCTRL33</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D04UL)</td></tr>
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<tr class="memdesc:a45b1d2b16810bb3bc2443ba1b5011df0"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 33 <br /></td></tr>
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<tr class="separator:a45b1d2b16810bb3bc2443ba1b5011df0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a00b210d7de292f88fb37c32631916126"><td class="memItemLeft" align="right" valign="top"><a id="a00b210d7de292f88fb37c32631916126"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a00b210d7de292f88fb37c32631916126">REG_GCLK_PCHCTRL34</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D08UL)</td></tr>
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<tr class="memdesc:a00b210d7de292f88fb37c32631916126"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 34 <br /></td></tr>
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<tr class="separator:a00b210d7de292f88fb37c32631916126"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac9a661ea428d1143e6c0f72fedcaf9c8"><td class="memItemLeft" align="right" valign="top"><a id="ac9a661ea428d1143e6c0f72fedcaf9c8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#ac9a661ea428d1143e6c0f72fedcaf9c8">REG_GCLK_PCHCTRL35</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D0CUL)</td></tr>
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<tr class="memdesc:ac9a661ea428d1143e6c0f72fedcaf9c8"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 35 <br /></td></tr>
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<tr class="separator:ac9a661ea428d1143e6c0f72fedcaf9c8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aef9058aa47b4331e5fab9c2056608064"><td class="memItemLeft" align="right" valign="top"><a id="aef9058aa47b4331e5fab9c2056608064"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#aef9058aa47b4331e5fab9c2056608064">REG_GCLK_PCHCTRL36</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D10UL)</td></tr>
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<tr class="memdesc:aef9058aa47b4331e5fab9c2056608064"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 36 <br /></td></tr>
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<tr class="separator:aef9058aa47b4331e5fab9c2056608064"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5088d24bdef0dc00dcd89d54c30dcdf0"><td class="memItemLeft" align="right" valign="top"><a id="a5088d24bdef0dc00dcd89d54c30dcdf0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a5088d24bdef0dc00dcd89d54c30dcdf0">REG_GCLK_PCHCTRL37</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D14UL)</td></tr>
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<tr class="memdesc:a5088d24bdef0dc00dcd89d54c30dcdf0"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 37 <br /></td></tr>
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<tr class="separator:a5088d24bdef0dc00dcd89d54c30dcdf0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2dfeebb763aa3702ff62d58400e67ea1"><td class="memItemLeft" align="right" valign="top"><a id="a2dfeebb763aa3702ff62d58400e67ea1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a2dfeebb763aa3702ff62d58400e67ea1">REG_GCLK_PCHCTRL38</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D18UL)</td></tr>
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<tr class="memdesc:a2dfeebb763aa3702ff62d58400e67ea1"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 38 <br /></td></tr>
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<tr class="separator:a2dfeebb763aa3702ff62d58400e67ea1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8cbc817d0608167a72e212c7dca8817f"><td class="memItemLeft" align="right" valign="top"><a id="a8cbc817d0608167a72e212c7dca8817f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a8cbc817d0608167a72e212c7dca8817f">REG_GCLK_PCHCTRL39</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D1CUL)</td></tr>
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<tr class="memdesc:a8cbc817d0608167a72e212c7dca8817f"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 39 <br /></td></tr>
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<tr class="separator:a8cbc817d0608167a72e212c7dca8817f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a55f8c47ea7fce982366e539237ba479e"><td class="memItemLeft" align="right" valign="top"><a id="a55f8c47ea7fce982366e539237ba479e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a55f8c47ea7fce982366e539237ba479e">REG_GCLK_PCHCTRL40</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D20UL)</td></tr>
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<tr class="memdesc:a55f8c47ea7fce982366e539237ba479e"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 40 <br /></td></tr>
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<tr class="separator:a55f8c47ea7fce982366e539237ba479e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4406939d57e953f681f0c11f4024bad4"><td class="memItemLeft" align="right" valign="top"><a id="a4406939d57e953f681f0c11f4024bad4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a4406939d57e953f681f0c11f4024bad4">REG_GCLK_PCHCTRL41</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D24UL)</td></tr>
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<tr class="memdesc:a4406939d57e953f681f0c11f4024bad4"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 41 <br /></td></tr>
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<tr class="separator:a4406939d57e953f681f0c11f4024bad4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a83fb4bdda5c122870f8062a211a503ca"><td class="memItemLeft" align="right" valign="top"><a id="a83fb4bdda5c122870f8062a211a503ca"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a83fb4bdda5c122870f8062a211a503ca">REG_GCLK_PCHCTRL42</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D28UL)</td></tr>
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<tr class="memdesc:a83fb4bdda5c122870f8062a211a503ca"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 42 <br /></td></tr>
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<tr class="separator:a83fb4bdda5c122870f8062a211a503ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a89ec0f111d6dd1608a2bf8e45d2b1aff"><td class="memItemLeft" align="right" valign="top"><a id="a89ec0f111d6dd1608a2bf8e45d2b1aff"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a89ec0f111d6dd1608a2bf8e45d2b1aff">REG_GCLK_PCHCTRL43</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D2CUL)</td></tr>
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<tr class="memdesc:a89ec0f111d6dd1608a2bf8e45d2b1aff"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 43 <br /></td></tr>
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<tr class="separator:a89ec0f111d6dd1608a2bf8e45d2b1aff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acdbbd5291365d7efbb3df6a6e7f173dd"><td class="memItemLeft" align="right" valign="top"><a id="acdbbd5291365d7efbb3df6a6e7f173dd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#acdbbd5291365d7efbb3df6a6e7f173dd">REG_GCLK_PCHCTRL44</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D30UL)</td></tr>
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<tr class="memdesc:acdbbd5291365d7efbb3df6a6e7f173dd"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 44 <br /></td></tr>
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<tr class="separator:acdbbd5291365d7efbb3df6a6e7f173dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae00715edc161d18d8b11f202e6580b80"><td class="memItemLeft" align="right" valign="top"><a id="ae00715edc161d18d8b11f202e6580b80"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#ae00715edc161d18d8b11f202e6580b80">REG_GCLK_PCHCTRL45</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D34UL)</td></tr>
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<tr class="memdesc:ae00715edc161d18d8b11f202e6580b80"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 45 <br /></td></tr>
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<tr class="separator:ae00715edc161d18d8b11f202e6580b80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8c8938c6e57db7fa7932998d5180b262"><td class="memItemLeft" align="right" valign="top"><a id="a8c8938c6e57db7fa7932998d5180b262"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a8c8938c6e57db7fa7932998d5180b262">REG_GCLK_PCHCTRL46</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D38UL)</td></tr>
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<tr class="memdesc:a8c8938c6e57db7fa7932998d5180b262"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 46 <br /></td></tr>
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<tr class="separator:a8c8938c6e57db7fa7932998d5180b262"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8413bf2e2efc126327faba9f749780a5"><td class="memItemLeft" align="right" valign="top"><a id="a8413bf2e2efc126327faba9f749780a5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2gclk_8h.html#a8413bf2e2efc126327faba9f749780a5">REG_GCLK_PCHCTRL47</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001D3CUL)</td></tr>
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<tr class="memdesc:a8413bf2e2efc126327faba9f749780a5"><td class="mdescLeft"> </td><td class="mdescRight">(GCLK) Peripheral Clock Control 47 <br /></td></tr>
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<tr class="separator:a8413bf2e2efc126327faba9f749780a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a823f51a02b33f27a12e7697284b6a55e"><td class="memItemLeft" align="right" valign="top"><a id="a823f51a02b33f27a12e7697284b6a55e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_GENCTRL0_RESETVALUE</b>   106</td></tr>
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<tr class="separator:a823f51a02b33f27a12e7697284b6a55e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abe0bef715864f25137d2c90728bbec50"><td class="memItemLeft" align="right" valign="top"><a id="abe0bef715864f25137d2c90728bbec50"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_GENDIV_BITS</b>   16</td></tr>
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<tr class="separator:abe0bef715864f25137d2c90728bbec50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5d29a525b55e60b4c0776a0de403cca6"><td class="memItemLeft" align="right" valign="top"><a id="a5d29a525b55e60b4c0776a0de403cca6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_GEN_BITS</b>   4</td></tr>
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<tr class="separator:a5d29a525b55e60b4c0776a0de403cca6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0b06f5ff2a5d83514fa57c1718ea8ee3"><td class="memItemLeft" align="right" valign="top"><a id="a0b06f5ff2a5d83514fa57c1718ea8ee3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_GEN_NUM</b>   12</td></tr>
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<tr class="separator:a0b06f5ff2a5d83514fa57c1718ea8ee3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a628ac1eca0aa71f6f484ed0dd5c4d6ef"><td class="memItemLeft" align="right" valign="top"><a id="a628ac1eca0aa71f6f484ed0dd5c4d6ef"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_GEN_NUM_MSB</b>   11</td></tr>
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<tr class="separator:a628ac1eca0aa71f6f484ed0dd5c4d6ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a37414154a97fceb345f32429046460e4"><td class="memItemLeft" align="right" valign="top"><a id="a37414154a97fceb345f32429046460e4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_GEN_SOURCE_NUM_MSB</b>   8</td></tr>
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<tr class="separator:a37414154a97fceb345f32429046460e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac98086ea52badd1ec5bf9d5ff99463eb"><td class="memItemLeft" align="right" valign="top"><a id="ac98086ea52badd1ec5bf9d5ff99463eb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_IO_NUM</b>   8</td></tr>
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<tr class="separator:ac98086ea52badd1ec5bf9d5ff99463eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abedb2fdf1c8a3f1fa0c29b6821bbfe9b"><td class="memItemLeft" align="right" valign="top"><a id="abedb2fdf1c8a3f1fa0c29b6821bbfe9b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_NUM</b>   48</td></tr>
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<tr class="separator:abedb2fdf1c8a3f1fa0c29b6821bbfe9b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aded12c413f1c532ae8c5bb8f7fa0993a"><td class="memItemLeft" align="right" valign="top"><a id="aded12c413f1c532ae8c5bb8f7fa0993a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_BITS</b>   4</td></tr>
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<tr class="memitem:afac26abc82da9089a0a40f81a4df0a7a"><td class="memItemLeft" align="right" valign="top"><a id="afac26abc82da9089a0a40f81a4df0a7a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_NUM</b>   9</td></tr>
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<tr class="memitem:a17e95ceb9221624d6ebe62bac342c274"><td class="memItemLeft" align="right" valign="top"><a id="a17e95ceb9221624d6ebe62bac342c274"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_XOSC0</b>   0</td></tr>
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<tr class="separator:a17e95ceb9221624d6ebe62bac342c274"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a407d7d7a2f371d5ed902940844ff1c1c"><td class="memItemLeft" align="right" valign="top"><a id="a407d7d7a2f371d5ed902940844ff1c1c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_XOSC</b>   0</td></tr>
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<tr class="memitem:a8111a8d021f938a638308937dd59e7db"><td class="memItemLeft" align="right" valign="top"><a id="a8111a8d021f938a638308937dd59e7db"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_XOSC1</b>   1</td></tr>
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<tr class="memitem:afae6d03225488001be006685ee011199"><td class="memItemLeft" align="right" valign="top"><a id="afae6d03225488001be006685ee011199"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_GCLKIN</b>   2</td></tr>
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<tr class="memitem:a0b8a49009d0b7755d7f016230aef5ffd"><td class="memItemLeft" align="right" valign="top"><a id="a0b8a49009d0b7755d7f016230aef5ffd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_GCLKGEN1</b>   3</td></tr>
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<tr class="memitem:a8df6754191b0e03fbf71165e2b20745a"><td class="memItemLeft" align="right" valign="top"><a id="a8df6754191b0e03fbf71165e2b20745a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_OSCULP32K</b>   4</td></tr>
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<tr class="memitem:aab432e69ee26643b3fbbcc25044d3a31"><td class="memItemLeft" align="right" valign="top"><a id="aab432e69ee26643b3fbbcc25044d3a31"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_XOSC32K</b>   5</td></tr>
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<tr class="memitem:a24525cc47db8f2d1d496b8b6643372cc"><td class="memItemLeft" align="right" valign="top"><a id="a24525cc47db8f2d1d496b8b6643372cc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_DFLL</b>   6</td></tr>
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<tr class="separator:a24525cc47db8f2d1d496b8b6643372cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af07175067558a9134a1054c894dd0acb"><td class="memItemLeft" align="right" valign="top"><a id="af07175067558a9134a1054c894dd0acb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_DFLL48M</b>   6</td></tr>
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<tr class="memitem:a215315eced9aeae532d02decfd350cc6"><td class="memItemLeft" align="right" valign="top"><a id="a215315eced9aeae532d02decfd350cc6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_OSC16M</b>   6</td></tr>
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<tr class="memitem:a0789ff576adb1223db886febd459ba7e"><td class="memItemLeft" align="right" valign="top"><a id="a0789ff576adb1223db886febd459ba7e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_OSC48M</b>   6</td></tr>
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<tr class="memitem:afb84cf5b41af20767cb6d7e6bd9230c0"><td class="memItemLeft" align="right" valign="top"><a id="afb84cf5b41af20767cb6d7e6bd9230c0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_DPLL0</b>   7</td></tr>
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<tr class="memitem:adf04ad702d4782c4f23796628b807092"><td class="memItemLeft" align="right" valign="top"><a id="adf04ad702d4782c4f23796628b807092"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_FDPLL</b>   7</td></tr>
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<tr class="memitem:a6e0b7b7d70f0837f0f94b91cb245df72"><td class="memItemLeft" align="right" valign="top"><a id="a6e0b7b7d70f0837f0f94b91cb245df72"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_FDPLL0</b>   7</td></tr>
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<tr class="separator:a6e0b7b7d70f0837f0f94b91cb245df72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1e4b971d729fcc0011339058231abf4b"><td class="memItemLeft" align="right" valign="top"><a id="a1e4b971d729fcc0011339058231abf4b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_DPLL1</b>   8</td></tr>
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<tr class="separator:a1e4b971d729fcc0011339058231abf4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9f46faaca561767d8f34dd256421ebd8"><td class="memItemLeft" align="right" valign="top"><a id="a9f46faaca561767d8f34dd256421ebd8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_SOURCE_FDPLL1</b>   8</td></tr>
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<tr class="memitem:a024ad7c37d7c897d1c74159ee336e0e6"><td class="memItemLeft" align="right" valign="top"><a id="a024ad7c37d7c897d1c74159ee336e0e6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>GCLK_GEN_DIV_BITS</b>   { 8, 16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8 }</td></tr>
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<tr class="separator:a024ad7c37d7c897d1c74159ee336e0e6"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for GCLK. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="instance_2gclk_8h_source.html">gclk.h</a>.</p>
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