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<div id="projectname">SAME54P20A Test Project
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">DmacDescriptor Struct Reference</div> </div>
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<div class="contents">
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<p>DMAC Descriptor SRAM registers.
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<a href="structDmacDescriptor.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="component_2dmac_8h_source.html">dmac.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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__IO <a class="el" href="unionDMAC__BTCTRL__Type.html">DMAC_BTCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacDescriptor.html#aca9f4ae141c62ca7afd5d2d37d40cf97">BTCTRL</a></td></tr>
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<tr class="memdesc:aca9f4ae141c62ca7afd5d2d37d40cf97"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 16) Block Transfer Control. <br /></td></tr>
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__IO <a class="el" href="unionDMAC__BTCNT__Type.html">DMAC_BTCNT_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacDescriptor.html#a0780167b50b7fdad01385ac59d932fe0">BTCNT</a></td></tr>
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<tr class="memdesc:a0780167b50b7fdad01385ac59d932fe0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02 (R/W 16) Block Transfer Count. <br /></td></tr>
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__IO <a class="el" href="unionDMAC__SRCADDR__Type.html">DMAC_SRCADDR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacDescriptor.html#a559459039dd1742d2b017cfee0aa42c6">SRCADDR</a></td></tr>
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<tr class="memdesc:a559459039dd1742d2b017cfee0aa42c6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 32) Block Transfer Source Address. <br /></td></tr>
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__IO <a class="el" href="unionDMAC__DSTADDR__Type.html">DMAC_DSTADDR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacDescriptor.html#a2d8c99d8e4c69a7034e16332f47331de">DSTADDR</a></td></tr>
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<tr class="memdesc:a2d8c99d8e4c69a7034e16332f47331de"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 32) Block Transfer Destination Address. <br /></td></tr>
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__IO <a class="el" href="unionDMAC__DESCADDR__Type.html">DMAC_DESCADDR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacDescriptor.html#a9eaae816f207483de696dce90bfdb585">DESCADDR</a></td></tr>
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<tr class="memdesc:a9eaae816f207483de696dce90bfdb585"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 32) Next Descriptor Address. <br /></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>DMAC Descriptor SRAM registers. </p>
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<p class="definition">Definition at line <a class="el" href="component_2dmac_8h_source.html#l01395">1395</a> of file <a class="el" href="component_2dmac_8h_source.html">dmac.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2dmac_8h_source.html">dmac.h</a></li>
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