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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<p class="definition">Definition at line <a class="el" href="component_2qspi_8h_source.html#l00244">244</a> of file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#adf341d62c5de3bde684a1528db190968">&#9670;&nbsp;</a></span>__pad0__</h2>
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<p>bit: 4.. 7 Reserved <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2qspi_8h_source.html#l00250">250</a> of file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a99da191d9555483e5758bfa14e79c287">&#9670;&nbsp;</a></span>__pad1__</h2>
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<p>bit: 9 Reserved <br />
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<p class="definition">Definition at line <a class="el" href="component_2qspi_8h_source.html#l00252">252</a> of file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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<p>bit: 11..31 Reserved <br />
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<p class="definition">Definition at line <a class="el" href="component_2qspi_8h_source.html#l00254">254</a> of file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#ad45e1b3abdbfe6130f116aaefbc81428">&#9670;&nbsp;</a></span>bit</h2>
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<p>Structure used for bit access <br />
</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a54e6cfe0fded456c1f115964c22ee5a4">&#9670;&nbsp;</a></span>CSRISE</h2>
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<p>bit: 8 Chip Select Rise Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2qspi_8h_source.html#l00251">251</a> of file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#abfad9d948c90044fcaf367e3499301a1">&#9670;&nbsp;</a></span>DRE</h2>
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<p>bit: 1 Transmit Data Register Empty Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2qspi_8h_source.html#l00247">247</a> of file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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<p>bit: 3 Overrun Error Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2qspi_8h_source.html#l00249">249</a> of file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#ad00a5f3343ee143b50a8000c879ca109">&#9670;&nbsp;</a></span>INSTREND</h2>
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<p>bit: 10 Instruction End Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2qspi_8h_source.html#l00253">253</a> of file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a3eb8216a8ed325db6a6c8a748150717a">&#9670;&nbsp;</a></span>reg</h2>
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<p>Type used for register access <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2qspi_8h_source.html#l00256">256</a> of file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a7a0e65ab51f1e2a81aea30ba5773900a">&#9670;&nbsp;</a></span>RXC</h2>
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<p>bit: 0 Receive Data Register Full Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2qspi_8h_source.html#l00246">246</a> of file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a1ecfd772eb0b7fd8b56745bde327edee">&#9670;&nbsp;</a></span>TXC</h2>
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<p>bit: 2 Transmission Complete Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2qspi_8h_source.html#l00248">248</a> of file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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<hr/>The documentation for this union was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2qspi_8h_source.html">qspi.h</a></li>
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