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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock">
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00152">152</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
</div><h2 class="groupheader">Field Documentation</h2>
<a id="af8b72bb54ebdf76e8091d0dbe92f6d57"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af8b72bb54ebdf76e8091d0dbe92f6d57">&#9670;&nbsp;</a></span>__pad0__</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::__pad0__</td>
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<p>bit: 4.. 7 Reserved <br />
</p>
<p>bit: 4..31 Reserved <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00158">158</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a8b1ea4bd84affe2c834cf4534dd26238">&#9670;&nbsp;</a></span>__pad1__</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::__pad1__</td>
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<p>bit: 13..15 Reserved <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00164">164</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a4ef9460939c6832a603b60d66e67e864">&#9670;&nbsp;</a></span>__pad2__</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::__pad2__</td>
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<p>bit: 20..23 Reserved <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00169">169</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<p>bit: 28..31 Reserved <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00174">174</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<p>Structure used for bit access <br />
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<p>bit: 11 DFLL Lock Coarse Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00162">162</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<p>bit: 10 DFLL Lock Fine Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00161">161</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<p>bit: 9 DFLL Out Of Bounds Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00160">160</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<p>bit: 12 DFLL Reference Clock Stopped Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00163">163</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::DFLLRDY</td>
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<p>bit: 8 DFLL Ready Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00159">159</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<a id="a720fa315e2bc651f6e771a295f5029fb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a720fa315e2bc651f6e771a295f5029fb">&#9670;&nbsp;</a></span>DPLL0LCKF</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::DPLL0LCKF</td>
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<p>bit: 17 DPLL0 Lock Fall Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00166">166</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<a id="a945688150d0615bee601f2ac66253fec"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a945688150d0615bee601f2ac66253fec">&#9670;&nbsp;</a></span>DPLL0LCKR</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::DPLL0LCKR</td>
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<p>bit: 16 DPLL0 Lock Rise Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00165">165</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a68bba136fa06d23a4965bde19b658964">&#9670;&nbsp;</a></span>DPLL0LDRTO</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::DPLL0LDRTO</td>
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<p>bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00168">168</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#adcc5a32b64b3255d0664219a3782ab41">&#9670;&nbsp;</a></span>DPLL0LTO</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::DPLL0LTO</td>
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<p>bit: 18 DPLL0 Lock Timeout Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00167">167</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<a id="a48f12382dd5a95f0d6a8bbd5ebc317a7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a48f12382dd5a95f0d6a8bbd5ebc317a7">&#9670;&nbsp;</a></span>DPLL1LCKF</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::DPLL1LCKF</td>
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<p>bit: 25 DPLL1 Lock Fall Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00171">171</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<a id="ab3489c4e2b39b65dd31b685f0fbf611e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab3489c4e2b39b65dd31b685f0fbf611e">&#9670;&nbsp;</a></span>DPLL1LCKR</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::DPLL1LCKR</td>
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<p>bit: 24 DPLL1 Lock Rise Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00170">170</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<a id="a5f4abdb04e74ff74a4d2ecf6627c9f15"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5f4abdb04e74ff74a4d2ecf6627c9f15">&#9670;&nbsp;</a></span>DPLL1LDRTO</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::DPLL1LDRTO</td>
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<p>bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00173">173</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<a id="a6094cb6330e9a14afdde52b6ecfdd151"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6094cb6330e9a14afdde52b6ecfdd151">&#9670;&nbsp;</a></span>DPLL1LTO</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::DPLL1LTO</td>
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<p>bit: 26 DPLL1 Lock Timeout Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00172">172</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a0b1e8d91cae3805b0b59247bcc496e24">&#9670;&nbsp;</a></span>reg</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::reg</td>
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<p>Type used for register access <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00181">181</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a8d774ce5c03039e41ed59619ec3a413d">&#9670;&nbsp;</a></span>vec</h2>
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<td class="memname">struct { ... } OSCCTRL_INTENSET_Type::vec</td>
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<p>Structure used for vec access <br />
</p>
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<a id="adac12ffa2859220a2faa02d1c9382aa4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#adac12ffa2859220a2faa02d1c9382aa4">&#9670;&nbsp;</a></span>XOSCFAIL</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::XOSCFAIL</td>
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<p>bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00178">178</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a121f44a9fe620b3438acc78c129da26b">&#9670;&nbsp;</a></span>XOSCFAIL0</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::XOSCFAIL0</td>
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<p>bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00156">156</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#ab7a319ff078e076c61cdd594c6b20601">&#9670;&nbsp;</a></span>XOSCFAIL1</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::XOSCFAIL1</td>
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<p>bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00157">157</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<a id="a6a9e6f7186a0c9cccb72c29ef41a34d0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6a9e6f7186a0c9cccb72c29ef41a34d0">&#9670;&nbsp;</a></span>XOSCRDY</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::XOSCRDY</td>
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<p>bit: 0.. 1 XOSC x Ready Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00177">177</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<a id="afe37798b768a6b61273987370b0cf50b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#afe37798b768a6b61273987370b0cf50b">&#9670;&nbsp;</a></span>XOSCRDY0</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::XOSCRDY0</td>
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<p>bit: 0 XOSC 0 Ready Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00154">154</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<a id="a98d8021fb7eae9aebbef635cef53c38b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a98d8021fb7eae9aebbef635cef53c38b">&#9670;&nbsp;</a></span>XOSCRDY1</h2>
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<td class="memname">uint32_t OSCCTRL_INTENSET_Type::XOSCRDY1</td>
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<p>bit: 1 XOSC 1 Ready Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00155">155</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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<hr/>The documentation for this union was generated from the following file:<ul>
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