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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock">
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00266">266</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
</div><h2 class="groupheader">Field Documentation</h2>
<a id="ae0c7109506ed899029818ba4515b26c9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae0c7109506ed899029818ba4515b26c9">&#9670;&nbsp;</a></span>__pad0__</h2>
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<p>bit: 11..15 Reserved <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00279">279</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
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<a id="aad10b082b6189e41f108d5c40141f90f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aad10b082b6189e41f108d5c40141f90f">&#9670;&nbsp;</a></span>ADDRE</h2>
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<p>bit: 1 Address Error Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00269">269</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
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<a id="a8d477a4d482e43ce20935ea549558da8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8d477a4d482e43ce20935ea549558da8">&#9670;&nbsp;</a></span>bit</h2>
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<td class="memname">struct { ... } NVMCTRL_INTENSET_Type::bit</td>
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<p>Structure used for bit access <br />
</p>
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</div>
<a id="a7e11e9831f0d712a0570fc5b8e157a80"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7e11e9831f0d712a0570fc5b8e157a80">&#9670;&nbsp;</a></span>DONE</h2>
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<td class="memname">uint16_t NVMCTRL_INTENSET_Type::DONE</td>
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<p>bit: 0 Command Done Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00268">268</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
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<a id="a677dfd10acf0011a22ee327a89a9363b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a677dfd10acf0011a22ee327a89a9363b">&#9670;&nbsp;</a></span>ECCDE</h2>
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<td class="memname">uint16_t NVMCTRL_INTENSET_Type::ECCDE</td>
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<p>bit: 5 ECC Dual Error Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00273">273</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
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<a id="a2f4b33b3e2534635fc995f490084b8f2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2f4b33b3e2534635fc995f490084b8f2">&#9670;&nbsp;</a></span>ECCSE</h2>
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<td class="memname">uint16_t NVMCTRL_INTENSET_Type::ECCSE</td>
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<p>bit: 4 ECC Single Error Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00272">272</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
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<a id="a7a3225bbceed8f691b9d2815e3cead70"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7a3225bbceed8f691b9d2815e3cead70">&#9670;&nbsp;</a></span>LOCKE</h2>
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<td class="memname">uint16_t NVMCTRL_INTENSET_Type::LOCKE</td>
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<p>bit: 3 Lock Error Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00271">271</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
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<a id="a3453ea9b60b5aab08ac77b077050d18c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3453ea9b60b5aab08ac77b077050d18c">&#9670;&nbsp;</a></span>NVME</h2>
<div class="memitem">
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<td class="memname">uint16_t NVMCTRL_INTENSET_Type::NVME</td>
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<p>bit: 6 NVM Error Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00274">274</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
</div>
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<a id="a9b285721f768f3be959b53ecfc8e29e3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9b285721f768f3be959b53ecfc8e29e3">&#9670;&nbsp;</a></span>PROGE</h2>
<div class="memitem">
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<td class="memname">uint16_t NVMCTRL_INTENSET_Type::PROGE</td>
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<p>bit: 2 Programming Error Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00270">270</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
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<a id="afd3d225c78e3421a2006e6b9ff886d46"></a>
<h2 class="memtitle"><span class="permalink"><a href="#afd3d225c78e3421a2006e6b9ff886d46">&#9670;&nbsp;</a></span>reg</h2>
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<td class="memname">uint16_t NVMCTRL_INTENSET_Type::reg</td>
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<p>Type used for register access <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00281">281</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
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<a id="a0d4f7db8fe0470fd5642e4d0b284f8b4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0d4f7db8fe0470fd5642e4d0b284f8b4">&#9670;&nbsp;</a></span>SEESFULL</h2>
<div class="memitem">
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<td class="memname">uint16_t NVMCTRL_INTENSET_Type::SEESFULL</td>
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<p>bit: 8 Active SEES Full Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00276">276</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
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<a id="abf97f6c7c80d31d7a6d1b2f513166dad"></a>
<h2 class="memtitle"><span class="permalink"><a href="#abf97f6c7c80d31d7a6d1b2f513166dad">&#9670;&nbsp;</a></span>SEESOVF</h2>
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<td class="memname">uint16_t NVMCTRL_INTENSET_Type::SEESOVF</td>
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<p>bit: 9 Active SEES Overflow Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00277">277</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
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<a id="a9ac58004be432a1220e42351e8e081aa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9ac58004be432a1220e42351e8e081aa">&#9670;&nbsp;</a></span>SEEWRC</h2>
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<td class="memname">uint16_t NVMCTRL_INTENSET_Type::SEEWRC</td>
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<p>bit: 10 SEE Write Completed Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00278">278</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
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<a id="a367a53f996895c84cc7772398c60d03b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a367a53f996895c84cc7772398c60d03b">&#9670;&nbsp;</a></span>SUSP</h2>
<div class="memitem">
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<td class="memname">uint16_t NVMCTRL_INTENSET_Type::SUSP</td>
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<p>bit: 7 Suspended Write Or Erase Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00275">275</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
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<hr/>The documentation for this union was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a></li>
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