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<div class="title">DMAC_CHINTENCLR_Type Union Reference</div> </div>
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Data Fields</h2></td></tr>
<tr class="memitem:ad50cf7b9d00b41cbb225e3bc08f6c628"><td class="memItemLeft" >struct {</td></tr>
<tr class="memitem:a7ea4167380c8eec041e76866a914c4e1"><td class="memItemLeft" >&#160;&#160;&#160;uint8_t&#160;&#160;&#160;<a class="el" href="unionDMAC__CHINTENCLR__Type.html#a6b0be4d554087d984941b5813d5de294">TERR</a>:1</td></tr>
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<tr class="memitem:abfe60335f77a3c2061f2cfd953de15e1"><td class="memItemLeft" >&#160;&#160;&#160;uint8_t&#160;&#160;&#160;<a class="el" href="unionDMAC__CHINTENCLR__Type.html#a90ebd4c0021765c34b343695627e535f">TCMPL</a>:1</td></tr>
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<tr class="memitem:af9955cb253ff8fcadca7be47f6702f69"><td class="memItemLeft" >&#160;&#160;&#160;uint8_t&#160;&#160;&#160;<a class="el" href="unionDMAC__CHINTENCLR__Type.html#a219fb0ac5cb82b70ba0c6467a05344d0">SUSP</a>:1</td></tr>
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<tr class="memitem:a2d4d0ce71d0d9c8ae42bdf079af51cc1"><td class="memItemLeft" >&#160;&#160;&#160;uint8_t&#160;&#160;&#160;<a class="el" href="unionDMAC__CHINTENCLR__Type.html#a67c6af94274d4c6625e47a9df3b515a8">__pad0__</a>:5</td></tr>
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<tr class="memitem:ad50cf7b9d00b41cbb225e3bc08f6c628"><td class="memItemLeft" valign="top">}&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionDMAC__CHINTENCLR__Type.html#ad50cf7b9d00b41cbb225e3bc08f6c628">bit</a></td></tr>
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<tr class="memitem:aae9517421f51de50d6d7ab042310ffc7"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="unionDMAC__CHINTENCLR__Type.html#aae9517421f51de50d6d7ab042310ffc7">reg</a></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock">
<p class="definition">Definition at line <a class="el" href="component_2dmac_8h_source.html#l01093">1093</a> of file <a class="el" href="component_2dmac_8h_source.html">dmac.h</a>.</p>
</div><h2 class="groupheader">Field Documentation</h2>
<a id="a67c6af94274d4c6625e47a9df3b515a8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a67c6af94274d4c6625e47a9df3b515a8">&#9670;&nbsp;</a></span>__pad0__</h2>
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<td class="memname">uint8_t DMAC_CHINTENCLR_Type::__pad0__</td>
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<p>bit: 3.. 7 Reserved <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2dmac_8h_source.html#l01098">1098</a> of file <a class="el" href="component_2dmac_8h_source.html">dmac.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#ad50cf7b9d00b41cbb225e3bc08f6c628">&#9670;&nbsp;</a></span>bit</h2>
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<td class="memname">struct { ... } DMAC_CHINTENCLR_Type::bit</td>
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<p>Structure used for bit access <br />
</p>
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<h2 class="memtitle"><span class="permalink"><a href="#aae9517421f51de50d6d7ab042310ffc7">&#9670;&nbsp;</a></span>reg</h2>
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<td class="memname">uint8_t DMAC_CHINTENCLR_Type::reg</td>
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<p>Type used for register access <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2dmac_8h_source.html#l01100">1100</a> of file <a class="el" href="component_2dmac_8h_source.html">dmac.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a219fb0ac5cb82b70ba0c6467a05344d0">&#9670;&nbsp;</a></span>SUSP</h2>
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<td class="memname">uint8_t DMAC_CHINTENCLR_Type::SUSP</td>
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<p>bit: 2 Channel Suspend Interrupt Enable <br />
</p>
<p class="definition">Definition at line <a class="el" href="component_2dmac_8h_source.html#l01097">1097</a> of file <a class="el" href="component_2dmac_8h_source.html">dmac.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a90ebd4c0021765c34b343695627e535f">&#9670;&nbsp;</a></span>TCMPL</h2>
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<td class="memname">uint8_t DMAC_CHINTENCLR_Type::TCMPL</td>
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<p>bit: 1 Channel Transfer Complete Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2dmac_8h_source.html#l01096">1096</a> of file <a class="el" href="component_2dmac_8h_source.html">dmac.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a6b0be4d554087d984941b5813d5de294">&#9670;&nbsp;</a></span>TERR</h2>
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<td class="memname">uint8_t DMAC_CHINTENCLR_Type::TERR</td>
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<p>bit: 0 Channel Transfer Error Interrupt Enable </p>
<p class="definition">Definition at line <a class="el" href="component_2dmac_8h_source.html#l01095">1095</a> of file <a class="el" href="component_2dmac_8h_source.html">dmac.h</a>.</p>
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<hr/>The documentation for this union was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2dmac_8h_source.html">dmac.h</a></li>
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