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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">tc6.h</div> </div>
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<div class="contents">
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<a href="tc6_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_TC6_INSTANCE_</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_TC6_INSTANCE_</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for TC6 peripheral ========== */</span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_TC6_CTRLA (0x43001400) </span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_TC6_CTRLBCLR (0x43001404) </span></div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_TC6_CTRLBSET (0x43001405) </span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_TC6_EVCTRL (0x43001406) </span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_TC6_INTENCLR (0x43001408) </span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_TC6_INTENSET (0x43001409) </span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_TC6_INTFLAG (0x4300140A) </span></div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_TC6_STATUS (0x4300140B) </span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_TC6_WAVE (0x4300140C) </span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_TC6_DRVCTRL (0x4300140D) </span></div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_TC6_DBGCTRL (0x4300140F) </span></div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_TC6_SYNCBUSY (0x43001410) </span></div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_TC6_COUNT16_COUNT (0x43001414) </span></div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_TC6_COUNT16_CC0 (0x4300141C) </span></div>
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<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_TC6_COUNT16_CC1 (0x4300141E) </span></div>
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<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_TC6_COUNT16_CCBUF0 (0x43001430) </span></div>
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<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_TC6_COUNT16_CCBUF1 (0x43001432) </span></div>
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<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_TC6_COUNT32_COUNT (0x43001414) </span></div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_TC6_COUNT32_CC0 (0x4300141C) </span></div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_TC6_COUNT32_CC1 (0x43001420) </span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_TC6_COUNT32_CCBUF0 (0x43001430) </span></div>
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<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_TC6_COUNT32_CCBUF1 (0x43001434) </span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define REG_TC6_COUNT8_COUNT (0x43001414) </span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define REG_TC6_COUNT8_PER (0x4300141B) </span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#define REG_TC6_COUNT8_CC0 (0x4300141C) </span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor">#define REG_TC6_COUNT8_CC1 (0x4300141D) </span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="preprocessor">#define REG_TC6_COUNT8_PERBUF (0x4300142F) </span></div>
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<div class="line"><a name="l00062"></a><span class="lineno"> 62</span> <span class="preprocessor">#define REG_TC6_COUNT8_CCBUF0 (0x43001430) </span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor">#define REG_TC6_COUNT8_CCBUF1 (0x43001431) </span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="preprocessor">#else</span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="tc6_8h.html#a2a42ceed3900b8f1bc4909ddf5457a34"> 65</a></span> <span class="preprocessor">#define REG_TC6_CTRLA (*(RwReg *)0x43001400UL) </span></div>
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<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="tc6_8h.html#a2ffb67d59a8a36ce11e645a476708283"> 66</a></span> <span class="preprocessor">#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x43001404UL) </span></div>
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<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="tc6_8h.html#a47c516d80434b7f0cf5dcc1891a46b80"> 67</a></span> <span class="preprocessor">#define REG_TC6_CTRLBSET (*(RwReg8 *)0x43001405UL) </span></div>
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<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="tc6_8h.html#ab668a3e9b67459e4428287e606ff030d"> 68</a></span> <span class="preprocessor">#define REG_TC6_EVCTRL (*(RwReg16*)0x43001406UL) </span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="tc6_8h.html#a1be697da1bf0e8500f8c9dcfad825200"> 69</a></span> <span class="preprocessor">#define REG_TC6_INTENCLR (*(RwReg8 *)0x43001408UL) </span></div>
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<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="tc6_8h.html#ab71502fb437c5338b2932be4fddfa599"> 70</a></span> <span class="preprocessor">#define REG_TC6_INTENSET (*(RwReg8 *)0x43001409UL) </span></div>
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<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="tc6_8h.html#a8b9fcd7ed831fe9a94eebfb3fa003b91"> 71</a></span> <span class="preprocessor">#define REG_TC6_INTFLAG (*(RwReg8 *)0x4300140AUL) </span></div>
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<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="tc6_8h.html#abe4622d9ee09a82a2bc6924a57543559"> 72</a></span> <span class="preprocessor">#define REG_TC6_STATUS (*(RwReg8 *)0x4300140BUL) </span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="tc6_8h.html#a6e1f74c5e9c6dd2e45a80e159873d9cf"> 73</a></span> <span class="preprocessor">#define REG_TC6_WAVE (*(RwReg8 *)0x4300140CUL) </span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="tc6_8h.html#ad035492f86b01d3a485d481f3db5697d"> 74</a></span> <span class="preprocessor">#define REG_TC6_DRVCTRL (*(RwReg8 *)0x4300140DUL) </span></div>
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<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="tc6_8h.html#ac33d7095f63674a2df1b75b10154aad8"> 75</a></span> <span class="preprocessor">#define REG_TC6_DBGCTRL (*(RwReg8 *)0x4300140FUL) </span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="tc6_8h.html#a6f6c84778e29e8b699edc548bf62e77f"> 76</a></span> <span class="preprocessor">#define REG_TC6_SYNCBUSY (*(RoReg *)0x43001410UL) </span></div>
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<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="tc6_8h.html#aa8bfea2b7d4f70e05f2aaf180b7a907e"> 77</a></span> <span class="preprocessor">#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x43001414UL) </span></div>
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<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="tc6_8h.html#a796b16088709f70d7bc0b9bcce87a2b1"> 78</a></span> <span class="preprocessor">#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x4300141CUL) </span></div>
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<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="tc6_8h.html#a392832ef09f5df4675e7acafe8f94ac9"> 79</a></span> <span class="preprocessor">#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4300141EUL) </span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="tc6_8h.html#afcb709f3979b648dcae084cde4672f7b"> 80</a></span> <span class="preprocessor">#define REG_TC6_COUNT16_CCBUF0 (*(RwReg16*)0x43001430UL) </span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="tc6_8h.html#a5298393144fb092af1a6b5fa51c40951"> 81</a></span> <span class="preprocessor">#define REG_TC6_COUNT16_CCBUF1 (*(RwReg16*)0x43001432UL) </span></div>
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<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="tc6_8h.html#a41152348f7d2b78ee5a69297b2838d4e"> 82</a></span> <span class="preprocessor">#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x43001414UL) </span></div>
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<div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="tc6_8h.html#a8842d1553335c4bd8fa12d8f54471c85"> 83</a></span> <span class="preprocessor">#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x4300141CUL) </span></div>
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<div class="line"><a name="l00084"></a><span class="lineno"><a class="line" href="tc6_8h.html#a4ad319aa8349bf80254a3239202221fa"> 84</a></span> <span class="preprocessor">#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x43001420UL) </span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"><a class="line" href="tc6_8h.html#a2faee0a09f3b90ac36ef422722ef28e9"> 85</a></span> <span class="preprocessor">#define REG_TC6_COUNT32_CCBUF0 (*(RwReg *)0x43001430UL) </span></div>
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<div class="line"><a name="l00086"></a><span class="lineno"><a class="line" href="tc6_8h.html#ae73fde7ce02346d2b0d21c62acfb8873"> 86</a></span> <span class="preprocessor">#define REG_TC6_COUNT32_CCBUF1 (*(RwReg *)0x43001434UL) </span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"><a class="line" href="tc6_8h.html#a99c114d0a3df4202417e1ebc8459154f"> 87</a></span> <span class="preprocessor">#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x43001414UL) </span></div>
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<div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="tc6_8h.html#a9abaa349888334d143144f29473efa24"> 88</a></span> <span class="preprocessor">#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x4300141BUL) </span></div>
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<div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="tc6_8h.html#a5a2ef15830497893a775eb7bd779a0ff"> 89</a></span> <span class="preprocessor">#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x4300141CUL) </span></div>
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<div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="tc6_8h.html#a6c2291bc909dc268453463ebaf273aa0"> 90</a></span> <span class="preprocessor">#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x4300141DUL) </span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="tc6_8h.html#a40a70937113a432231ddce453139a985"> 91</a></span> <span class="preprocessor">#define REG_TC6_COUNT8_PERBUF (*(RwReg8 *)0x4300142FUL) </span></div>
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<div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="tc6_8h.html#a220a33809698d2eac3a187666a5177db"> 92</a></span> <span class="preprocessor">#define REG_TC6_COUNT8_CCBUF0 (*(RwReg8 *)0x43001430UL) </span></div>
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<div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="tc6_8h.html#a5bf3c8681b0fcf85a3dbe7063bf150e1"> 93</a></span> <span class="preprocessor">#define REG_TC6_COUNT8_CCBUF1 (*(RwReg8 *)0x43001431UL) </span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span>  </div>
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<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="comment">/* ========== Instance parameters for TC6 peripheral ========== */</span></div>
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<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="preprocessor">#define TC6_CC_NUM 2 </span></div>
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<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#define TC6_DMAC_ID_MC_0 63</span></div>
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<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor">#define TC6_DMAC_ID_MC_1 64</span></div>
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<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor">#define TC6_DMAC_ID_MC_LSB 63</span></div>
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<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor">#define TC6_DMAC_ID_MC_MSB 64</span></div>
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<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="preprocessor">#define TC6_DMAC_ID_MC_SIZE 2</span></div>
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<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#define TC6_DMAC_ID_OVF 62 // Indexes of DMA Overflow trigger</span></div>
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<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> <span class="preprocessor">#define TC6_EXT 0 // Coding of implemented extended features (keep 0 value)</span></div>
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<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor">#define TC6_GCLK_ID 39 // Index of Generic Clock</span></div>
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<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> <span class="preprocessor">#define TC6_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave</span></div>
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<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="preprocessor">#define TC6_OW_NUM 2 // Number of Output Waveforms</span></div>
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<div class="line"><a name="l00108"></a><span class="lineno"> 108</span>  </div>
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<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_TC6_INSTANCE_ */</span><span class="preprocessor"></span></div>
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