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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">tc5.h</div> </div>
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<div class="contents">
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<a href="tc5_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_TC5_INSTANCE_</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_TC5_INSTANCE_</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for TC5 peripheral ========== */</span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_TC5_CTRLA (0x42001800) </span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_TC5_CTRLBCLR (0x42001804) </span></div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_TC5_CTRLBSET (0x42001805) </span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_TC5_EVCTRL (0x42001806) </span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_TC5_INTENCLR (0x42001808) </span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_TC5_INTENSET (0x42001809) </span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_TC5_INTFLAG (0x4200180A) </span></div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_TC5_STATUS (0x4200180B) </span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_TC5_WAVE (0x4200180C) </span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_TC5_DRVCTRL (0x4200180D) </span></div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_TC5_DBGCTRL (0x4200180F) </span></div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_TC5_SYNCBUSY (0x42001810) </span></div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_TC5_COUNT16_COUNT (0x42001814) </span></div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_TC5_COUNT16_CC0 (0x4200181C) </span></div>
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<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_TC5_COUNT16_CC1 (0x4200181E) </span></div>
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<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_TC5_COUNT16_CCBUF0 (0x42001830) </span></div>
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<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_TC5_COUNT16_CCBUF1 (0x42001832) </span></div>
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<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_TC5_COUNT32_COUNT (0x42001814) </span></div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_TC5_COUNT32_CC0 (0x4200181C) </span></div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_TC5_COUNT32_CC1 (0x42001820) </span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_TC5_COUNT32_CCBUF0 (0x42001830) </span></div>
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<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_TC5_COUNT32_CCBUF1 (0x42001834) </span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define REG_TC5_COUNT8_COUNT (0x42001814) </span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define REG_TC5_COUNT8_PER (0x4200181B) </span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#define REG_TC5_COUNT8_CC0 (0x4200181C) </span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor">#define REG_TC5_COUNT8_CC1 (0x4200181D) </span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="preprocessor">#define REG_TC5_COUNT8_PERBUF (0x4200182F) </span></div>
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<div class="line"><a name="l00062"></a><span class="lineno"> 62</span> <span class="preprocessor">#define REG_TC5_COUNT8_CCBUF0 (0x42001830) </span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor">#define REG_TC5_COUNT8_CCBUF1 (0x42001831) </span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="preprocessor">#else</span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="tc5_8h.html#a36f2f5adaa216f7e2d6f351a4237b0b5"> 65</a></span> <span class="preprocessor">#define REG_TC5_CTRLA (*(RwReg *)0x42001800UL) </span></div>
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<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="tc5_8h.html#a03620420f6220c74b2af9877d7515857"> 66</a></span> <span class="preprocessor">#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42001804UL) </span></div>
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<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="tc5_8h.html#a10c61f89faec9e7c619ac274808d7a22"> 67</a></span> <span class="preprocessor">#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42001805UL) </span></div>
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<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="tc5_8h.html#a6c4910cd3213e47d9d76a1024c3688bb"> 68</a></span> <span class="preprocessor">#define REG_TC5_EVCTRL (*(RwReg16*)0x42001806UL) </span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="tc5_8h.html#aaebdd97b315232f561552586ca65238a"> 69</a></span> <span class="preprocessor">#define REG_TC5_INTENCLR (*(RwReg8 *)0x42001808UL) </span></div>
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<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="tc5_8h.html#a81334a898c261d5fdf7f97ee7918b125"> 70</a></span> <span class="preprocessor">#define REG_TC5_INTENSET (*(RwReg8 *)0x42001809UL) </span></div>
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<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="tc5_8h.html#a0bcc5d7cf40d3b43a00eba853224e2bd"> 71</a></span> <span class="preprocessor">#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200180AUL) </span></div>
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<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="tc5_8h.html#a3c06987126a6226210e7196f84bff2f1"> 72</a></span> <span class="preprocessor">#define REG_TC5_STATUS (*(RwReg8 *)0x4200180BUL) </span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="tc5_8h.html#af0e7234f34ea548a7ac7ae8d89f59fe4"> 73</a></span> <span class="preprocessor">#define REG_TC5_WAVE (*(RwReg8 *)0x4200180CUL) </span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="tc5_8h.html#af78cd407732db6ff1d23bcb59881ecbd"> 74</a></span> <span class="preprocessor">#define REG_TC5_DRVCTRL (*(RwReg8 *)0x4200180DUL) </span></div>
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<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="tc5_8h.html#a2bd0ebe3f5a205d00730b70f4725094c"> 75</a></span> <span class="preprocessor">#define REG_TC5_DBGCTRL (*(RwReg8 *)0x4200180FUL) </span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="tc5_8h.html#a0c6d52d871b48c5fd3649e6ba803af39"> 76</a></span> <span class="preprocessor">#define REG_TC5_SYNCBUSY (*(RoReg *)0x42001810UL) </span></div>
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<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="tc5_8h.html#aca48651342c6095ce0678522106952b6"> 77</a></span> <span class="preprocessor">#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42001814UL) </span></div>
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<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="tc5_8h.html#adeb0a01a1e964be87b5f5616ecae982d"> 78</a></span> <span class="preprocessor">#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x4200181CUL) </span></div>
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<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="tc5_8h.html#ac311a74865044a332483f5fe300f0847"> 79</a></span> <span class="preprocessor">#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200181EUL) </span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="tc5_8h.html#a8d6db84c219ef2b12d8ba44669349746"> 80</a></span> <span class="preprocessor">#define REG_TC5_COUNT16_CCBUF0 (*(RwReg16*)0x42001830UL) </span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="tc5_8h.html#aad176ca3dd230dc01a935a9004dc7190"> 81</a></span> <span class="preprocessor">#define REG_TC5_COUNT16_CCBUF1 (*(RwReg16*)0x42001832UL) </span></div>
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<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="tc5_8h.html#ad03e8573951c9fca5edec5470bea0763"> 82</a></span> <span class="preprocessor">#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42001814UL) </span></div>
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<div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="tc5_8h.html#abd975e5f793b61f099e970a6381a071e"> 83</a></span> <span class="preprocessor">#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x4200181CUL) </span></div>
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<div class="line"><a name="l00084"></a><span class="lineno"><a class="line" href="tc5_8h.html#acef420d6ce5f220f693ea690df5c7b00"> 84</a></span> <span class="preprocessor">#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x42001820UL) </span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"><a class="line" href="tc5_8h.html#a09d62f31d98e9dd5defe49bc7c4bc10a"> 85</a></span> <span class="preprocessor">#define REG_TC5_COUNT32_CCBUF0 (*(RwReg *)0x42001830UL) </span></div>
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<div class="line"><a name="l00086"></a><span class="lineno"><a class="line" href="tc5_8h.html#a44ed2183a1cad8c0f5626deebdfd87e3"> 86</a></span> <span class="preprocessor">#define REG_TC5_COUNT32_CCBUF1 (*(RwReg *)0x42001834UL) </span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"><a class="line" href="tc5_8h.html#a928e868195d74eed096d2354e360aee8"> 87</a></span> <span class="preprocessor">#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42001814UL) </span></div>
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<div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="tc5_8h.html#a4a852a08add96ebd2f8ac73140eac869"> 88</a></span> <span class="preprocessor">#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x4200181BUL) </span></div>
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<div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="tc5_8h.html#ae376099626a29b16e49fdf83c6c27e69"> 89</a></span> <span class="preprocessor">#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x4200181CUL) </span></div>
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<div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="tc5_8h.html#afac369a178a8928f5cf497c37d84f7c3"> 90</a></span> <span class="preprocessor">#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x4200181DUL) </span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="tc5_8h.html#a804249e9bbdefe094e0dc6362d9e3aef"> 91</a></span> <span class="preprocessor">#define REG_TC5_COUNT8_PERBUF (*(RwReg8 *)0x4200182FUL) </span></div>
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<div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="tc5_8h.html#af68312ffd44bd94c50bd8f93e2d296eb"> 92</a></span> <span class="preprocessor">#define REG_TC5_COUNT8_CCBUF0 (*(RwReg8 *)0x42001830UL) </span></div>
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<div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="tc5_8h.html#a6b35c5bb80e449b6303b6916243af6fd"> 93</a></span> <span class="preprocessor">#define REG_TC5_COUNT8_CCBUF1 (*(RwReg8 *)0x42001831UL) </span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span>  </div>
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<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="comment">/* ========== Instance parameters for TC5 peripheral ========== */</span></div>
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<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="preprocessor">#define TC5_CC_NUM 2 </span></div>
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<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#define TC5_DMAC_ID_MC_0 60</span></div>
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<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor">#define TC5_DMAC_ID_MC_1 61</span></div>
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<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor">#define TC5_DMAC_ID_MC_LSB 60</span></div>
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<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor">#define TC5_DMAC_ID_MC_MSB 61</span></div>
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<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="preprocessor">#define TC5_DMAC_ID_MC_SIZE 2</span></div>
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<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#define TC5_DMAC_ID_OVF 59 // Indexes of DMA Overflow trigger</span></div>
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<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> <span class="preprocessor">#define TC5_EXT 0 // Coding of implemented extended features (keep 0 value)</span></div>
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<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor">#define TC5_GCLK_ID 30 // Index of Generic Clock</span></div>
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<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> <span class="preprocessor">#define TC5_MASTER_SLAVE_MODE 2 // TC type 0 : NA, 1 : Master, 2 : Slave</span></div>
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<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="preprocessor">#define TC5_OW_NUM 2 // Number of Output Waveforms</span></div>
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<div class="line"><a name="l00108"></a><span class="lineno"> 108</span>  </div>
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<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_TC5_INSTANCE_ */</span><span class="preprocessor"></span></div>
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