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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">tc2.h</div> </div>
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<div class="contents">
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<a href="tc2_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_TC2_INSTANCE_</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_TC2_INSTANCE_</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for TC2 peripheral ========== */</span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_TC2_CTRLA (0x4101A000) </span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_TC2_CTRLBCLR (0x4101A004) </span></div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_TC2_CTRLBSET (0x4101A005) </span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_TC2_EVCTRL (0x4101A006) </span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_TC2_INTENCLR (0x4101A008) </span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_TC2_INTENSET (0x4101A009) </span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_TC2_INTFLAG (0x4101A00A) </span></div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_TC2_STATUS (0x4101A00B) </span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_TC2_WAVE (0x4101A00C) </span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_TC2_DRVCTRL (0x4101A00D) </span></div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_TC2_DBGCTRL (0x4101A00F) </span></div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_TC2_SYNCBUSY (0x4101A010) </span></div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_TC2_COUNT16_COUNT (0x4101A014) </span></div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_TC2_COUNT16_CC0 (0x4101A01C) </span></div>
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<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_TC2_COUNT16_CC1 (0x4101A01E) </span></div>
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<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_TC2_COUNT16_CCBUF0 (0x4101A030) </span></div>
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<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_TC2_COUNT16_CCBUF1 (0x4101A032) </span></div>
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<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_TC2_COUNT32_COUNT (0x4101A014) </span></div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_TC2_COUNT32_CC0 (0x4101A01C) </span></div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_TC2_COUNT32_CC1 (0x4101A020) </span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_TC2_COUNT32_CCBUF0 (0x4101A030) </span></div>
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<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_TC2_COUNT32_CCBUF1 (0x4101A034) </span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define REG_TC2_COUNT8_COUNT (0x4101A014) </span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define REG_TC2_COUNT8_PER (0x4101A01B) </span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#define REG_TC2_COUNT8_CC0 (0x4101A01C) </span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor">#define REG_TC2_COUNT8_CC1 (0x4101A01D) </span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="preprocessor">#define REG_TC2_COUNT8_PERBUF (0x4101A02F) </span></div>
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<div class="line"><a name="l00062"></a><span class="lineno"> 62</span> <span class="preprocessor">#define REG_TC2_COUNT8_CCBUF0 (0x4101A030) </span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor">#define REG_TC2_COUNT8_CCBUF1 (0x4101A031) </span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="preprocessor">#else</span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="tc2_8h.html#a602e97de147dbbf449752f7201252873"> 65</a></span> <span class="preprocessor">#define REG_TC2_CTRLA (*(RwReg *)0x4101A000UL) </span></div>
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<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="tc2_8h.html#a5e199a0b6c0812b7cedb7eccc99e3860"> 66</a></span> <span class="preprocessor">#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x4101A004UL) </span></div>
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<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="tc2_8h.html#ab9ad3b25bc48b6494f774a7501812cbd"> 67</a></span> <span class="preprocessor">#define REG_TC2_CTRLBSET (*(RwReg8 *)0x4101A005UL) </span></div>
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<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="tc2_8h.html#ab16f699085b459ceacb143d7c94f5483"> 68</a></span> <span class="preprocessor">#define REG_TC2_EVCTRL (*(RwReg16*)0x4101A006UL) </span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="tc2_8h.html#a9582b7fbf5107f6c27a6a1b72f16b245"> 69</a></span> <span class="preprocessor">#define REG_TC2_INTENCLR (*(RwReg8 *)0x4101A008UL) </span></div>
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<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="tc2_8h.html#aacac77761400e95b9c25e4703e9c0318"> 70</a></span> <span class="preprocessor">#define REG_TC2_INTENSET (*(RwReg8 *)0x4101A009UL) </span></div>
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<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="tc2_8h.html#a9a1b860bea03636894bc6107504d22b5"> 71</a></span> <span class="preprocessor">#define REG_TC2_INTFLAG (*(RwReg8 *)0x4101A00AUL) </span></div>
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<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="tc2_8h.html#a8f0af3a08313543cb63a73ebd015a66f"> 72</a></span> <span class="preprocessor">#define REG_TC2_STATUS (*(RwReg8 *)0x4101A00BUL) </span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="tc2_8h.html#a16591f977ec83f9106172bb32f3e2760"> 73</a></span> <span class="preprocessor">#define REG_TC2_WAVE (*(RwReg8 *)0x4101A00CUL) </span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="tc2_8h.html#a2a23fe4fda1fa90c29b9811ea9d1fbb7"> 74</a></span> <span class="preprocessor">#define REG_TC2_DRVCTRL (*(RwReg8 *)0x4101A00DUL) </span></div>
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<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="tc2_8h.html#aecb3b78cffbc51ce22aa967a3648c424"> 75</a></span> <span class="preprocessor">#define REG_TC2_DBGCTRL (*(RwReg8 *)0x4101A00FUL) </span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="tc2_8h.html#a606b017fd26e16b00fb116688a8ce117"> 76</a></span> <span class="preprocessor">#define REG_TC2_SYNCBUSY (*(RoReg *)0x4101A010UL) </span></div>
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<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="tc2_8h.html#a170972d7947b2e9af6b647abfc1ff451"> 77</a></span> <span class="preprocessor">#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x4101A014UL) </span></div>
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<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="tc2_8h.html#aa7813e9429dba001efaf685d11467a3e"> 78</a></span> <span class="preprocessor">#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4101A01CUL) </span></div>
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<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="tc2_8h.html#a065a6cfa874c8b09114c369146f22a7d"> 79</a></span> <span class="preprocessor">#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4101A01EUL) </span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="tc2_8h.html#a845b435dcd8351eb5efae7d15df12aa8"> 80</a></span> <span class="preprocessor">#define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x4101A030UL) </span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="tc2_8h.html#a421a47fbfee296a73e3f2279ef9f1be4"> 81</a></span> <span class="preprocessor">#define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x4101A032UL) </span></div>
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<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="tc2_8h.html#a1f5b44a590a1d803c5d853ba145d5fc0"> 82</a></span> <span class="preprocessor">#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x4101A014UL) </span></div>
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<div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="tc2_8h.html#a9c3e8a88363b722b314259bde5c4c901"> 83</a></span> <span class="preprocessor">#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4101A01CUL) </span></div>
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<div class="line"><a name="l00084"></a><span class="lineno"><a class="line" href="tc2_8h.html#ac544efda8296544db6db55ff0c4b21e3"> 84</a></span> <span class="preprocessor">#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x4101A020UL) </span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"><a class="line" href="tc2_8h.html#ab9fe2757bcf6e0383b366b896b58e241"> 85</a></span> <span class="preprocessor">#define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x4101A030UL) </span></div>
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<div class="line"><a name="l00086"></a><span class="lineno"><a class="line" href="tc2_8h.html#a7d91825566f7f73256a4c68ad0a7d80a"> 86</a></span> <span class="preprocessor">#define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x4101A034UL) </span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"><a class="line" href="tc2_8h.html#a10e15b50e41ba93ead8ff3c0a7bcd144"> 87</a></span> <span class="preprocessor">#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x4101A014UL) </span></div>
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<div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="tc2_8h.html#a520d8988d793f085384afae520db879e"> 88</a></span> <span class="preprocessor">#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4101A01BUL) </span></div>
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<div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="tc2_8h.html#ae3c6cbad961bb9b862e08f27a5cc16a5"> 89</a></span> <span class="preprocessor">#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4101A01CUL) </span></div>
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<div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="tc2_8h.html#ac2f7d868c024f149ff5271421bb2e74a"> 90</a></span> <span class="preprocessor">#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4101A01DUL) </span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="tc2_8h.html#a391a085606a3d1fa46b28347ca035fe8"> 91</a></span> <span class="preprocessor">#define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4101A02FUL) </span></div>
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<div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="tc2_8h.html#aa03aaa884b053fd83b913cfd762319b6"> 92</a></span> <span class="preprocessor">#define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x4101A030UL) </span></div>
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<div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="tc2_8h.html#a0fc5ff1e41d6817c64822cefb0dbb3ca"> 93</a></span> <span class="preprocessor">#define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x4101A031UL) </span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span>  </div>
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<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="comment">/* ========== Instance parameters for TC2 peripheral ========== */</span></div>
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<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="preprocessor">#define TC2_CC_NUM 2 </span></div>
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<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#define TC2_DMAC_ID_MC_0 51</span></div>
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<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor">#define TC2_DMAC_ID_MC_1 52</span></div>
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<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor">#define TC2_DMAC_ID_MC_LSB 51</span></div>
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<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor">#define TC2_DMAC_ID_MC_MSB 52</span></div>
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<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="preprocessor">#define TC2_DMAC_ID_MC_SIZE 2</span></div>
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<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#define TC2_DMAC_ID_OVF 50 // Indexes of DMA Overflow trigger</span></div>
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<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> <span class="preprocessor">#define TC2_EXT 0 // Coding of implemented extended features (keep 0 value)</span></div>
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<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor">#define TC2_GCLK_ID 26 // Index of Generic Clock</span></div>
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<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> <span class="preprocessor">#define TC2_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave</span></div>
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<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="preprocessor">#define TC2_OW_NUM 2 // Number of Output Waveforms</span></div>
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<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_TC2_INSTANCE_ */</span><span class="preprocessor"></span></div>
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