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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">tc0.h</div> </div>
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<div class="contents">
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<a href="tc0_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_TC0_INSTANCE_</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_TC0_INSTANCE_</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for TC0 peripheral ========== */</span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_TC0_CTRLA (0x40003800) </span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_TC0_CTRLBCLR (0x40003804) </span></div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_TC0_CTRLBSET (0x40003805) </span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_TC0_EVCTRL (0x40003806) </span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_TC0_INTENCLR (0x40003808) </span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_TC0_INTENSET (0x40003809) </span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_TC0_INTFLAG (0x4000380A) </span></div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_TC0_STATUS (0x4000380B) </span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_TC0_WAVE (0x4000380C) </span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_TC0_DRVCTRL (0x4000380D) </span></div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_TC0_DBGCTRL (0x4000380F) </span></div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_TC0_SYNCBUSY (0x40003810) </span></div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_TC0_COUNT16_COUNT (0x40003814) </span></div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_TC0_COUNT16_CC0 (0x4000381C) </span></div>
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<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_TC0_COUNT16_CC1 (0x4000381E) </span></div>
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<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_TC0_COUNT16_CCBUF0 (0x40003830) </span></div>
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<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_TC0_COUNT16_CCBUF1 (0x40003832) </span></div>
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<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_TC0_COUNT32_COUNT (0x40003814) </span></div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_TC0_COUNT32_CC0 (0x4000381C) </span></div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_TC0_COUNT32_CC1 (0x40003820) </span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_TC0_COUNT32_CCBUF0 (0x40003830) </span></div>
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<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_TC0_COUNT32_CCBUF1 (0x40003834) </span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define REG_TC0_COUNT8_COUNT (0x40003814) </span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define REG_TC0_COUNT8_PER (0x4000381B) </span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#define REG_TC0_COUNT8_CC0 (0x4000381C) </span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor">#define REG_TC0_COUNT8_CC1 (0x4000381D) </span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="preprocessor">#define REG_TC0_COUNT8_PERBUF (0x4000382F) </span></div>
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<div class="line"><a name="l00062"></a><span class="lineno"> 62</span> <span class="preprocessor">#define REG_TC0_COUNT8_CCBUF0 (0x40003830) </span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor">#define REG_TC0_COUNT8_CCBUF1 (0x40003831) </span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="preprocessor">#else</span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="tc0_8h.html#a501a29d491fdc64ccf54b854fc7a0416"> 65</a></span> <span class="preprocessor">#define REG_TC0_CTRLA (*(RwReg *)0x40003800UL) </span></div>
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<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="tc0_8h.html#a52e563deca463927a67d758c8440ce94"> 66</a></span> <span class="preprocessor">#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x40003804UL) </span></div>
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<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="tc0_8h.html#ae9a6ae4b9eeb3ab5740e74533133231f"> 67</a></span> <span class="preprocessor">#define REG_TC0_CTRLBSET (*(RwReg8 *)0x40003805UL) </span></div>
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<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="tc0_8h.html#a3e07d56ef477f730a08ecf805c011489"> 68</a></span> <span class="preprocessor">#define REG_TC0_EVCTRL (*(RwReg16*)0x40003806UL) </span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="tc0_8h.html#a952f878bfb85b9ba26abff4a22a7522f"> 69</a></span> <span class="preprocessor">#define REG_TC0_INTENCLR (*(RwReg8 *)0x40003808UL) </span></div>
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<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="tc0_8h.html#aca5dd6c113c34f6c503cbe688e45a9c5"> 70</a></span> <span class="preprocessor">#define REG_TC0_INTENSET (*(RwReg8 *)0x40003809UL) </span></div>
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<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="tc0_8h.html#aed10d46f7d47ff44ee8d5942360e1a9a"> 71</a></span> <span class="preprocessor">#define REG_TC0_INTFLAG (*(RwReg8 *)0x4000380AUL) </span></div>
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<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="tc0_8h.html#a00fdb55a56a33638104ad31bf3f3f182"> 72</a></span> <span class="preprocessor">#define REG_TC0_STATUS (*(RwReg8 *)0x4000380BUL) </span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="tc0_8h.html#a9e00c234c76aec073adb0388cad52c68"> 73</a></span> <span class="preprocessor">#define REG_TC0_WAVE (*(RwReg8 *)0x4000380CUL) </span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="tc0_8h.html#a5c9efa7d2ec38147d9b0ffdaa33f536b"> 74</a></span> <span class="preprocessor">#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4000380DUL) </span></div>
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<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="tc0_8h.html#a6fea929a7941a2b9bbd863b55e76ca68"> 75</a></span> <span class="preprocessor">#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4000380FUL) </span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="tc0_8h.html#adc1cf6fcb8fd4f5e93943790568020a9"> 76</a></span> <span class="preprocessor">#define REG_TC0_SYNCBUSY (*(RoReg *)0x40003810UL) </span></div>
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<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="tc0_8h.html#a85d595198b1c1440221a8109cc046c78"> 77</a></span> <span class="preprocessor">#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x40003814UL) </span></div>
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<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="tc0_8h.html#a80429d809bb7fa5d1bc3bba8120a2c00"> 78</a></span> <span class="preprocessor">#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4000381CUL) </span></div>
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<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="tc0_8h.html#a68fbdeb33e1beba3f09fef4a01edec17"> 79</a></span> <span class="preprocessor">#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4000381EUL) </span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="tc0_8h.html#a8b2fc7a4645c962ba85f6f3a92f0529c"> 80</a></span> <span class="preprocessor">#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x40003830UL) </span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="tc0_8h.html#a9f94c46481b56a3e1caadd799af3da9d"> 81</a></span> <span class="preprocessor">#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x40003832UL) </span></div>
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<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="tc0_8h.html#a166f52310a912bd6d7d81cf0684c82bf"> 82</a></span> <span class="preprocessor">#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x40003814UL) </span></div>
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<div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="tc0_8h.html#a4bc750dad60cfcf006c7726a04b9ce9c"> 83</a></span> <span class="preprocessor">#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4000381CUL) </span></div>
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<div class="line"><a name="l00084"></a><span class="lineno"><a class="line" href="tc0_8h.html#ab22fbf8a3b69ffd2a3e2f05637a92c86"> 84</a></span> <span class="preprocessor">#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x40003820UL) </span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"><a class="line" href="tc0_8h.html#ad34b246580a8fd096af0d232b8e937dc"> 85</a></span> <span class="preprocessor">#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x40003830UL) </span></div>
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<div class="line"><a name="l00086"></a><span class="lineno"><a class="line" href="tc0_8h.html#a10621ba2863c6086a9107d66fa510923"> 86</a></span> <span class="preprocessor">#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x40003834UL) </span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"><a class="line" href="tc0_8h.html#a265e360444ac2c22261e62cfc8a9531c"> 87</a></span> <span class="preprocessor">#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x40003814UL) </span></div>
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<div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="tc0_8h.html#a1df99c66fd2e4c8d0e1a7cbd5ed85740"> 88</a></span> <span class="preprocessor">#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4000381BUL) </span></div>
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<div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="tc0_8h.html#a7563890ac8081315d1e44f5839f537b4"> 89</a></span> <span class="preprocessor">#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4000381CUL) </span></div>
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<div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="tc0_8h.html#ad26f1e087e67966a7a799c28bf588b45"> 90</a></span> <span class="preprocessor">#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4000381DUL) </span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="tc0_8h.html#a3c5c2f13b7755b25fabc4d5f48ec0781"> 91</a></span> <span class="preprocessor">#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4000382FUL) </span></div>
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<div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="tc0_8h.html#a9230ff443c63e2e9a5520a33f0c08c08"> 92</a></span> <span class="preprocessor">#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x40003830UL) </span></div>
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<div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="tc0_8h.html#a2206851e921fa37563c07c1962428c30"> 93</a></span> <span class="preprocessor">#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x40003831UL) </span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span>  </div>
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<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="comment">/* ========== Instance parameters for TC0 peripheral ========== */</span></div>
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<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="preprocessor">#define TC0_CC_NUM 2 </span></div>
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<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#define TC0_DMAC_ID_MC_0 45</span></div>
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<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor">#define TC0_DMAC_ID_MC_1 46</span></div>
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<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor">#define TC0_DMAC_ID_MC_LSB 45</span></div>
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<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor">#define TC0_DMAC_ID_MC_MSB 46</span></div>
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<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="preprocessor">#define TC0_DMAC_ID_MC_SIZE 2</span></div>
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<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#define TC0_DMAC_ID_OVF 44 // Indexes of DMA Overflow trigger</span></div>
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<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> <span class="preprocessor">#define TC0_EXT 0 // Coding of implemented extended features (keep 0 value)</span></div>
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<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor">#define TC0_GCLK_ID 9 // Index of Generic Clock</span></div>
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<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> <span class="preprocessor">#define TC0_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave</span></div>
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<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="preprocessor">#define TC0_OW_NUM 2 // Number of Output Waveforms</span></div>
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<div class="line"><a name="l00108"></a><span class="lineno"> 108</span>  </div>
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<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_TC0_INSTANCE_ */</span><span class="preprocessor"></span></div>
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