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<div id="projectname">SAME54P20A Test Project
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">SercomUsart Struct Reference</div> </div>
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<p>SERCOM_USART hardware registers.
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<a href="structSercomUsart.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="sercom_8h_source.html">sercom.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a0d6e3df70af3c2599e2227162d7e481d"><td class="memItemLeft" align="right" valign="top"><a id="a0d6e3df70af3c2599e2227162d7e481d"></a>
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__IO <a class="el" href="unionSERCOM__USART__CTRLA__Type.html">SERCOM_USART_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#a0d6e3df70af3c2599e2227162d7e481d">CTRLA</a></td></tr>
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<tr class="memdesc:a0d6e3df70af3c2599e2227162d7e481d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 32) USART Control A. <br /></td></tr>
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__IO <a class="el" href="unionSERCOM__USART__CTRLB__Type.html">SERCOM_USART_CTRLB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#a13f48d6962c20b0fbbc697b339b24637">CTRLB</a></td></tr>
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<tr class="memdesc:a13f48d6962c20b0fbbc697b339b24637"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 32) USART Control B. <br /></td></tr>
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__IO <a class="el" href="unionSERCOM__USART__CTRLC__Type.html">SERCOM_USART_CTRLC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#a842428ce820db74cf8d48171b49299e5">CTRLC</a></td></tr>
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<tr class="memdesc:a842428ce820db74cf8d48171b49299e5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 32) USART Control C. <br /></td></tr>
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__IO <a class="el" href="unionSERCOM__USART__BAUD__Type.html">SERCOM_USART_BAUD_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#a9a8765c0b1cc714d92655d120b616aea">BAUD</a></td></tr>
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<tr class="memdesc:a9a8765c0b1cc714d92655d120b616aea"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 16) USART Baud Rate. <br /></td></tr>
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__IO <a class="el" href="unionSERCOM__USART__RXPL__Type.html">SERCOM_USART_RXPL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#a8691431cde63ebb8e0529496d808f616">RXPL</a></td></tr>
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<tr class="memdesc:a8691431cde63ebb8e0529496d808f616"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0E (R/W 8) USART Receive Pulse Length. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x5]</td></tr>
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__IO <a class="el" href="unionSERCOM__USART__INTENCLR__Type.html">SERCOM_USART_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#a41bd9a7bd443197a9177357eb122dfb1">INTENCLR</a></td></tr>
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<tr class="memdesc:a41bd9a7bd443197a9177357eb122dfb1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 8) USART Interrupt Enable Clear. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x1]</td></tr>
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__IO <a class="el" href="unionSERCOM__USART__INTENSET__Type.html">SERCOM_USART_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#a1ac4a7c27bab21a1bfd18aa9aaea176b">INTENSET</a></td></tr>
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<tr class="memdesc:a1ac4a7c27bab21a1bfd18aa9aaea176b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x16 (R/W 8) USART Interrupt Enable Set. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x1]</td></tr>
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__IO <a class="el" href="unionSERCOM__USART__INTFLAG__Type.html">SERCOM_USART_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#aeddd2226c1eec2dc16bb85bb57dcb986">INTFLAG</a></td></tr>
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<tr class="memdesc:aeddd2226c1eec2dc16bb85bb57dcb986"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved4</b> [0x1]</td></tr>
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<tr class="separator:a29c5a6d40bd692d00c8a4581c9104522"><td class="memSeparator" colspan="2"> </td></tr>
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__IO <a class="el" href="unionSERCOM__USART__STATUS__Type.html">SERCOM_USART_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#aec9dc41e7c3727dcb02b794159f115da">STATUS</a></td></tr>
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<tr class="memdesc:aec9dc41e7c3727dcb02b794159f115da"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1A (R/W 16) USART Status. <br /></td></tr>
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<tr class="memitem:ac487a89bcf95684f4d9259492d7d8cc5"><td class="memItemLeft" align="right" valign="top"><a id="ac487a89bcf95684f4d9259492d7d8cc5"></a>
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__I <a class="el" href="unionSERCOM__USART__SYNCBUSY__Type.html">SERCOM_USART_SYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#ac487a89bcf95684f4d9259492d7d8cc5">SYNCBUSY</a></td></tr>
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<tr class="memdesc:ac487a89bcf95684f4d9259492d7d8cc5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/ 32) USART Synchronization Busy. <br /></td></tr>
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<tr class="memitem:a7a2f2876b3ab52e9a07f424551d4d9cb"><td class="memItemLeft" align="right" valign="top"><a id="a7a2f2876b3ab52e9a07f424551d4d9cb"></a>
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__I <a class="el" href="unionSERCOM__USART__RXERRCNT__Type.html">SERCOM_USART_RXERRCNT_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#a7a2f2876b3ab52e9a07f424551d4d9cb">RXERRCNT</a></td></tr>
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<tr class="memdesc:a7a2f2876b3ab52e9a07f424551d4d9cb"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x20 (R/ 8) USART Receive Error Count. <br /></td></tr>
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<tr class="memitem:aab6316b40a2a0e231392ed2a2a4e9642"><td class="memItemLeft" align="right" valign="top"><a id="aab6316b40a2a0e231392ed2a2a4e9642"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved5</b> [0x1]</td></tr>
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<tr class="memitem:afaebddcec542423a7404759bf2793e1e"><td class="memItemLeft" align="right" valign="top"><a id="afaebddcec542423a7404759bf2793e1e"></a>
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__IO <a class="el" href="unionSERCOM__USART__LENGTH__Type.html">SERCOM_USART_LENGTH_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#afaebddcec542423a7404759bf2793e1e">LENGTH</a></td></tr>
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<tr class="memdesc:afaebddcec542423a7404759bf2793e1e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x22 (R/W 16) USART Length. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved6</b> [0x4]</td></tr>
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<tr class="memitem:a50fd58032f505c3c27f235809bc85e23"><td class="memItemLeft" align="right" valign="top"><a id="a50fd58032f505c3c27f235809bc85e23"></a>
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__IO <a class="el" href="unionSERCOM__USART__DATA__Type.html">SERCOM_USART_DATA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#a50fd58032f505c3c27f235809bc85e23">DATA</a></td></tr>
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<tr class="memdesc:a50fd58032f505c3c27f235809bc85e23"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x28 (R/W 32) USART Data. <br /></td></tr>
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<tr class="memitem:aec63d76279664217148c428d3c43c94b"><td class="memItemLeft" align="right" valign="top"><a id="aec63d76279664217148c428d3c43c94b"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved7</b> [0x4]</td></tr>
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<tr class="separator:aec63d76279664217148c428d3c43c94b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad8b879e69131449d6cc726b444772065"><td class="memItemLeft" align="right" valign="top"><a id="ad8b879e69131449d6cc726b444772065"></a>
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__IO <a class="el" href="unionSERCOM__USART__DBGCTRL__Type.html">SERCOM_USART_DBGCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomUsart.html#ad8b879e69131449d6cc726b444772065">DBGCTRL</a></td></tr>
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<tr class="memdesc:ad8b879e69131449d6cc726b444772065"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 (R/W 8) USART Debug Control. <br /></td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>SERCOM_USART hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="sercom_8h_source.html#l01644">1644</a> of file <a class="el" href="sercom_8h_source.html">sercom.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="sercom_8h_source.html">sercom.h</a></li>
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</ul>
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