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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">SercomSpi Struct Reference</div> </div>
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<p>SERCOM_SPI hardware registers.
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<a href="structSercomSpi.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="sercom_8h_source.html">sercom.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a6b5ceac8734777daa2c939a528bd8d7a"><td class="memItemLeft" align="right" valign="top"><a id="a6b5ceac8734777daa2c939a528bd8d7a"></a>
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__IO <a class="el" href="unionSERCOM__SPI__CTRLA__Type.html">SERCOM_SPI_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#a6b5ceac8734777daa2c939a528bd8d7a">CTRLA</a></td></tr>
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<tr class="memdesc:a6b5ceac8734777daa2c939a528bd8d7a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 32) SPI Control A. <br /></td></tr>
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__IO <a class="el" href="unionSERCOM__SPI__CTRLB__Type.html">SERCOM_SPI_CTRLB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#a82682944a4341eac7e7cead927114f27">CTRLB</a></td></tr>
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<tr class="memdesc:a82682944a4341eac7e7cead927114f27"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 32) SPI Control B. <br /></td></tr>
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__IO <a class="el" href="unionSERCOM__SPI__CTRLC__Type.html">SERCOM_SPI_CTRLC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#aee02e14b6e6984e182a88a0bbab2ab9b">CTRLC</a></td></tr>
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<tr class="memdesc:aee02e14b6e6984e182a88a0bbab2ab9b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 32) SPI Control C. <br /></td></tr>
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__IO <a class="el" href="unionSERCOM__SPI__BAUD__Type.html">SERCOM_SPI_BAUD_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#ae3617d06a12a777081ef2bea85b1fd79">BAUD</a></td></tr>
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<tr class="memdesc:ae3617d06a12a777081ef2bea85b1fd79"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 8) SPI Baud Rate. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x7]</td></tr>
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__IO <a class="el" href="unionSERCOM__SPI__INTENCLR__Type.html">SERCOM_SPI_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#a447e3f476bf3805f1ac0729f5751e249">INTENCLR</a></td></tr>
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<tr class="memdesc:a447e3f476bf3805f1ac0729f5751e249"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x1]</td></tr>
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<tr class="memitem:a746460fa2d29ff5cf5859a7e120823e9"><td class="memItemLeft" align="right" valign="top"><a id="a746460fa2d29ff5cf5859a7e120823e9"></a>
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__IO <a class="el" href="unionSERCOM__SPI__INTENSET__Type.html">SERCOM_SPI_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#a746460fa2d29ff5cf5859a7e120823e9">INTENSET</a></td></tr>
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<tr class="memdesc:a746460fa2d29ff5cf5859a7e120823e9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x16 (R/W 8) SPI Interrupt Enable Set. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x1]</td></tr>
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<tr class="memitem:aa8972f8e6759af48a837664cbc55f3e0"><td class="memItemLeft" align="right" valign="top"><a id="aa8972f8e6759af48a837664cbc55f3e0"></a>
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__IO <a class="el" href="unionSERCOM__SPI__INTFLAG__Type.html">SERCOM_SPI_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#aa8972f8e6759af48a837664cbc55f3e0">INTFLAG</a></td></tr>
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<tr class="memdesc:aa8972f8e6759af48a837664cbc55f3e0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved4</b> [0x1]</td></tr>
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<tr class="separator:ab81d843802be80bbb21dfbc06f3ce9bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6bb0888f1297cca734fc8f625fa9ca0f"><td class="memItemLeft" align="right" valign="top"><a id="a6bb0888f1297cca734fc8f625fa9ca0f"></a>
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__IO <a class="el" href="unionSERCOM__SPI__STATUS__Type.html">SERCOM_SPI_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#a6bb0888f1297cca734fc8f625fa9ca0f">STATUS</a></td></tr>
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<tr class="memdesc:a6bb0888f1297cca734fc8f625fa9ca0f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1A (R/W 16) SPI Status. <br /></td></tr>
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<tr class="separator:a6bb0888f1297cca734fc8f625fa9ca0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae5172768f1e8016b3d898ffde1d0d47f"><td class="memItemLeft" align="right" valign="top"><a id="ae5172768f1e8016b3d898ffde1d0d47f"></a>
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__I <a class="el" href="unionSERCOM__SPI__SYNCBUSY__Type.html">SERCOM_SPI_SYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#ae5172768f1e8016b3d898ffde1d0d47f">SYNCBUSY</a></td></tr>
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<tr class="memdesc:ae5172768f1e8016b3d898ffde1d0d47f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/ 32) SPI Synchronization Busy. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved5</b> [0x2]</td></tr>
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<tr class="separator:a22c41b61ce17c9af40e3d98f767b7b26"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a18f51e8281c8163249bd8f38fc47a65b"><td class="memItemLeft" align="right" valign="top"><a id="a18f51e8281c8163249bd8f38fc47a65b"></a>
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__IO <a class="el" href="unionSERCOM__SPI__LENGTH__Type.html">SERCOM_SPI_LENGTH_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#a18f51e8281c8163249bd8f38fc47a65b">LENGTH</a></td></tr>
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<tr class="memdesc:a18f51e8281c8163249bd8f38fc47a65b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x22 (R/W 16) SPI Length. <br /></td></tr>
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<tr class="memitem:a928810e5e30da98caef3da7c1c16b1bc"><td class="memItemLeft" align="right" valign="top"><a id="a928810e5e30da98caef3da7c1c16b1bc"></a>
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__IO <a class="el" href="unionSERCOM__SPI__ADDR__Type.html">SERCOM_SPI_ADDR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#a928810e5e30da98caef3da7c1c16b1bc">ADDR</a></td></tr>
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<tr class="memdesc:a928810e5e30da98caef3da7c1c16b1bc"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x24 (R/W 32) SPI Address. <br /></td></tr>
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<tr class="memitem:a427dacdb6fab86af3e318a7ff97ef7d3"><td class="memItemLeft" align="right" valign="top"><a id="a427dacdb6fab86af3e318a7ff97ef7d3"></a>
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__IO <a class="el" href="unionSERCOM__SPI__DATA__Type.html">SERCOM_SPI_DATA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#a427dacdb6fab86af3e318a7ff97ef7d3">DATA</a></td></tr>
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<tr class="memdesc:a427dacdb6fab86af3e318a7ff97ef7d3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x28 (R/W 32) SPI Data. <br /></td></tr>
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<tr class="memitem:acc86858be3e30a23d223dc2c5e10fa50"><td class="memItemLeft" align="right" valign="top"><a id="acc86858be3e30a23d223dc2c5e10fa50"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved6</b> [0x4]</td></tr>
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<tr class="memitem:a01c414f8fb8404c72c2ecc5544469980"><td class="memItemLeft" align="right" valign="top"><a id="a01c414f8fb8404c72c2ecc5544469980"></a>
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__IO <a class="el" href="unionSERCOM__SPI__DBGCTRL__Type.html">SERCOM_SPI_DBGCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomSpi.html#a01c414f8fb8404c72c2ecc5544469980">DBGCTRL</a></td></tr>
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<tr class="memdesc:a01c414f8fb8404c72c2ecc5544469980"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 (R/W 8) SPI Debug Control. <br /></td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>SERCOM_SPI hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="sercom_8h_source.html#l01619">1619</a> of file <a class="el" href="sercom_8h_source.html">sercom.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="sercom_8h_source.html">sercom.h</a></li>
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</ul>
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