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$(function() {
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initMenu('',true,false,'search.php','Search');
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});
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onmouseover="return searchBox.OnSearchSelectShow()"
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onkeydown="return searchBox.OnSearchSelectKey(event)">
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Sdhc Struct Reference</div> </div>
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<p>SDHC hardware registers.
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<a href="structSdhc.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="sdhc_8h_source.html">sdhc.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a070212a369866069c779d3d625c73c5a"><td class="memItemLeft" align="right" valign="top"><a id="a070212a369866069c779d3d625c73c5a"></a>
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__IO <a class="el" href="unionSDHC__SSAR__Type.html">SDHC_SSAR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a070212a369866069c779d3d625c73c5a">SSAR</a></td></tr>
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<tr class="memdesc:a070212a369866069c779d3d625c73c5a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W 32) SDMA System Address / Argument 2. <br /></td></tr>
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<tr class="separator:a070212a369866069c779d3d625c73c5a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a59ba6630d2d6b5b4a376b8b2c25e0e59"><td class="memItemLeft" align="right" valign="top"><a id="a59ba6630d2d6b5b4a376b8b2c25e0e59"></a>
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__IO <a class="el" href="unionSDHC__BSR__Type.html">SDHC_BSR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a59ba6630d2d6b5b4a376b8b2c25e0e59">BSR</a></td></tr>
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<tr class="memdesc:a59ba6630d2d6b5b4a376b8b2c25e0e59"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W 16) Block Size. <br /></td></tr>
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<tr class="separator:a59ba6630d2d6b5b4a376b8b2c25e0e59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6f8f6ea8aabbab1b73c9fdab764197ee"><td class="memItemLeft" align="right" valign="top"><a id="a6f8f6ea8aabbab1b73c9fdab764197ee"></a>
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__IO <a class="el" href="unionSDHC__BCR__Type.html">SDHC_BCR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a6f8f6ea8aabbab1b73c9fdab764197ee">BCR</a></td></tr>
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<tr class="memdesc:a6f8f6ea8aabbab1b73c9fdab764197ee"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x006 (R/W 16) Block Count. <br /></td></tr>
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<tr class="separator:a6f8f6ea8aabbab1b73c9fdab764197ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a89a5b2a5ffa53e84294fe68a4911d405"><td class="memItemLeft" align="right" valign="top"><a id="a89a5b2a5ffa53e84294fe68a4911d405"></a>
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__IO <a class="el" href="unionSDHC__ARG1R__Type.html">SDHC_ARG1R_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a89a5b2a5ffa53e84294fe68a4911d405">ARG1R</a></td></tr>
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<tr class="memdesc:a89a5b2a5ffa53e84294fe68a4911d405"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W 32) Argument 1. <br /></td></tr>
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<tr class="separator:a89a5b2a5ffa53e84294fe68a4911d405"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab53744d61e7d3a7bbed9f300b296a9d1"><td class="memItemLeft" align="right" valign="top"><a id="ab53744d61e7d3a7bbed9f300b296a9d1"></a>
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__IO <a class="el" href="unionSDHC__TMR__Type.html">SDHC_TMR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#ab53744d61e7d3a7bbed9f300b296a9d1">TMR</a></td></tr>
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<tr class="memdesc:ab53744d61e7d3a7bbed9f300b296a9d1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W 16) Transfer Mode. <br /></td></tr>
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<tr class="separator:ab53744d61e7d3a7bbed9f300b296a9d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acd65c4184a194d80c1dfb1a2a9feb547"><td class="memItemLeft" align="right" valign="top"><a id="acd65c4184a194d80c1dfb1a2a9feb547"></a>
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__IO <a class="el" href="unionSDHC__CR__Type.html">SDHC_CR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#acd65c4184a194d80c1dfb1a2a9feb547">CR</a></td></tr>
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<tr class="memdesc:acd65c4184a194d80c1dfb1a2a9feb547"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00E (R/W 16) Command. <br /></td></tr>
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<tr class="separator:acd65c4184a194d80c1dfb1a2a9feb547"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a79975ceaa50ff01d60741138d6c98065"><td class="memItemLeft" align="right" valign="top"><a id="a79975ceaa50ff01d60741138d6c98065"></a>
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__I <a class="el" href="unionSDHC__RR__Type.html">SDHC_RR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a79975ceaa50ff01d60741138d6c98065">RR</a> [4]</td></tr>
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<tr class="memdesc:a79975ceaa50ff01d60741138d6c98065"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/ 32) Response. <br /></td></tr>
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<tr class="separator:a79975ceaa50ff01d60741138d6c98065"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2e743ac48a95de97af4400cc46470147"><td class="memItemLeft" align="right" valign="top"><a id="a2e743ac48a95de97af4400cc46470147"></a>
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__IO <a class="el" href="unionSDHC__BDPR__Type.html">SDHC_BDPR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a2e743ac48a95de97af4400cc46470147">BDPR</a></td></tr>
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<tr class="memdesc:a2e743ac48a95de97af4400cc46470147"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x020 (R/W 32) Buffer Data <a class="el" href="structPort.html" title="PORT hardware registers.">Port</a>. <br /></td></tr>
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<tr class="separator:a2e743ac48a95de97af4400cc46470147"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4434057082a55207b61bf35cef90f62a"><td class="memItemLeft" align="right" valign="top"><a id="a4434057082a55207b61bf35cef90f62a"></a>
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__I <a class="el" href="unionSDHC__PSR__Type.html">SDHC_PSR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a4434057082a55207b61bf35cef90f62a">PSR</a></td></tr>
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<tr class="memdesc:a4434057082a55207b61bf35cef90f62a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 (R/ 32) Present State. <br /></td></tr>
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<tr class="separator:a4434057082a55207b61bf35cef90f62a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1bf67e3e42d5f4bcb463f3ca08d8f7a5"><td class="memItemLeft" align="right" valign="top"><a id="a1bf67e3e42d5f4bcb463f3ca08d8f7a5"></a>
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__IO <a class="el" href="unionSDHC__HC1R__Type.html">SDHC_HC1R_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a1bf67e3e42d5f4bcb463f3ca08d8f7a5">HC1R</a></td></tr>
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<tr class="memdesc:a1bf67e3e42d5f4bcb463f3ca08d8f7a5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x028 (R/W 8) Host Control 1. <br /></td></tr>
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<tr class="separator:a1bf67e3e42d5f4bcb463f3ca08d8f7a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a70f02b061b959ea53bf99bbd2c7e493d"><td class="memItemLeft" align="right" valign="top"><a id="a70f02b061b959ea53bf99bbd2c7e493d"></a>
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__IO <a class="el" href="unionSDHC__PCR__Type.html">SDHC_PCR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a70f02b061b959ea53bf99bbd2c7e493d">PCR</a></td></tr>
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<tr class="memdesc:a70f02b061b959ea53bf99bbd2c7e493d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x029 (R/W 8) Power Control. <br /></td></tr>
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<tr class="separator:a70f02b061b959ea53bf99bbd2c7e493d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a411747fd98b27952758552020779cc4f"><td class="memItemLeft" align="right" valign="top"><a id="a411747fd98b27952758552020779cc4f"></a>
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__IO <a class="el" href="unionSDHC__BGCR__Type.html">SDHC_BGCR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a411747fd98b27952758552020779cc4f">BGCR</a></td></tr>
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<tr class="memdesc:a411747fd98b27952758552020779cc4f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02A (R/W 8) Block Gap Control. <br /></td></tr>
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<tr class="separator:a411747fd98b27952758552020779cc4f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d12718e83da406180da44458bf3c0b1"><td class="memItemLeft" align="right" valign="top"><a id="a2d12718e83da406180da44458bf3c0b1"></a>
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__IO <a class="el" href="unionSDHC__WCR__Type.html">SDHC_WCR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a2d12718e83da406180da44458bf3c0b1">WCR</a></td></tr>
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<tr class="memdesc:a2d12718e83da406180da44458bf3c0b1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02B (R/W 8) Wakeup Control. <br /></td></tr>
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<tr class="separator:a2d12718e83da406180da44458bf3c0b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2b93d35322ff7d9e8119a5e935c64d35"><td class="memItemLeft" align="right" valign="top"><a id="a2b93d35322ff7d9e8119a5e935c64d35"></a>
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__IO <a class="el" href="unionSDHC__CCR__Type.html">SDHC_CCR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a2b93d35322ff7d9e8119a5e935c64d35">CCR</a></td></tr>
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<tr class="memdesc:a2b93d35322ff7d9e8119a5e935c64d35"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02C (R/W 16) Clock Control. <br /></td></tr>
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<tr class="separator:a2b93d35322ff7d9e8119a5e935c64d35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4882d54895d7cb3ecf9f7bb0613bca81"><td class="memItemLeft" align="right" valign="top"><a id="a4882d54895d7cb3ecf9f7bb0613bca81"></a>
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__IO <a class="el" href="unionSDHC__TCR__Type.html">SDHC_TCR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a4882d54895d7cb3ecf9f7bb0613bca81">TCR</a></td></tr>
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<tr class="memdesc:a4882d54895d7cb3ecf9f7bb0613bca81"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02E (R/W 8) Timeout Control. <br /></td></tr>
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<tr class="separator:a4882d54895d7cb3ecf9f7bb0613bca81"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1d4478a8a443a6d888bf0d357b83ead5"><td class="memItemLeft" align="right" valign="top"><a id="a1d4478a8a443a6d888bf0d357b83ead5"></a>
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__IO <a class="el" href="unionSDHC__SRR__Type.html">SDHC_SRR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a1d4478a8a443a6d888bf0d357b83ead5">SRR</a></td></tr>
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<tr class="memdesc:a1d4478a8a443a6d888bf0d357b83ead5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02F (R/W 8) Software Reset. <br /></td></tr>
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<tr class="separator:a1d4478a8a443a6d888bf0d357b83ead5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acf9f58587e04851bacc1d91079e81b32"><td class="memItemLeft" align="right" valign="top"><a id="acf9f58587e04851bacc1d91079e81b32"></a>
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__IO <a class="el" href="unionSDHC__NISTR__Type.html">SDHC_NISTR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#acf9f58587e04851bacc1d91079e81b32">NISTR</a></td></tr>
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<tr class="memdesc:acf9f58587e04851bacc1d91079e81b32"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x030 (R/W 16) Normal Interrupt Status. <br /></td></tr>
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<tr class="separator:acf9f58587e04851bacc1d91079e81b32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad8f8c9fca271cad54aee4624cd04349"><td class="memItemLeft" align="right" valign="top"><a id="aad8f8c9fca271cad54aee4624cd04349"></a>
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__IO <a class="el" href="unionSDHC__EISTR__Type.html">SDHC_EISTR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#aad8f8c9fca271cad54aee4624cd04349">EISTR</a></td></tr>
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<tr class="memdesc:aad8f8c9fca271cad54aee4624cd04349"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x032 (R/W 16) Error Interrupt Status. <br /></td></tr>
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<tr class="separator:aad8f8c9fca271cad54aee4624cd04349"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af3e4658556b475655f9e5f66bb185644"><td class="memItemLeft" align="right" valign="top"><a id="af3e4658556b475655f9e5f66bb185644"></a>
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__IO <a class="el" href="unionSDHC__NISTER__Type.html">SDHC_NISTER_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#af3e4658556b475655f9e5f66bb185644">NISTER</a></td></tr>
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<tr class="memdesc:af3e4658556b475655f9e5f66bb185644"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x034 (R/W 16) Normal Interrupt Status Enable. <br /></td></tr>
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<tr class="separator:af3e4658556b475655f9e5f66bb185644"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1f30c196f524e73f94d08b5b86e177e1"><td class="memItemLeft" align="right" valign="top"><a id="a1f30c196f524e73f94d08b5b86e177e1"></a>
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__IO <a class="el" href="unionSDHC__EISTER__Type.html">SDHC_EISTER_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a1f30c196f524e73f94d08b5b86e177e1">EISTER</a></td></tr>
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<tr class="memdesc:a1f30c196f524e73f94d08b5b86e177e1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x036 (R/W 16) Error Interrupt Status Enable. <br /></td></tr>
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<tr class="separator:a1f30c196f524e73f94d08b5b86e177e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afdd268f6b489d081c4267344572c4dad"><td class="memItemLeft" align="right" valign="top"><a id="afdd268f6b489d081c4267344572c4dad"></a>
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__IO <a class="el" href="unionSDHC__NISIER__Type.html">SDHC_NISIER_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#afdd268f6b489d081c4267344572c4dad">NISIER</a></td></tr>
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<tr class="memdesc:afdd268f6b489d081c4267344572c4dad"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x038 (R/W 16) Normal Interrupt Signal Enable. <br /></td></tr>
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<tr class="separator:afdd268f6b489d081c4267344572c4dad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa558f67af1bb27b82188e52275567ab6"><td class="memItemLeft" align="right" valign="top"><a id="aa558f67af1bb27b82188e52275567ab6"></a>
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__IO <a class="el" href="unionSDHC__EISIER__Type.html">SDHC_EISIER_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#aa558f67af1bb27b82188e52275567ab6">EISIER</a></td></tr>
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<tr class="memdesc:aa558f67af1bb27b82188e52275567ab6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x03A (R/W 16) Error Interrupt Signal Enable. <br /></td></tr>
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__I <a class="el" href="unionSDHC__ACESR__Type.html">SDHC_ACESR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a156c75cfce8dc1ff1b50d4733d8791d8">ACESR</a></td></tr>
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<tr class="memdesc:a156c75cfce8dc1ff1b50d4733d8791d8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x03C (R/ 16) Auto CMD Error Status. <br /></td></tr>
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__IO <a class="el" href="unionSDHC__HC2R__Type.html">SDHC_HC2R_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#ae127cfd080359c4ac12d577b0a37c62b">HC2R</a></td></tr>
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<tr class="memdesc:ae127cfd080359c4ac12d577b0a37c62b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x03E (R/W 16) Host Control 2. <br /></td></tr>
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__I <a class="el" href="unionSDHC__CA0R__Type.html">SDHC_CA0R_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#affbc2dfe365d7a03c4e5a1eb2c40f4cf">CA0R</a></td></tr>
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<tr class="memdesc:affbc2dfe365d7a03c4e5a1eb2c40f4cf"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x040 (R/ 32) Capabilities 0. <br /></td></tr>
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__I <a class="el" href="unionSDHC__CA1R__Type.html">SDHC_CA1R_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#acbcf5f2b979aad2d608d2d5f4e201058">CA1R</a></td></tr>
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<tr class="memdesc:acbcf5f2b979aad2d608d2d5f4e201058"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x044 (R/ 32) Capabilities 1. <br /></td></tr>
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__I <a class="el" href="unionSDHC__MCCAR__Type.html">SDHC_MCCAR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#afff46b235f0390e6b361b0ac08c4131a">MCCAR</a></td></tr>
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<tr class="memdesc:afff46b235f0390e6b361b0ac08c4131a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x048 (R/ 32) Maximum Current Capabilities. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x4]</td></tr>
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__O <a class="el" href="unionSDHC__FERACES__Type.html">SDHC_FERACES_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a2c038b5c61b50be78a233d9f32390010">FERACES</a></td></tr>
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<tr class="memdesc:a2c038b5c61b50be78a233d9f32390010"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x050 ( /W 16) Force Event for Auto CMD Error Status. <br /></td></tr>
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__O <a class="el" href="unionSDHC__FEREIS__Type.html">SDHC_FEREIS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a44bc2b90bd693ec2aebd11501f2059e8">FEREIS</a></td></tr>
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<tr class="memdesc:a44bc2b90bd693ec2aebd11501f2059e8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x052 ( /W 16) Force Event for Error Interrupt Status. <br /></td></tr>
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__I <a class="el" href="unionSDHC__AESR__Type.html">SDHC_AESR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a5ff7854bf47236e6b24198f50d16a9ae">AESR</a></td></tr>
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<tr class="memdesc:a5ff7854bf47236e6b24198f50d16a9ae"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x054 (R/ 8) ADMA Error Status. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x3]</td></tr>
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<tr class="memitem:ad96d69be33f8fd7a24a6f1526b17c066"><td class="memItemLeft" align="right" valign="top"><a id="ad96d69be33f8fd7a24a6f1526b17c066"></a>
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__IO <a class="el" href="unionSDHC__ASAR__Type.html">SDHC_ASAR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#ad96d69be33f8fd7a24a6f1526b17c066">ASAR</a> [1]</td></tr>
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<tr class="memdesc:ad96d69be33f8fd7a24a6f1526b17c066"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x058 (R/W 32) ADMA System Address n. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x4]</td></tr>
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__IO <a class="el" href="unionSDHC__PVR__Type.html">SDHC_PVR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#af0a59141d2f88e040c08335613197a7d">PVR</a> [8]</td></tr>
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<tr class="memdesc:af0a59141d2f88e040c08335613197a7d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x060 (R/W 16) Preset Value n. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved4</b> [0x8C]</td></tr>
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<tr class="memitem:ad7e62fbc1c367146592bd5095f6af180"><td class="memItemLeft" align="right" valign="top"><a id="ad7e62fbc1c367146592bd5095f6af180"></a>
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__I <a class="el" href="unionSDHC__SISR__Type.html">SDHC_SISR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#ad7e62fbc1c367146592bd5095f6af180">SISR</a></td></tr>
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<tr class="memdesc:ad7e62fbc1c367146592bd5095f6af180"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0FC (R/ 16) Slot Interrupt Status. <br /></td></tr>
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__I <a class="el" href="unionSDHC__HCVR__Type.html">SDHC_HCVR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a939d29db6ed07054f0cbc7920ed94b06">HCVR</a></td></tr>
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<tr class="memdesc:a939d29db6ed07054f0cbc7920ed94b06"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0FE (R/ 16) Host Controller Version. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved5</b> [0x104]</td></tr>
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__IO <a class="el" href="unionSDHC__MC1R__Type.html">SDHC_MC1R_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#ad825e5d75852893a9591060235dea33d">MC1R</a></td></tr>
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<tr class="memdesc:ad825e5d75852893a9591060235dea33d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x204 (R/W 8) MMC Control 1. <br /></td></tr>
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__O <a class="el" href="unionSDHC__MC2R__Type.html">SDHC_MC2R_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a7f7b113ddba11bcd5d6c66283a06a616">MC2R</a></td></tr>
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<tr class="memdesc:a7f7b113ddba11bcd5d6c66283a06a616"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x205 ( /W 8) MMC Control 2. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved6</b> [0x2]</td></tr>
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<tr class="memitem:a9db63cd10e808ca6091441955a5aad79"><td class="memItemLeft" align="right" valign="top"><a id="a9db63cd10e808ca6091441955a5aad79"></a>
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__IO <a class="el" href="unionSDHC__ACR__Type.html">SDHC_ACR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a9db63cd10e808ca6091441955a5aad79">ACR</a></td></tr>
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<tr class="memdesc:a9db63cd10e808ca6091441955a5aad79"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x208 (R/W 32) AHB Control. <br /></td></tr>
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__IO <a class="el" href="unionSDHC__CC2R__Type.html">SDHC_CC2R_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a00bd6a8653fcc814e41d7d0cefacf7d8">CC2R</a></td></tr>
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<tr class="memdesc:a00bd6a8653fcc814e41d7d0cefacf7d8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x20C (R/W 32) Clock Control 2. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved7</b> [0x20]</td></tr>
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<tr class="memitem:a5fd2a4796f96d67567310c6c12c57080"><td class="memItemLeft" align="right" valign="top"><a id="a5fd2a4796f96d67567310c6c12c57080"></a>
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__IO <a class="el" href="unionSDHC__CACR__Type.html">SDHC_CACR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#a5fd2a4796f96d67567310c6c12c57080">CACR</a></td></tr>
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<tr class="memdesc:a5fd2a4796f96d67567310c6c12c57080"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x230 (R/W 32) Capabilities Control. <br /></td></tr>
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<tr class="memitem:ac9c54e01b4e13d59ddc203bc20046712"><td class="memItemLeft" align="right" valign="top"><a id="ac9c54e01b4e13d59ddc203bc20046712"></a>
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__IO <a class="el" href="unionSDHC__DBGR__Type.html">SDHC_DBGR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSdhc.html#ac9c54e01b4e13d59ddc203bc20046712">DBGR</a></td></tr>
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<tr class="memdesc:ac9c54e01b4e13d59ddc203bc20046712"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x234 (R/W 8) Debug. <br /></td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>SDHC hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="sdhc_8h_source.html#l02546">2546</a> of file <a class="el" href="sdhc_8h_source.html">sdhc.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="sdhc_8h_source.html">sdhc.h</a></li>
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</ul>
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