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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Qspi Struct Reference</div> </div>
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<p>QSPI APB hardware registers.
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<a href="structQspi.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="component_2qspi_8h_source.html">qspi.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a036135899d8b56cb0da657f92fd7f33b"><td class="memItemLeft" align="right" valign="top"><a id="a036135899d8b56cb0da657f92fd7f33b"></a>
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__IO <a class="el" href="unionQSPI__CTRLA__Type.html">QSPI_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#a036135899d8b56cb0da657f92fd7f33b">CTRLA</a></td></tr>
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<tr class="memdesc:a036135899d8b56cb0da657f92fd7f33b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 32) Control A. <br /></td></tr>
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__IO <a class="el" href="unionQSPI__CTRLB__Type.html">QSPI_CTRLB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#ad82456fa96981795d4d4dc4c737fe477">CTRLB</a></td></tr>
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<tr class="memdesc:ad82456fa96981795d4d4dc4c737fe477"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 32) Control B. <br /></td></tr>
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__IO <a class="el" href="unionQSPI__BAUD__Type.html">QSPI_BAUD_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#a8ffd9fd736eb1904a3bac44c74d38e86">BAUD</a></td></tr>
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<tr class="memdesc:a8ffd9fd736eb1904a3bac44c74d38e86"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 32) Baud Rate. <br /></td></tr>
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__I <a class="el" href="unionQSPI__RXDATA__Type.html">QSPI_RXDATA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#a6575f26e79b6630b2f204db527ed6e02">RXDATA</a></td></tr>
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<tr class="memdesc:a6575f26e79b6630b2f204db527ed6e02"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/ 32) Receive Data. <br /></td></tr>
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<tr class="memdesc:a337729f71a0cefe9e7846257d114ec33"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 ( /W 32) Transmit Data. <br /></td></tr>
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__IO <a class="el" href="unionQSPI__INTENCLR__Type.html">QSPI_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#ac87eada8e9fb313301f67cbc40c93eb3">INTENCLR</a></td></tr>
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<tr class="memdesc:ac87eada8e9fb313301f67cbc40c93eb3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 32) Interrupt Enable Clear. <br /></td></tr>
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__IO <a class="el" href="unionQSPI__INTENSET__Type.html">QSPI_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#a87ffbe45eb4baaebac25849d60fec1b7">INTENSET</a></td></tr>
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<tr class="memdesc:a87ffbe45eb4baaebac25849d60fec1b7"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x18 (R/W 32) Interrupt Enable Set. <br /></td></tr>
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__IO <a class="el" href="unionQSPI__INTFLAG__Type.html">QSPI_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#aec5e882df9b5ddf5a4398ab89ad4f70c">INTFLAG</a></td></tr>
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<tr class="memdesc:aec5e882df9b5ddf5a4398ab89ad4f70c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear. <br /></td></tr>
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<tr class="memitem:a13817f23c84d3f9db5acaf239d6f4bf6"><td class="memItemLeft" align="right" valign="top"><a id="a13817f23c84d3f9db5acaf239d6f4bf6"></a>
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__I <a class="el" href="unionQSPI__STATUS__Type.html">QSPI_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#a13817f23c84d3f9db5acaf239d6f4bf6">STATUS</a></td></tr>
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<tr class="memdesc:a13817f23c84d3f9db5acaf239d6f4bf6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x20 (R/ 32) Status Register. <br /></td></tr>
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<tr class="memitem:a9134ea944f2d0421ad511d5b5b7a8e9e"><td class="memItemLeft" align="right" valign="top"><a id="a9134ea944f2d0421ad511d5b5b7a8e9e"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0xC]</td></tr>
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<tr class="memitem:a1ca888f8481c2f74f17202f86da43bb4"><td class="memItemLeft" align="right" valign="top"><a id="a1ca888f8481c2f74f17202f86da43bb4"></a>
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__IO <a class="el" href="unionQSPI__INSTRADDR__Type.html">QSPI_INSTRADDR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#a1ca888f8481c2f74f17202f86da43bb4">INSTRADDR</a></td></tr>
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<tr class="memdesc:a1ca888f8481c2f74f17202f86da43bb4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 (R/W 32) Instruction Address. <br /></td></tr>
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<tr class="memitem:a028aaca0f980cadda025f73b78702bdd"><td class="memItemLeft" align="right" valign="top"><a id="a028aaca0f980cadda025f73b78702bdd"></a>
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__IO <a class="el" href="unionQSPI__INSTRCTRL__Type.html">QSPI_INSTRCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#a028aaca0f980cadda025f73b78702bdd">INSTRCTRL</a></td></tr>
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<tr class="memdesc:a028aaca0f980cadda025f73b78702bdd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x34 (R/W 32) Instruction Code. <br /></td></tr>
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<tr class="memitem:a4caceb6a280cbde82946b99189c08438"><td class="memItemLeft" align="right" valign="top"><a id="a4caceb6a280cbde82946b99189c08438"></a>
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__IO <a class="el" href="unionQSPI__INSTRFRAME__Type.html">QSPI_INSTRFRAME_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#a4caceb6a280cbde82946b99189c08438">INSTRFRAME</a></td></tr>
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<tr class="memdesc:a4caceb6a280cbde82946b99189c08438"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x38 (R/W 32) Instruction Frame. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x4]</td></tr>
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<tr class="separator:a236ba832e9c68d6921c35df151db3d78"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad55fe0189a3683730f5cc1b3db933dec"><td class="memItemLeft" align="right" valign="top"><a id="ad55fe0189a3683730f5cc1b3db933dec"></a>
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__IO <a class="el" href="unionQSPI__SCRAMBCTRL__Type.html">QSPI_SCRAMBCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#ad55fe0189a3683730f5cc1b3db933dec">SCRAMBCTRL</a></td></tr>
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<tr class="memdesc:ad55fe0189a3683730f5cc1b3db933dec"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x40 (R/W 32) Scrambling Mode. <br /></td></tr>
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<tr class="memitem:a1c55f219ca8463e412b8a92bd8250747"><td class="memItemLeft" align="right" valign="top"><a id="a1c55f219ca8463e412b8a92bd8250747"></a>
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__O <a class="el" href="unionQSPI__SCRAMBKEY__Type.html">QSPI_SCRAMBKEY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structQspi.html#a1c55f219ca8463e412b8a92bd8250747">SCRAMBKEY</a></td></tr>
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<tr class="memdesc:a1c55f219ca8463e412b8a92bd8250747"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x44 ( /W 32) Scrambling Key. <br /></td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>QSPI APB hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="component_2qspi_8h_source.html#l00506">506</a> of file <a class="el" href="component_2qspi_8h_source.html">qspi.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2qspi_8h_source.html">qspi.h</a></li>
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