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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Picop Struct Reference</div> </div>
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<p>PICOP hardware registers.
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<a href="structPicop.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="component_2picop_8h_source.html">picop.h</a>></code></p>
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Data Fields</h2></td></tr>
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__IO <a class="el" href="unionPICOP__ID__Type.html">PICOP_ID_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a02bb97b1a6dc30fddc1f7d19a591b13e">ID</a> [8]</td></tr>
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<tr class="memdesc:a1f9f49b07e95fb567650d7ccbbab6725"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 (R/W 32) Control. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x10]</td></tr>
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__IO <a class="el" href="unionPICOP__OCDCONFIG__Type.html">PICOP_OCDCONFIG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#aa9627e4e25ed455d29dae5dc85a00a06">OCDCONFIG</a></td></tr>
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<tr class="memdesc:aa9627e4e25ed455d29dae5dc85a00a06"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x050 (R/W 32) OCD Configuration. <br /></td></tr>
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<tr class="separator:aa9627e4e25ed455d29dae5dc85a00a06"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a56cb6802962d13ef3bf0925d7c51f660"><td class="memItemLeft" align="right" valign="top"><a id="a56cb6802962d13ef3bf0925d7c51f660"></a>
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__IO <a class="el" href="unionPICOP__OCDCONTROL__Type.html">PICOP_OCDCONTROL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a56cb6802962d13ef3bf0925d7c51f660">OCDCONTROL</a></td></tr>
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<tr class="memdesc:a56cb6802962d13ef3bf0925d7c51f660"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x054 (R/W 32) OCD Control. <br /></td></tr>
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__IO <a class="el" href="unionPICOP__OCDSTATUS__Type.html">PICOP_OCDSTATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a90528bf0937031f6d3afc46fae2cf787">OCDSTATUS</a></td></tr>
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<tr class="memdesc:a90528bf0937031f6d3afc46fae2cf787"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x058 (R/W 32) OCD Status and Command. <br /></td></tr>
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<tr class="memitem:a5545b15e0290af0e2cbbdfd583e3e424"><td class="memItemLeft" align="right" valign="top"><a id="a5545b15e0290af0e2cbbdfd583e3e424"></a>
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__IO <a class="el" href="unionPICOP__OCDPC__Type.html">PICOP_OCDPC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a5545b15e0290af0e2cbbdfd583e3e424">OCDPC</a></td></tr>
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<tr class="memdesc:a5545b15e0290af0e2cbbdfd583e3e424"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x05C (R/W 32) ODC Program Counter. <br /></td></tr>
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<tr class="separator:a5545b15e0290af0e2cbbdfd583e3e424"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a34ed43adaf51dec7019c49074b6d326c"><td class="memItemLeft" align="right" valign="top"><a id="a34ed43adaf51dec7019c49074b6d326c"></a>
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__IO <a class="el" href="unionPICOP__OCDFEAT__Type.html">PICOP_OCDFEAT_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a34ed43adaf51dec7019c49074b6d326c">OCDFEAT</a></td></tr>
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<tr class="memdesc:a34ed43adaf51dec7019c49074b6d326c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x060 (R/W 32) OCD Features. <br /></td></tr>
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<tr class="separator:a34ed43adaf51dec7019c49074b6d326c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a58dbae9c94629d5be2b276540aa5f675"><td class="memItemLeft" align="right" valign="top"><a id="a58dbae9c94629d5be2b276540aa5f675"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x4]</td></tr>
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<tr class="separator:a58dbae9c94629d5be2b276540aa5f675"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a789d563e3224a77fc0d88fb2e9ae1297"><td class="memItemLeft" align="right" valign="top"><a id="a789d563e3224a77fc0d88fb2e9ae1297"></a>
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__IO <a class="el" href="unionPICOP__OCDCCNT__Type.html">PICOP_OCDCCNT_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a789d563e3224a77fc0d88fb2e9ae1297">OCDCCNT</a></td></tr>
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<tr class="memdesc:a789d563e3224a77fc0d88fb2e9ae1297"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x068 (R/W 32) OCD Cycle Counter. <br /></td></tr>
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<tr class="separator:a789d563e3224a77fc0d88fb2e9ae1297"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a67114b7b207df640773830db0dfa628f"><td class="memItemLeft" align="right" valign="top"><a id="a67114b7b207df640773830db0dfa628f"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x4]</td></tr>
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<tr class="separator:a67114b7b207df640773830db0dfa628f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a08ed926ced309198a3a93d7f3b453057"><td class="memItemLeft" align="right" valign="top"><a id="a08ed926ced309198a3a93d7f3b453057"></a>
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__IO <a class="el" href="unionPICOP__OCDBPGEN__Type.html">PICOP_OCDBPGEN_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a08ed926ced309198a3a93d7f3b453057">OCDBPGEN</a> [4]</td></tr>
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<tr class="memdesc:a08ed926ced309198a3a93d7f3b453057"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x070 (R/W 32) OCD Breakpoint Generator n. <br /></td></tr>
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<tr class="separator:a08ed926ced309198a3a93d7f3b453057"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0c0165d79f6218707a42f8c91577e034"><td class="memItemLeft" align="right" valign="top"><a id="a0c0165d79f6218707a42f8c91577e034"></a>
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__IO <a class="el" href="unionPICOP__R3R0__Type.html">PICOP_R3R0_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a0c0165d79f6218707a42f8c91577e034">R3R0</a></td></tr>
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<tr class="memdesc:a0c0165d79f6218707a42f8c91577e034"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x080 (R/W 32) R3 to 0. <br /></td></tr>
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<tr class="separator:a0c0165d79f6218707a42f8c91577e034"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af62779f8f5809f01adbc623a152ed614"><td class="memItemLeft" align="right" valign="top"><a id="af62779f8f5809f01adbc623a152ed614"></a>
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__IO <a class="el" href="unionPICOP__R7R4__Type.html">PICOP_R7R4_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#af62779f8f5809f01adbc623a152ed614">R7R4</a></td></tr>
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<tr class="memdesc:af62779f8f5809f01adbc623a152ed614"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x084 (R/W 32) R7 to 4. <br /></td></tr>
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__IO <a class="el" href="unionPICOP__R11R8__Type.html">PICOP_R11R8_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a91385ef4585b1a0fab69bcf11dc69c68">R11R8</a></td></tr>
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<tr class="memdesc:a91385ef4585b1a0fab69bcf11dc69c68"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x088 (R/W 32) R11 to 8. <br /></td></tr>
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<tr class="memitem:a87f8571a9c2e7be31d9a79f799877926"><td class="memItemLeft" align="right" valign="top"><a id="a87f8571a9c2e7be31d9a79f799877926"></a>
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__IO <a class="el" href="unionPICOP__R15R12__Type.html">PICOP_R15R12_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a87f8571a9c2e7be31d9a79f799877926">R15R12</a></td></tr>
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<tr class="memdesc:a87f8571a9c2e7be31d9a79f799877926"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08C (R/W 32) R15 to 12. <br /></td></tr>
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<tr class="separator:a87f8571a9c2e7be31d9a79f799877926"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a196942bfc60fba8076b5d67c12c9ddb0"><td class="memItemLeft" align="right" valign="top"><a id="a196942bfc60fba8076b5d67c12c9ddb0"></a>
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__IO <a class="el" href="unionPICOP__R19R16__Type.html">PICOP_R19R16_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a196942bfc60fba8076b5d67c12c9ddb0">R19R16</a></td></tr>
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<tr class="memdesc:a196942bfc60fba8076b5d67c12c9ddb0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x090 (R/W 32) R19 to 16. <br /></td></tr>
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<tr class="separator:a196942bfc60fba8076b5d67c12c9ddb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af453bf8cf953a6aa86afd3e39ba4a1a2"><td class="memItemLeft" align="right" valign="top"><a id="af453bf8cf953a6aa86afd3e39ba4a1a2"></a>
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__IO <a class="el" href="unionPICOP__R23R20__Type.html">PICOP_R23R20_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#af453bf8cf953a6aa86afd3e39ba4a1a2">R23R20</a></td></tr>
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<tr class="memdesc:af453bf8cf953a6aa86afd3e39ba4a1a2"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x094 (R/W 32) R23 to 20. <br /></td></tr>
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<tr class="separator:af453bf8cf953a6aa86afd3e39ba4a1a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae2e771bb0ad76f346d2d232e16aa0ef6"><td class="memItemLeft" align="right" valign="top"><a id="ae2e771bb0ad76f346d2d232e16aa0ef6"></a>
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__IO <a class="el" href="unionPICOP__R27R24__Type.html">PICOP_R27R24_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#ae2e771bb0ad76f346d2d232e16aa0ef6">R27R24</a></td></tr>
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<tr class="memdesc:ae2e771bb0ad76f346d2d232e16aa0ef6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x098 (R/W 32) R27 to 24: XH, XL, R25, R24. <br /></td></tr>
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<tr class="separator:ae2e771bb0ad76f346d2d232e16aa0ef6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1768e1ba57d37694dd706f142622cc0a"><td class="memItemLeft" align="right" valign="top"><a id="a1768e1ba57d37694dd706f142622cc0a"></a>
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__IO <a class="el" href="unionPICOP__R31R28__Type.html">PICOP_R31R28_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a1768e1ba57d37694dd706f142622cc0a">R31R28</a></td></tr>
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<tr class="memdesc:a1768e1ba57d37694dd706f142622cc0a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x09C (R/W 32) R31 to 28: ZH, ZL, YH, YL. <br /></td></tr>
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<tr class="separator:a1768e1ba57d37694dd706f142622cc0a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a726f15d25e0cce72852da3375b1ae04f"><td class="memItemLeft" align="right" valign="top"><a id="a726f15d25e0cce72852da3375b1ae04f"></a>
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__IO <a class="el" href="unionPICOP__S1S0__Type.html">PICOP_S1S0_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a726f15d25e0cce72852da3375b1ae04f">S1S0</a></td></tr>
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<tr class="memdesc:a726f15d25e0cce72852da3375b1ae04f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0A0 (R/W 32) System Regs 1 to 0: SR. <br /></td></tr>
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<tr class="separator:a726f15d25e0cce72852da3375b1ae04f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:add53643aae577046c29980c7e8b445c9"><td class="memItemLeft" align="right" valign="top"><a id="add53643aae577046c29980c7e8b445c9"></a>
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__IO <a class="el" href="unionPICOP__S3S2__Type.html">PICOP_S3S2_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#add53643aae577046c29980c7e8b445c9">S3S2</a></td></tr>
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<tr class="memdesc:add53643aae577046c29980c7e8b445c9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0A4 (R/W 32) System Regs 3 to 2: CTRL. <br /></td></tr>
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<tr class="separator:add53643aae577046c29980c7e8b445c9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0424733cecb32caa268d74d44e78894a"><td class="memItemLeft" align="right" valign="top"><a id="a0424733cecb32caa268d74d44e78894a"></a>
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__IO <a class="el" href="unionPICOP__S5S4__Type.html">PICOP_S5S4_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a0424733cecb32caa268d74d44e78894a">S5S4</a></td></tr>
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<tr class="memdesc:a0424733cecb32caa268d74d44e78894a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0A8 (R/W 32) System Regs 5 to 4: SREG, CCR. <br /></td></tr>
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<tr class="separator:a0424733cecb32caa268d74d44e78894a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afddf398dcc03f96956ffe63e048668f7"><td class="memItemLeft" align="right" valign="top"><a id="afddf398dcc03f96956ffe63e048668f7"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved4</b> [0x8]</td></tr>
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<tr class="separator:afddf398dcc03f96956ffe63e048668f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8370ed32bf0f8c299085169f07b4bd14"><td class="memItemLeft" align="right" valign="top"><a id="a8370ed32bf0f8c299085169f07b4bd14"></a>
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__IO <a class="el" href="unionPICOP__S11S10__Type.html">PICOP_S11S10_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a8370ed32bf0f8c299085169f07b4bd14">S11S10</a></td></tr>
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<tr class="memdesc:a8370ed32bf0f8c299085169f07b4bd14"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0B4 (R/W 32) System Regs 11 to 10: Immediate. <br /></td></tr>
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<tr class="separator:a8370ed32bf0f8c299085169f07b4bd14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a13f70fef9f202e157ba106f2c56eb4e1"><td class="memItemLeft" align="right" valign="top"><a id="a13f70fef9f202e157ba106f2c56eb4e1"></a>
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__IO <a class="el" href="unionPICOP__LINK__Type.html">PICOP_LINK_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a13f70fef9f202e157ba106f2c56eb4e1">LINK</a></td></tr>
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<tr class="memdesc:a13f70fef9f202e157ba106f2c56eb4e1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0B8 (R/W 32) Link. <br /></td></tr>
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<tr class="separator:a13f70fef9f202e157ba106f2c56eb4e1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3b82e4cb1776c77816ba0bf16eae0bfe"><td class="memItemLeft" align="right" valign="top"><a id="a3b82e4cb1776c77816ba0bf16eae0bfe"></a>
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__IO <a class="el" href="unionPICOP__SP__Type.html">PICOP_SP_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a3b82e4cb1776c77816ba0bf16eae0bfe">SP</a></td></tr>
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<tr class="memdesc:a3b82e4cb1776c77816ba0bf16eae0bfe"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0BC (R/W 32) Stack Pointer. <br /></td></tr>
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<tr class="separator:a3b82e4cb1776c77816ba0bf16eae0bfe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8d89ce4edfb46f2678ede119c3089a61"><td class="memItemLeft" align="right" valign="top"><a id="a8d89ce4edfb46f2678ede119c3089a61"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved5</b> [0x40]</td></tr>
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<tr class="separator:a8d89ce4edfb46f2678ede119c3089a61"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a052b6a7a264ff7f6ebf6e8b5fe36f1af"><td class="memItemLeft" align="right" valign="top"><a id="a052b6a7a264ff7f6ebf6e8b5fe36f1af"></a>
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__IO <a class="el" href="unionPICOP__MMUFLASH__Type.html">PICOP_MMUFLASH_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a052b6a7a264ff7f6ebf6e8b5fe36f1af">MMUFLASH</a></td></tr>
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<tr class="memdesc:a052b6a7a264ff7f6ebf6e8b5fe36f1af"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x100 (R/W 32) MMU mapping for flash. <br /></td></tr>
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<tr class="separator:a052b6a7a264ff7f6ebf6e8b5fe36f1af"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac5d61cce19dd93184b6a8f37699041d5"><td class="memItemLeft" align="right" valign="top"><a id="ac5d61cce19dd93184b6a8f37699041d5"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved6</b> [0x14]</td></tr>
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<tr class="separator:ac5d61cce19dd93184b6a8f37699041d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4b019cca1c976fa47fcda394db203e50"><td class="memItemLeft" align="right" valign="top"><a id="a4b019cca1c976fa47fcda394db203e50"></a>
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__IO <a class="el" href="unionPICOP__MMU0__Type.html">PICOP_MMU0_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a4b019cca1c976fa47fcda394db203e50">MMU0</a></td></tr>
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<tr class="memdesc:a4b019cca1c976fa47fcda394db203e50"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x118 (R/W 32) MMU mapping user 0. <br /></td></tr>
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<tr class="separator:a4b019cca1c976fa47fcda394db203e50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acb04d87fb9f3a9f52732243fa5a9846f"><td class="memItemLeft" align="right" valign="top"><a id="acb04d87fb9f3a9f52732243fa5a9846f"></a>
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__IO <a class="el" href="unionPICOP__MMU1__Type.html">PICOP_MMU1_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#acb04d87fb9f3a9f52732243fa5a9846f">MMU1</a></td></tr>
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<tr class="memdesc:acb04d87fb9f3a9f52732243fa5a9846f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x11C (R/W 32) MMU mapping user 1. <br /></td></tr>
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<tr class="separator:acb04d87fb9f3a9f52732243fa5a9846f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad781f325652dffdb3e472aa8ed09aa60"><td class="memItemLeft" align="right" valign="top"><a id="ad781f325652dffdb3e472aa8ed09aa60"></a>
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__IO <a class="el" href="unionPICOP__MMUCTRL__Type.html">PICOP_MMUCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#ad781f325652dffdb3e472aa8ed09aa60">MMUCTRL</a></td></tr>
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<tr class="memdesc:ad781f325652dffdb3e472aa8ed09aa60"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x120 (R/W 32) MMU Control. <br /></td></tr>
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<tr class="separator:ad781f325652dffdb3e472aa8ed09aa60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a090e18940522a41928828aebf2668710"><td class="memItemLeft" align="right" valign="top"><a id="a090e18940522a41928828aebf2668710"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved7</b> [0x5C]</td></tr>
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<tr class="separator:a090e18940522a41928828aebf2668710"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a225dc570334332dfa9db45ffc8ae5184"><td class="memItemLeft" align="right" valign="top"><a id="a225dc570334332dfa9db45ffc8ae5184"></a>
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__IO <a class="el" href="unionPICOP__ICACHE__Type.html">PICOP_ICACHE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a225dc570334332dfa9db45ffc8ae5184">ICACHE</a></td></tr>
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<tr class="memdesc:a225dc570334332dfa9db45ffc8ae5184"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x180 (R/W 32) Instruction Cache Control. <br /></td></tr>
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<tr class="separator:a225dc570334332dfa9db45ffc8ae5184"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae63b2539dcc65e1c490e891d7f098130"><td class="memItemLeft" align="right" valign="top"><a id="ae63b2539dcc65e1c490e891d7f098130"></a>
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__IO <a class="el" href="unionPICOP__ICACHELRU__Type.html">PICOP_ICACHELRU_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#ae63b2539dcc65e1c490e891d7f098130">ICACHELRU</a></td></tr>
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<tr class="memdesc:ae63b2539dcc65e1c490e891d7f098130"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x184 (R/W 32) Instruction Cache LRU. <br /></td></tr>
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<tr class="separator:ae63b2539dcc65e1c490e891d7f098130"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae3caacd32da29b6f6152ec8663b5986b"><td class="memItemLeft" align="right" valign="top"><a id="ae3caacd32da29b6f6152ec8663b5986b"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved8</b> [0x78]</td></tr>
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<tr class="separator:ae3caacd32da29b6f6152ec8663b5986b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1546159caebf63df278d15554a0cb692"><td class="memItemLeft" align="right" valign="top"><a id="a1546159caebf63df278d15554a0cb692"></a>
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__IO <a class="el" href="unionPICOP__QOSCTRL__Type.html">PICOP_QOSCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPicop.html#a1546159caebf63df278d15554a0cb692">QOSCTRL</a></td></tr>
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<tr class="memdesc:a1546159caebf63df278d15554a0cb692"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x200 (R/W 32) QOS Control. <br /></td></tr>
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<tr class="separator:a1546159caebf63df278d15554a0cb692"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>PICOP hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="component_2picop_8h_source.html#l01270">1270</a> of file <a class="el" href="component_2picop_8h_source.html">picop.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2picop_8h_source.html">picop.h</a></li>
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</ul>
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</div><!-- contents -->
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Generated by <a href="http://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.8.20
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