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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Oscctrl Struct Reference</div> </div>
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<p>OSCCTRL hardware registers.
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<a href="structOscctrl.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a3d9a2ba0eb41137e7a5d0f73bfc7bdc8"><td class="memItemLeft" align="right" valign="top"><a id="a3d9a2ba0eb41137e7a5d0f73bfc7bdc8"></a>
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__IO <a class="el" href="unionOSCCTRL__EVCTRL__Type.html">OSCCTRL_EVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrl.html#a3d9a2ba0eb41137e7a5d0f73bfc7bdc8">EVCTRL</a></td></tr>
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<tr class="memdesc:a3d9a2ba0eb41137e7a5d0f73bfc7bdc8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 8) Event Control. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x3]</td></tr>
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<tr class="separator:ac069d16e64dd75d0be1dc36c26e360dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6d860ddc7b53d096cb7c4f0e63053d3c"><td class="memItemLeft" align="right" valign="top"><a id="a6d860ddc7b53d096cb7c4f0e63053d3c"></a>
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__IO <a class="el" href="unionOSCCTRL__INTENCLR__Type.html">OSCCTRL_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrl.html#a6d860ddc7b53d096cb7c4f0e63053d3c">INTENCLR</a></td></tr>
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<tr class="memdesc:a6d860ddc7b53d096cb7c4f0e63053d3c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 32) Interrupt Enable Clear. <br /></td></tr>
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__IO <a class="el" href="unionOSCCTRL__INTENSET__Type.html">OSCCTRL_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrl.html#a2574505371983e1f0a1228ec3e8f1d22">INTENSET</a></td></tr>
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<tr class="memdesc:a2574505371983e1f0a1228ec3e8f1d22"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 32) Interrupt Enable Set. <br /></td></tr>
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<tr class="memitem:aa1fcfa6ec9a636e85e721056268617fa"><td class="memItemLeft" align="right" valign="top"><a id="aa1fcfa6ec9a636e85e721056268617fa"></a>
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__IO <a class="el" href="unionOSCCTRL__INTFLAG__Type.html">OSCCTRL_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrl.html#aa1fcfa6ec9a636e85e721056268617fa">INTFLAG</a></td></tr>
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<tr class="memdesc:aa1fcfa6ec9a636e85e721056268617fa"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear. <br /></td></tr>
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__I <a class="el" href="unionOSCCTRL__STATUS__Type.html">OSCCTRL_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrl.html#a4a7242dfd036f33a32da80313ad1bb01">STATUS</a></td></tr>
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<tr class="memdesc:a4a7242dfd036f33a32da80313ad1bb01"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/ 32) Status. <br /></td></tr>
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<tr class="separator:a4a7242dfd036f33a32da80313ad1bb01"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a577961ed982b57a5500ad4863171cb52"><td class="memItemLeft" align="right" valign="top"><a id="a577961ed982b57a5500ad4863171cb52"></a>
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__IO <a class="el" href="unionOSCCTRL__XOSCCTRL__Type.html">OSCCTRL_XOSCCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrl.html#a577961ed982b57a5500ad4863171cb52">XOSCCTRL</a> [2]</td></tr>
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<tr class="memdesc:a577961ed982b57a5500ad4863171cb52"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control. <br /></td></tr>
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<tr class="memitem:a991c8c7ca210b73cb9fc075f4bace8f3"><td class="memItemLeft" align="right" valign="top"><a id="a991c8c7ca210b73cb9fc075f4bace8f3"></a>
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__IO <a class="el" href="unionOSCCTRL__DFLLCTRLA__Type.html">OSCCTRL_DFLLCTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrl.html#a991c8c7ca210b73cb9fc075f4bace8f3">DFLLCTRLA</a></td></tr>
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<tr class="memdesc:a991c8c7ca210b73cb9fc075f4bace8f3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/W 8) DFLL48M Control A. <br /></td></tr>
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<tr class="memitem:a5dcbf856f99c4b5b8368342f286d0933"><td class="memItemLeft" align="right" valign="top"><a id="a5dcbf856f99c4b5b8368342f286d0933"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x3]</td></tr>
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<tr class="separator:a5dcbf856f99c4b5b8368342f286d0933"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aac90d6fbc832e20c4e0a82993dc4a8bb"><td class="memItemLeft" align="right" valign="top"><a id="aac90d6fbc832e20c4e0a82993dc4a8bb"></a>
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__IO <a class="el" href="unionOSCCTRL__DFLLCTRLB__Type.html">OSCCTRL_DFLLCTRLB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrl.html#aac90d6fbc832e20c4e0a82993dc4a8bb">DFLLCTRLB</a></td></tr>
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<tr class="memdesc:aac90d6fbc832e20c4e0a82993dc4a8bb"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x20 (R/W 8) DFLL48M Control B. <br /></td></tr>
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<tr class="separator:aac90d6fbc832e20c4e0a82993dc4a8bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aecb88597e5e0575b9ce6c454cec2318c"><td class="memItemLeft" align="right" valign="top"><a id="aecb88597e5e0575b9ce6c454cec2318c"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x3]</td></tr>
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<tr class="separator:aecb88597e5e0575b9ce6c454cec2318c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac53609a01e9506a55b522270b056cfbd"><td class="memItemLeft" align="right" valign="top"><a id="ac53609a01e9506a55b522270b056cfbd"></a>
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__IO <a class="el" href="unionOSCCTRL__DFLLVAL__Type.html">OSCCTRL_DFLLVAL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrl.html#ac53609a01e9506a55b522270b056cfbd">DFLLVAL</a></td></tr>
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<tr class="memdesc:ac53609a01e9506a55b522270b056cfbd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x24 (R/W 32) DFLL48M Value. <br /></td></tr>
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<tr class="separator:ac53609a01e9506a55b522270b056cfbd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6f5f5a94910b0097e158b10b409fe8fa"><td class="memItemLeft" align="right" valign="top"><a id="a6f5f5a94910b0097e158b10b409fe8fa"></a>
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__IO <a class="el" href="unionOSCCTRL__DFLLMUL__Type.html">OSCCTRL_DFLLMUL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrl.html#a6f5f5a94910b0097e158b10b409fe8fa">DFLLMUL</a></td></tr>
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<tr class="memdesc:a6f5f5a94910b0097e158b10b409fe8fa"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x28 (R/W 32) DFLL48M Multiplier. <br /></td></tr>
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<tr class="separator:a6f5f5a94910b0097e158b10b409fe8fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa4857fc3c646f1118b8e0c22226b194d"><td class="memItemLeft" align="right" valign="top"><a id="aa4857fc3c646f1118b8e0c22226b194d"></a>
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__IO <a class="el" href="unionOSCCTRL__DFLLSYNC__Type.html">OSCCTRL_DFLLSYNC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrl.html#aa4857fc3c646f1118b8e0c22226b194d">DFLLSYNC</a></td></tr>
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<tr class="memdesc:aa4857fc3c646f1118b8e0c22226b194d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2C (R/W 8) DFLL48M Synchronization. <br /></td></tr>
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<tr class="separator:aa4857fc3c646f1118b8e0c22226b194d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad5960d2808cc8eff0f9ca823f7321540"><td class="memItemLeft" align="right" valign="top"><a id="ad5960d2808cc8eff0f9ca823f7321540"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved4</b> [0x3]</td></tr>
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<tr class="separator:ad5960d2808cc8eff0f9ca823f7321540"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2a7ff599a3ed3884b51e6e5f54f1548b"><td class="memItemLeft" align="right" valign="top"><a id="a2a7ff599a3ed3884b51e6e5f54f1548b"></a>
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<a class="el" href="structOscctrlDpll.html">OscctrlDpll</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrl.html#a2a7ff599a3ed3884b51e6e5f54f1548b">Dpll</a> [2]</td></tr>
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<tr class="memdesc:a2a7ff599a3ed3884b51e6e5f54f1548b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 <a class="el" href="structOscctrlDpll.html" title="OscctrlDpll hardware registers.">OscctrlDpll</a> groups [DPLLS_NUM]. <br /></td></tr>
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<tr class="separator:a2a7ff599a3ed3884b51e6e5f54f1548b"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>OSCCTRL hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00771">771</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a></li>
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</ul>
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Generated by <a href="http://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.8.20
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