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<div id="projectname">SAME54P20A Test Project
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">I2s Struct Reference</div> </div>
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<p>I2S hardware registers.
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<a href="structI2s.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="component_2i2s_8h_source.html">i2s.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a789ed154702ba87dba0ff007ea7180e6"><td class="memItemLeft" align="right" valign="top"><a id="a789ed154702ba87dba0ff007ea7180e6"></a>
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__IO <a class="el" href="unionI2S__CTRLA__Type.html">I2S_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structI2s.html#a789ed154702ba87dba0ff007ea7180e6">CTRLA</a></td></tr>
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<tr class="memdesc:a789ed154702ba87dba0ff007ea7180e6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 8) Control A. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x3]</td></tr>
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__IO <a class="el" href="unionI2S__CLKCTRL__Type.html">I2S_CLKCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structI2s.html#ab5a3279daceafd9030bd4772351709a5">CLKCTRL</a> [2]</td></tr>
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<tr class="memdesc:ab5a3279daceafd9030bd4772351709a5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 32) Clock Unit n Control. <br /></td></tr>
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__IO <a class="el" href="unionI2S__INTENCLR__Type.html">I2S_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structI2s.html#a288e75f19ac339c92dd44b059501cd66">INTENCLR</a></td></tr>
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<tr class="memdesc:a288e75f19ac339c92dd44b059501cd66"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 16) Interrupt Enable Clear. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x2]</td></tr>
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__IO <a class="el" href="unionI2S__INTENSET__Type.html">I2S_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structI2s.html#a8509c18ae990d1a0fdf87162db444d66">INTENSET</a></td></tr>
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<tr class="memdesc:a8509c18ae990d1a0fdf87162db444d66"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/W 16) Interrupt Enable Set. <br /></td></tr>
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__IO <a class="el" href="unionI2S__INTFLAG__Type.html">I2S_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structI2s.html#ac631fa19eb0927d9cc99c1743945274c">INTFLAG</a></td></tr>
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<tr class="memdesc:ac631fa19eb0927d9cc99c1743945274c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear. <br /></td></tr>
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__I <a class="el" href="unionI2S__SYNCBUSY__Type.html">I2S_SYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structI2s.html#aed448d6e471dea1704798838e2517ddf">SYNCBUSY</a></td></tr>
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<tr class="memdesc:aed448d6e471dea1704798838e2517ddf"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x18 (R/ 16) Synchronization Status. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved5</b> [0x6]</td></tr>
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__IO <a class="el" href="unionI2S__TXCTRL__Type.html">I2S_TXCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structI2s.html#abca7c659461def682cd1e2a1212a8e85">TXCTRL</a></td></tr>
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<tr class="memdesc:abca7c659461def682cd1e2a1212a8e85"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x20 (R/W 32) Tx Serializer Control. <br /></td></tr>
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__IO <a class="el" href="unionI2S__RXCTRL__Type.html">I2S_RXCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structI2s.html#ad119b071db73fdeb1c9351e9df9e113c">RXCTRL</a></td></tr>
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<tr class="memdesc:ad119b071db73fdeb1c9351e9df9e113c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x24 (R/W 32) Rx Serializer Control. <br /></td></tr>
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__O <a class="el" href="unionI2S__TXDATA__Type.html">I2S_TXDATA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structI2s.html#ac22ccf3ad15a78e92b0de1321aff2656">TXDATA</a></td></tr>
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<tr class="memdesc:ac22ccf3ad15a78e92b0de1321aff2656"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 ( /W 32) Tx Data. <br /></td></tr>
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__I <a class="el" href="unionI2S__RXDATA__Type.html">I2S_RXDATA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structI2s.html#a23288f6adcad3c1c90d16067f7011839">RXDATA</a></td></tr>
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<tr class="memdesc:a23288f6adcad3c1c90d16067f7011839"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x34 (R/ 32) Rx Data. <br /></td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>I2S hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="component_2i2s_8h_source.html#l00725">725</a> of file <a class="el" href="component_2i2s_8h_source.html">i2s.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2i2s_8h_source.html">i2s.h</a></li>
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Generated by <a href="http://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.8.20
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