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<div id="projectname">SAME54P20A Test Project
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Freqm Struct Reference</div> </div>
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<p>FREQM hardware registers.
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<a href="structFreqm.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="component_2freqm_8h_source.html">freqm.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:aa4f58c1c25812f29b58cf44f427ccafe"><td class="memItemLeft" align="right" valign="top"><a id="aa4f58c1c25812f29b58cf44f427ccafe"></a>
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__IO <a class="el" href="unionFREQM__CTRLA__Type.html">FREQM_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structFreqm.html#aa4f58c1c25812f29b58cf44f427ccafe">CTRLA</a></td></tr>
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<tr class="memdesc:aa4f58c1c25812f29b58cf44f427ccafe"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 8) Control A Register. <br /></td></tr>
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<tr class="separator:aa4f58c1c25812f29b58cf44f427ccafe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a792aea49e629c0ed49ffc0a450e7276e"><td class="memItemLeft" align="right" valign="top"><a id="a792aea49e629c0ed49ffc0a450e7276e"></a>
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__O <a class="el" href="unionFREQM__CTRLB__Type.html">FREQM_CTRLB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structFreqm.html#a792aea49e629c0ed49ffc0a450e7276e">CTRLB</a></td></tr>
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<tr class="memdesc:a792aea49e629c0ed49ffc0a450e7276e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x01 ( /W 8) Control B Register. <br /></td></tr>
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<tr class="separator:a792aea49e629c0ed49ffc0a450e7276e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a86acf9141590973a744d9bf722b27cd9"><td class="memItemLeft" align="right" valign="top"><a id="a86acf9141590973a744d9bf722b27cd9"></a>
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__IO <a class="el" href="unionFREQM__CFGA__Type.html">FREQM_CFGA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structFreqm.html#a86acf9141590973a744d9bf722b27cd9">CFGA</a></td></tr>
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<tr class="memdesc:a86acf9141590973a744d9bf722b27cd9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02 (R/W 16) Config A register. <br /></td></tr>
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<tr class="separator:a86acf9141590973a744d9bf722b27cd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a761c9f670e0051ee3a4acc726fee610d"><td class="memItemLeft" align="right" valign="top"><a id="a761c9f670e0051ee3a4acc726fee610d"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x4]</td></tr>
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<tr class="separator:a761c9f670e0051ee3a4acc726fee610d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a01cf84b4191bb7afb80794793d442084"><td class="memItemLeft" align="right" valign="top"><a id="a01cf84b4191bb7afb80794793d442084"></a>
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__IO <a class="el" href="unionFREQM__INTENCLR__Type.html">FREQM_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structFreqm.html#a01cf84b4191bb7afb80794793d442084">INTENCLR</a></td></tr>
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<tr class="memdesc:a01cf84b4191bb7afb80794793d442084"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 8) Interrupt Enable Clear Register. <br /></td></tr>
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<tr class="separator:a01cf84b4191bb7afb80794793d442084"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8f361e5f18a099f2087cdaaef0954676"><td class="memItemLeft" align="right" valign="top"><a id="a8f361e5f18a099f2087cdaaef0954676"></a>
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__IO <a class="el" href="unionFREQM__INTENSET__Type.html">FREQM_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structFreqm.html#a8f361e5f18a099f2087cdaaef0954676">INTENSET</a></td></tr>
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<tr class="memdesc:a8f361e5f18a099f2087cdaaef0954676"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x09 (R/W 8) Interrupt Enable Set Register. <br /></td></tr>
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<tr class="separator:a8f361e5f18a099f2087cdaaef0954676"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7e6535e0c1ebd90f0f1f501c8553fa1c"><td class="memItemLeft" align="right" valign="top"><a id="a7e6535e0c1ebd90f0f1f501c8553fa1c"></a>
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__IO <a class="el" href="unionFREQM__INTFLAG__Type.html">FREQM_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structFreqm.html#a7e6535e0c1ebd90f0f1f501c8553fa1c">INTFLAG</a></td></tr>
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<tr class="memdesc:a7e6535e0c1ebd90f0f1f501c8553fa1c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0A (R/W 8) Interrupt Flag Register. <br /></td></tr>
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<tr class="memitem:a86f3d2bd313cb43e4da910ee8ffde25d"><td class="memItemLeft" align="right" valign="top"><a id="a86f3d2bd313cb43e4da910ee8ffde25d"></a>
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__IO <a class="el" href="unionFREQM__STATUS__Type.html">FREQM_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structFreqm.html#a86f3d2bd313cb43e4da910ee8ffde25d">STATUS</a></td></tr>
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<tr class="memdesc:a86f3d2bd313cb43e4da910ee8ffde25d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0B (R/W 8) Status Register. <br /></td></tr>
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<tr class="separator:a86f3d2bd313cb43e4da910ee8ffde25d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a93b2df6b6e009cb72796957addd0cc03"><td class="memItemLeft" align="right" valign="top"><a id="a93b2df6b6e009cb72796957addd0cc03"></a>
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__I <a class="el" href="unionFREQM__SYNCBUSY__Type.html">FREQM_SYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structFreqm.html#a93b2df6b6e009cb72796957addd0cc03">SYNCBUSY</a></td></tr>
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<tr class="memdesc:a93b2df6b6e009cb72796957addd0cc03"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/ 32) Synchronization Busy Register. <br /></td></tr>
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<tr class="separator:a93b2df6b6e009cb72796957addd0cc03"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afc0d7ea9d3603865a764e82f2a448781"><td class="memItemLeft" align="right" valign="top"><a id="afc0d7ea9d3603865a764e82f2a448781"></a>
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__I <a class="el" href="unionFREQM__VALUE__Type.html">FREQM_VALUE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structFreqm.html#afc0d7ea9d3603865a764e82f2a448781">VALUE</a></td></tr>
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<tr class="memdesc:afc0d7ea9d3603865a764e82f2a448781"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/ 32) Count Value Register. <br /></td></tr>
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<tr class="separator:afc0d7ea9d3603865a764e82f2a448781"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>FREQM hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="component_2freqm_8h_source.html#l00217">217</a> of file <a class="el" href="component_2freqm_8h_source.html">freqm.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2freqm_8h_source.html">freqm.h</a></li>
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