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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">DmacChannel Struct Reference</div> </div>
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<p><a class="el" href="structDmacChannel.html" title="DmacChannel hardware registers.">DmacChannel</a> hardware registers.
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<a href="structDmacChannel.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="component_2dmac_8h_source.html">dmac.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:ab328f5ef6c9bd46945648a94f8c177ad"><td class="memItemLeft" align="right" valign="top"><a id="ab328f5ef6c9bd46945648a94f8c177ad"></a>
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__IO <a class="el" href="unionDMAC__CHCTRLA__Type.html">DMAC_CHCTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacChannel.html#ab328f5ef6c9bd46945648a94f8c177ad">CHCTRLA</a></td></tr>
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<tr class="memdesc:ab328f5ef6c9bd46945648a94f8c177ad"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 32) Channel n Control A. <br /></td></tr>
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__IO <a class="el" href="unionDMAC__CHCTRLB__Type.html">DMAC_CHCTRLB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacChannel.html#a28372b6e32fab475213f93c150c7231c">CHCTRLB</a></td></tr>
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<tr class="memdesc:a28372b6e32fab475213f93c150c7231c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 8) Channel n Control B. <br /></td></tr>
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<tr class="separator:a28372b6e32fab475213f93c150c7231c"><td class="memSeparator" colspan="2"> </td></tr>
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__IO <a class="el" href="unionDMAC__CHPRILVL__Type.html">DMAC_CHPRILVL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacChannel.html#a8106c41bd57fe548c95750dccf6c95a5">CHPRILVL</a></td></tr>
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<tr class="memdesc:a8106c41bd57fe548c95750dccf6c95a5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x05 (R/W 8) Channel n Priority Level. <br /></td></tr>
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__IO <a class="el" href="unionDMAC__CHEVCTRL__Type.html">DMAC_CHEVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacChannel.html#a09e7050f13d84a4b3811d449dba5c18a">CHEVCTRL</a></td></tr>
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<tr class="memdesc:a09e7050f13d84a4b3811d449dba5c18a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x06 (R/W 8) Channel n Event Control. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x5]</td></tr>
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__IO <a class="el" href="unionDMAC__CHINTENCLR__Type.html">DMAC_CHINTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacChannel.html#aa6c320da2b2ec251fb20fe7872c8121d">CHINTENCLR</a></td></tr>
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<tr class="memdesc:aa6c320da2b2ec251fb20fe7872c8121d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 8) Channel n Interrupt Enable Clear. <br /></td></tr>
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<tr class="separator:aa6c320da2b2ec251fb20fe7872c8121d"><td class="memSeparator" colspan="2"> </td></tr>
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__IO <a class="el" href="unionDMAC__CHINTENSET__Type.html">DMAC_CHINTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacChannel.html#aa3465a216376f1a38cec382b6fd713d8">CHINTENSET</a></td></tr>
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<tr class="memdesc:aa3465a216376f1a38cec382b6fd713d8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0D (R/W 8) Channel n Interrupt Enable Set. <br /></td></tr>
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__IO <a class="el" href="unionDMAC__CHINTFLAG__Type.html">DMAC_CHINTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacChannel.html#ab717a01690a7bc9c18fc05822b79834f">CHINTFLAG</a></td></tr>
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<tr class="memdesc:ab717a01690a7bc9c18fc05822b79834f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0E (R/W 8) Channel n Interrupt Flag Status and Clear. <br /></td></tr>
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__IO <a class="el" href="unionDMAC__CHSTATUS__Type.html">DMAC_CHSTATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmacChannel.html#a692a00aaa2f24723e138c6ef10121168">CHSTATUS</a></td></tr>
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<tr class="memdesc:a692a00aaa2f24723e138c6ef10121168"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0F (R/W 8) Channel n Status. <br /></td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p><a class="el" href="structDmacChannel.html" title="DmacChannel hardware registers.">DmacChannel</a> hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="component_2dmac_8h_source.html#l01354">1354</a> of file <a class="el" href="component_2dmac_8h_source.html">dmac.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2dmac_8h_source.html">dmac.h</a></li>
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