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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/supc.h File Reference</title>
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<a href="#define-members">Macros</a> </div>
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<div class="title">supc.h File Reference</div> </div>
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<div class="contents">
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<p>Instance description for SUPC.
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<a href="#details">More...</a></p>
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<p><a href="instance_2supc_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:aa62069401ac79b985ae99c6b29059683"><td class="memItemLeft" align="right" valign="top"><a id="aa62069401ac79b985ae99c6b29059683"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2supc_8h.html#aa62069401ac79b985ae99c6b29059683">REG_SUPC_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001800UL)</td></tr>
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<tr class="memdesc:aa62069401ac79b985ae99c6b29059683"><td class="mdescLeft"> </td><td class="mdescRight">(SUPC) Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:aa62069401ac79b985ae99c6b29059683"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afddf3f8bfd8b5eb4424ee841c04cca43"><td class="memItemLeft" align="right" valign="top"><a id="afddf3f8bfd8b5eb4424ee841c04cca43"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2supc_8h.html#afddf3f8bfd8b5eb4424ee841c04cca43">REG_SUPC_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001804UL)</td></tr>
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<tr class="memdesc:afddf3f8bfd8b5eb4424ee841c04cca43"><td class="mdescLeft"> </td><td class="mdescRight">(SUPC) Interrupt Enable Set <br /></td></tr>
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<tr class="separator:afddf3f8bfd8b5eb4424ee841c04cca43"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0f62cbbc73d5a4a0b2b335c7dce783a8"><td class="memItemLeft" align="right" valign="top"><a id="a0f62cbbc73d5a4a0b2b335c7dce783a8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2supc_8h.html#a0f62cbbc73d5a4a0b2b335c7dce783a8">REG_SUPC_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001808UL)</td></tr>
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<tr class="memdesc:a0f62cbbc73d5a4a0b2b335c7dce783a8"><td class="mdescLeft"> </td><td class="mdescRight">(SUPC) Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:a0f62cbbc73d5a4a0b2b335c7dce783a8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aff1836023546825f537c1d62b1dd1360"><td class="memItemLeft" align="right" valign="top"><a id="aff1836023546825f537c1d62b1dd1360"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2supc_8h.html#aff1836023546825f537c1d62b1dd1360">REG_SUPC_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4000180CUL)</td></tr>
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<tr class="memdesc:aff1836023546825f537c1d62b1dd1360"><td class="mdescLeft"> </td><td class="mdescRight">(SUPC) Power and Clocks Status <br /></td></tr>
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<tr class="separator:aff1836023546825f537c1d62b1dd1360"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5b1d7b6889f888ca8f32790949541d84"><td class="memItemLeft" align="right" valign="top"><a id="a5b1d7b6889f888ca8f32790949541d84"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2supc_8h.html#a5b1d7b6889f888ca8f32790949541d84">REG_SUPC_BOD33</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001810UL)</td></tr>
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<tr class="memdesc:a5b1d7b6889f888ca8f32790949541d84"><td class="mdescLeft"> </td><td class="mdescRight">(SUPC) BOD33 Control <br /></td></tr>
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<tr class="separator:a5b1d7b6889f888ca8f32790949541d84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aae7b5adb1fa5c23b414388b49ea14f5f"><td class="memItemLeft" align="right" valign="top"><a id="aae7b5adb1fa5c23b414388b49ea14f5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2supc_8h.html#aae7b5adb1fa5c23b414388b49ea14f5f">REG_SUPC_VREG</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001818UL)</td></tr>
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<tr class="memdesc:aae7b5adb1fa5c23b414388b49ea14f5f"><td class="mdescLeft"> </td><td class="mdescRight">(SUPC) VREG Control <br /></td></tr>
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<tr class="separator:aae7b5adb1fa5c23b414388b49ea14f5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3c7daa384e194167957343c00a1fa138"><td class="memItemLeft" align="right" valign="top"><a id="a3c7daa384e194167957343c00a1fa138"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2supc_8h.html#a3c7daa384e194167957343c00a1fa138">REG_SUPC_VREF</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4000181CUL)</td></tr>
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<tr class="memdesc:a3c7daa384e194167957343c00a1fa138"><td class="mdescLeft"> </td><td class="mdescRight">(SUPC) VREF Control <br /></td></tr>
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<tr class="separator:a3c7daa384e194167957343c00a1fa138"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a85b8fd51b114867c6f3e3f552899ae2e"><td class="memItemLeft" align="right" valign="top"><a id="a85b8fd51b114867c6f3e3f552899ae2e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2supc_8h.html#a85b8fd51b114867c6f3e3f552899ae2e">REG_SUPC_BBPS</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001820UL)</td></tr>
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<tr class="memdesc:a85b8fd51b114867c6f3e3f552899ae2e"><td class="mdescLeft"> </td><td class="mdescRight">(SUPC) Battery Backup Power Switch <br /></td></tr>
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<tr class="separator:a85b8fd51b114867c6f3e3f552899ae2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2f0811412545c6726e65c0a252ce44c1"><td class="memItemLeft" align="right" valign="top"><a id="a2f0811412545c6726e65c0a252ce44c1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2supc_8h.html#a2f0811412545c6726e65c0a252ce44c1">REG_SUPC_BKOUT</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001824UL)</td></tr>
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<tr class="memdesc:a2f0811412545c6726e65c0a252ce44c1"><td class="mdescLeft"> </td><td class="mdescRight">(SUPC) Backup Output Control <br /></td></tr>
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<tr class="separator:a2f0811412545c6726e65c0a252ce44c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a08f9dc4914e332d58f2d9cc1fcc320"><td class="memItemLeft" align="right" valign="top"><a id="a0a08f9dc4914e332d58f2d9cc1fcc320"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2supc_8h.html#a0a08f9dc4914e332d58f2d9cc1fcc320">REG_SUPC_BKIN</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x40001828UL)</td></tr>
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<tr class="memdesc:a0a08f9dc4914e332d58f2d9cc1fcc320"><td class="mdescLeft"> </td><td class="mdescRight">(SUPC) Backup Input Control <br /></td></tr>
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<tr class="separator:a0a08f9dc4914e332d58f2d9cc1fcc320"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:accee3147cc5ed78df32d458d0774235f"><td class="memItemLeft" align="right" valign="top"><a id="accee3147cc5ed78df32d458d0774235f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SUPC_BOD12_CALIB_MSB</b>   5</td></tr>
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<tr class="separator:accee3147cc5ed78df32d458d0774235f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a83434cb98943cabaa271dd805461dba4"><td class="memItemLeft" align="right" valign="top"><a id="a83434cb98943cabaa271dd805461dba4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SUPC_BOD33_CALIB_MSB</b>   5</td></tr>
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<tr class="separator:a83434cb98943cabaa271dd805461dba4"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for SUPC. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="instance_2supc_8h_source.html">supc.h</a>.</p>
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Generated by <a href="http://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.8.20
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