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<div id="projectname">SAME54P20A Test Project
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">port.h</div> </div>
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<div class="contents">
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<a href="instance_2port_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_PORT_INSTANCE_</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_PORT_INSTANCE_</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for PORT peripheral ========== */</span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_PORT_DIR0 (0x41008000) </span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_PORT_DIRCLR0 (0x41008004) </span></div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_PORT_DIRSET0 (0x41008008) </span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_PORT_DIRTGL0 (0x4100800C) </span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_PORT_OUT0 (0x41008010) </span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_PORT_OUTCLR0 (0x41008014) </span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_PORT_OUTSET0 (0x41008018) </span></div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_PORT_OUTTGL0 (0x4100801C) </span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_PORT_IN0 (0x41008020) </span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_PORT_CTRL0 (0x41008024) </span></div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_PORT_WRCONFIG0 (0x41008028) </span></div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_PORT_EVCTRL0 (0x4100802C) </span></div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_PORT_PMUX0 (0x41008030) </span></div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_PORT_PINCFG0 (0x41008040) </span></div>
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<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_PORT_DIR1 (0x41008080) </span></div>
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<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_PORT_DIRCLR1 (0x41008084) </span></div>
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<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_PORT_DIRSET1 (0x41008088) </span></div>
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<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_PORT_DIRTGL1 (0x4100808C) </span></div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_PORT_OUT1 (0x41008090) </span></div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_PORT_OUTCLR1 (0x41008094) </span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_PORT_OUTSET1 (0x41008098) </span></div>
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<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_PORT_OUTTGL1 (0x4100809C) </span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define REG_PORT_IN1 (0x410080A0) </span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define REG_PORT_CTRL1 (0x410080A4) </span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#define REG_PORT_WRCONFIG1 (0x410080A8) </span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor">#define REG_PORT_EVCTRL1 (0x410080AC) </span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="preprocessor">#define REG_PORT_PMUX1 (0x410080B0) </span></div>
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<div class="line"><a name="l00062"></a><span class="lineno"> 62</span> <span class="preprocessor">#define REG_PORT_PINCFG1 (0x410080C0) </span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor">#define REG_PORT_DIR2 (0x41008100) </span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="preprocessor">#define REG_PORT_DIRCLR2 (0x41008104) </span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"> 65</span> <span class="preprocessor">#define REG_PORT_DIRSET2 (0x41008108) </span></div>
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<div class="line"><a name="l00066"></a><span class="lineno"> 66</span> <span class="preprocessor">#define REG_PORT_DIRTGL2 (0x4100810C) </span></div>
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<div class="line"><a name="l00067"></a><span class="lineno"> 67</span> <span class="preprocessor">#define REG_PORT_OUT2 (0x41008110) </span></div>
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<div class="line"><a name="l00068"></a><span class="lineno"> 68</span> <span class="preprocessor">#define REG_PORT_OUTCLR2 (0x41008114) </span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"> 69</span> <span class="preprocessor">#define REG_PORT_OUTSET2 (0x41008118) </span></div>
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<div class="line"><a name="l00070"></a><span class="lineno"> 70</span> <span class="preprocessor">#define REG_PORT_OUTTGL2 (0x4100811C) </span></div>
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<div class="line"><a name="l00071"></a><span class="lineno"> 71</span> <span class="preprocessor">#define REG_PORT_IN2 (0x41008120) </span></div>
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<div class="line"><a name="l00072"></a><span class="lineno"> 72</span> <span class="preprocessor">#define REG_PORT_CTRL2 (0x41008124) </span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"> 73</span> <span class="preprocessor">#define REG_PORT_WRCONFIG2 (0x41008128) </span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"> 74</span> <span class="preprocessor">#define REG_PORT_EVCTRL2 (0x4100812C) </span></div>
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<div class="line"><a name="l00075"></a><span class="lineno"> 75</span> <span class="preprocessor">#define REG_PORT_PMUX2 (0x41008130) </span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"> 76</span> <span class="preprocessor">#define REG_PORT_PINCFG2 (0x41008140) </span></div>
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<div class="line"><a name="l00077"></a><span class="lineno"> 77</span> <span class="preprocessor">#define REG_PORT_DIR3 (0x41008180) </span></div>
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<div class="line"><a name="l00078"></a><span class="lineno"> 78</span> <span class="preprocessor">#define REG_PORT_DIRCLR3 (0x41008184) </span></div>
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<div class="line"><a name="l00079"></a><span class="lineno"> 79</span> <span class="preprocessor">#define REG_PORT_DIRSET3 (0x41008188) </span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"> 80</span> <span class="preprocessor">#define REG_PORT_DIRTGL3 (0x4100818C) </span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"> 81</span> <span class="preprocessor">#define REG_PORT_OUT3 (0x41008190) </span></div>
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<div class="line"><a name="l00082"></a><span class="lineno"> 82</span> <span class="preprocessor">#define REG_PORT_OUTCLR3 (0x41008194) </span></div>
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<div class="line"><a name="l00083"></a><span class="lineno"> 83</span> <span class="preprocessor">#define REG_PORT_OUTSET3 (0x41008198) </span></div>
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<div class="line"><a name="l00084"></a><span class="lineno"> 84</span> <span class="preprocessor">#define REG_PORT_OUTTGL3 (0x4100819C) </span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"> 85</span> <span class="preprocessor">#define REG_PORT_IN3 (0x410081A0) </span></div>
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<div class="line"><a name="l00086"></a><span class="lineno"> 86</span> <span class="preprocessor">#define REG_PORT_CTRL3 (0x410081A4) </span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"> 87</span> <span class="preprocessor">#define REG_PORT_WRCONFIG3 (0x410081A8) </span></div>
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<div class="line"><a name="l00088"></a><span class="lineno"> 88</span> <span class="preprocessor">#define REG_PORT_EVCTRL3 (0x410081AC) </span></div>
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<div class="line"><a name="l00089"></a><span class="lineno"> 89</span> <span class="preprocessor">#define REG_PORT_PMUX3 (0x410081B0) </span></div>
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<div class="line"><a name="l00090"></a><span class="lineno"> 90</span> <span class="preprocessor">#define REG_PORT_PINCFG3 (0x410081C0) </span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"> 91</span> <span class="preprocessor">#else</span></div>
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<div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a97266c43309c6d9ae5e9b0b7fade9b88"> 92</a></span> <span class="preprocessor">#define REG_PORT_DIR0 (*(RwReg *)0x41008000UL) </span></div>
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<div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a202e7577e003ee206321199cc1425730"> 93</a></span> <span class="preprocessor">#define REG_PORT_DIRCLR0 (*(RwReg *)0x41008004UL) </span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#adfceb6d4e4c262cf212b9be2109e989f"> 94</a></span> <span class="preprocessor">#define REG_PORT_DIRSET0 (*(RwReg *)0x41008008UL) </span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a44d946752b1e9c699bd69918081579a4"> 95</a></span> <span class="preprocessor">#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100800CUL) </span></div>
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<div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#ac0e9c345de1c1ea20a4634012545a4de"> 96</a></span> <span class="preprocessor">#define REG_PORT_OUT0 (*(RwReg *)0x41008010UL) </span></div>
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<div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#ad7a6aa55482c6e92ed66a6deeca0b0b5"> 97</a></span> <span class="preprocessor">#define REG_PORT_OUTCLR0 (*(RwReg *)0x41008014UL) </span></div>
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<div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a3481abedeb8460f687c1a19ec8433dd9"> 98</a></span> <span class="preprocessor">#define REG_PORT_OUTSET0 (*(RwReg *)0x41008018UL) </span></div>
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<div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a078c4860bbcb38bdc972ae229eeea08e"> 99</a></span> <span class="preprocessor">#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100801CUL) </span></div>
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<div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a80079360b9d522773b1793da944d3f10"> 100</a></span> <span class="preprocessor">#define REG_PORT_IN0 (*(RoReg *)0x41008020UL) </span></div>
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<div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#af2078f225a38de014a88804d31e7c032"> 101</a></span> <span class="preprocessor">#define REG_PORT_CTRL0 (*(RwReg *)0x41008024UL) </span></div>
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<div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a91ac37967534f1755cdf49b6bb3bc559"> 102</a></span> <span class="preprocessor">#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41008028UL) </span></div>
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<div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#aac947060c7edb8c76015d52236a4ad62"> 103</a></span> <span class="preprocessor">#define REG_PORT_EVCTRL0 (*(RwReg *)0x4100802CUL) </span></div>
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<div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#aeb037cc9cda118676dff8ad7505ddc2f"> 104</a></span> <span class="preprocessor">#define REG_PORT_PMUX0 (*(RwReg8 *)0x41008030UL) </span></div>
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<div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a2e31b23171a494bff836994fa537f731"> 105</a></span> <span class="preprocessor">#define REG_PORT_PINCFG0 (*(RwReg8 *)0x41008040UL) </span></div>
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<div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#ac8dc6913719cf8cf84d5b902bb08b3e5"> 106</a></span> <span class="preprocessor">#define REG_PORT_DIR1 (*(RwReg *)0x41008080UL) </span></div>
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<div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a05a281f12c37a0d891edb87e4e3f44f0"> 107</a></span> <span class="preprocessor">#define REG_PORT_DIRCLR1 (*(RwReg *)0x41008084UL) </span></div>
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<div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#ad08b54a1cadc6153671bd02995e7fdf9"> 108</a></span> <span class="preprocessor">#define REG_PORT_DIRSET1 (*(RwReg *)0x41008088UL) </span></div>
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<div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a3f243c3e1324bf63fe615463fd7da9ec"> 109</a></span> <span class="preprocessor">#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100808CUL) </span></div>
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<div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a675f28e419b3dad129f7d2866a37e957"> 110</a></span> <span class="preprocessor">#define REG_PORT_OUT1 (*(RwReg *)0x41008090UL) </span></div>
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<div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#aa231b8a484b2b2e25e024529ab0bdaa4"> 111</a></span> <span class="preprocessor">#define REG_PORT_OUTCLR1 (*(RwReg *)0x41008094UL) </span></div>
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<div class="line"><a name="l00112"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#accd4c6ca59c7375653168f8cd3f7695e"> 112</a></span> <span class="preprocessor">#define REG_PORT_OUTSET1 (*(RwReg *)0x41008098UL) </span></div>
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<div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a6ef8a41ab86b47ac05ed1de8cc0442f1"> 113</a></span> <span class="preprocessor">#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100809CUL) </span></div>
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<div class="line"><a name="l00114"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a94288e15fe3ce4c8b1a968396de063ae"> 114</a></span> <span class="preprocessor">#define REG_PORT_IN1 (*(RoReg *)0x410080A0UL) </span></div>
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<div class="line"><a name="l00115"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#ada81fa07af25afdc8437a28f6835784a"> 115</a></span> <span class="preprocessor">#define REG_PORT_CTRL1 (*(RwReg *)0x410080A4UL) </span></div>
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<div class="line"><a name="l00116"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#adf1cf6e3d72650defd52025c13333f75"> 116</a></span> <span class="preprocessor">#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410080A8UL) </span></div>
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<div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#ac9e245291d5e9b4742b898acd2a48c51"> 117</a></span> <span class="preprocessor">#define REG_PORT_EVCTRL1 (*(RwReg *)0x410080ACUL) </span></div>
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<div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a7045d8c7fbb9ac73235016d1f4c8e4f4"> 118</a></span> <span class="preprocessor">#define REG_PORT_PMUX1 (*(RwReg8 *)0x410080B0UL) </span></div>
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<div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a66e44ef756e8a9b0af90efe44ba34987"> 119</a></span> <span class="preprocessor">#define REG_PORT_PINCFG1 (*(RwReg8 *)0x410080C0UL) </span></div>
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<div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a872afd5fcbef3b6ee9ee6fb44add7146"> 120</a></span> <span class="preprocessor">#define REG_PORT_DIR2 (*(RwReg *)0x41008100UL) </span></div>
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<div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#ad38fc174d5931ccec83836e2612de56c"> 121</a></span> <span class="preprocessor">#define REG_PORT_DIRCLR2 (*(RwReg *)0x41008104UL) </span></div>
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<div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#adce4f38c02a8477a5cb2f9c33f0b13d5"> 122</a></span> <span class="preprocessor">#define REG_PORT_DIRSET2 (*(RwReg *)0x41008108UL) </span></div>
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<div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a6ff43e4151c08f13eb157f2e66a40245"> 123</a></span> <span class="preprocessor">#define REG_PORT_DIRTGL2 (*(RwReg *)0x4100810CUL) </span></div>
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<div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a507d998c5cc641f434475cbcae20f5d0"> 124</a></span> <span class="preprocessor">#define REG_PORT_OUT2 (*(RwReg *)0x41008110UL) </span></div>
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<div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a4dbb89796636fd5c6dfb34c06cbb49b7"> 125</a></span> <span class="preprocessor">#define REG_PORT_OUTCLR2 (*(RwReg *)0x41008114UL) </span></div>
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<div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a2c956e8d7634fb454c1a84ea67634b88"> 126</a></span> <span class="preprocessor">#define REG_PORT_OUTSET2 (*(RwReg *)0x41008118UL) </span></div>
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<div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#aba863da2144fcdc3b7d8e123f4092277"> 127</a></span> <span class="preprocessor">#define REG_PORT_OUTTGL2 (*(RwReg *)0x4100811CUL) </span></div>
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<div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a76da99db4e2d836ad27f8803a0252ffc"> 128</a></span> <span class="preprocessor">#define REG_PORT_IN2 (*(RoReg *)0x41008120UL) </span></div>
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<div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#aa36d2fd0669cc9c6dc7999c6f67f0ea2"> 129</a></span> <span class="preprocessor">#define REG_PORT_CTRL2 (*(RwReg *)0x41008124UL) </span></div>
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<div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a8e146dee7a6dd42fa8a1e991fd949474"> 130</a></span> <span class="preprocessor">#define REG_PORT_WRCONFIG2 (*(WoReg *)0x41008128UL) </span></div>
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<div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#af89f6c4f192391bee2733e726ff25b63"> 131</a></span> <span class="preprocessor">#define REG_PORT_EVCTRL2 (*(RwReg *)0x4100812CUL) </span></div>
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<div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a861b7f546ae0bb7f02905f5a30cd1c67"> 132</a></span> <span class="preprocessor">#define REG_PORT_PMUX2 (*(RwReg8 *)0x41008130UL) </span></div>
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<div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#ac17d95425b4880233144f4a9fda3f12b"> 133</a></span> <span class="preprocessor">#define REG_PORT_PINCFG2 (*(RwReg8 *)0x41008140UL) </span></div>
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<div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#adb974144b9fcaadfaf05ba87bb68e089"> 134</a></span> <span class="preprocessor">#define REG_PORT_DIR3 (*(RwReg *)0x41008180UL) </span></div>
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<div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#afb37489aebca03ae1447cc096efa49d4"> 135</a></span> <span class="preprocessor">#define REG_PORT_DIRCLR3 (*(RwReg *)0x41008184UL) </span></div>
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<div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a95c61d5508d06ed87eaf8e705e22d7d7"> 136</a></span> <span class="preprocessor">#define REG_PORT_DIRSET3 (*(RwReg *)0x41008188UL) </span></div>
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<div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a982edfcece99f6e44ce29b7689a61d9e"> 137</a></span> <span class="preprocessor">#define REG_PORT_DIRTGL3 (*(RwReg *)0x4100818CUL) </span></div>
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<div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a7098f84e744325310acee6d70fc22ee3"> 138</a></span> <span class="preprocessor">#define REG_PORT_OUT3 (*(RwReg *)0x41008190UL) </span></div>
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<div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a527c434ecfc889b9f7d68129675d769b"> 139</a></span> <span class="preprocessor">#define REG_PORT_OUTCLR3 (*(RwReg *)0x41008194UL) </span></div>
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<div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#aee2f7f8e3c5c5c89c69c8201625e0c8f"> 140</a></span> <span class="preprocessor">#define REG_PORT_OUTSET3 (*(RwReg *)0x41008198UL) </span></div>
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<div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a3530acbf836432a098d1447637055da4"> 141</a></span> <span class="preprocessor">#define REG_PORT_OUTTGL3 (*(RwReg *)0x4100819CUL) </span></div>
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<div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a4b3e245beaa6ebec94956e5d0b7fb417"> 142</a></span> <span class="preprocessor">#define REG_PORT_IN3 (*(RoReg *)0x410081A0UL) </span></div>
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<div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#aad460286154e843c5df4fab20ecb9c80"> 143</a></span> <span class="preprocessor">#define REG_PORT_CTRL3 (*(RwReg *)0x410081A4UL) </span></div>
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<div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a7175d2d84e153a5f5549772e59a19fd2"> 144</a></span> <span class="preprocessor">#define REG_PORT_WRCONFIG3 (*(WoReg *)0x410081A8UL) </span></div>
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<div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a5646355ad13c594ac708cf2b5ca47e5b"> 145</a></span> <span class="preprocessor">#define REG_PORT_EVCTRL3 (*(RwReg *)0x410081ACUL) </span></div>
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<div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a37e0d2dbf82c71a19abf8f91285523ef"> 146</a></span> <span class="preprocessor">#define REG_PORT_PMUX3 (*(RwReg8 *)0x410081B0UL) </span></div>
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<div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="instance_2port_8h.html#a08074a30f4db9891561655ac0d57012c"> 147</a></span> <span class="preprocessor">#define REG_PORT_PINCFG3 (*(RwReg8 *)0x410081C0UL) </span></div>
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<div class="line"><a name="l00148"></a><span class="lineno"> 148</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00149"></a><span class="lineno"> 149</span>  </div>
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<div class="line"><a name="l00150"></a><span class="lineno"> 150</span> <span class="comment">/* ========== Instance parameters for PORT peripheral ========== */</span></div>
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<div class="line"><a name="l00151"></a><span class="lineno"> 151</span> <span class="preprocessor">#define PORT_BITS 118 </span></div>
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<div class="line"><a name="l00152"></a><span class="lineno"> 152</span> <span class="preprocessor">#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00153"></a><span class="lineno"> 153</span> <span class="preprocessor">#define PORT_DIR_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</span></div>
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<div class="line"><a name="l00154"></a><span class="lineno"> 154</span> <span class="preprocessor">#define PORT_DRVSTR 1 // DRVSTR supported</span></div>
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<div class="line"><a name="l00155"></a><span class="lineno"> 155</span> <span class="preprocessor">#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00156"></a><span class="lineno"> 156</span> <span class="preprocessor">#define PORT_DRVSTR_IMPLEMENTED { 0xC8FFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</span></div>
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<div class="line"><a name="l00157"></a><span class="lineno"> 157</span> <span class="preprocessor">#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</span></div>
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<div class="line"><a name="l00158"></a><span class="lineno"> 158</span> <span class="preprocessor">#define PORT_EV_NUM 4 </span></div>
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<div class="line"><a name="l00159"></a><span class="lineno"> 159</span> <span class="preprocessor">#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00160"></a><span class="lineno"> 160</span> <span class="preprocessor">#define PORT_INEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</span></div>
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<div class="line"><a name="l00161"></a><span class="lineno"> 161</span> <span class="preprocessor">#define PORT_ODRAIN 0 // ODRAIN supported</span></div>
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<div class="line"><a name="l00162"></a><span class="lineno"> 162</span> <span class="preprocessor">#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00163"></a><span class="lineno"> 163</span> <span class="preprocessor">#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00164"></a><span class="lineno"> 164</span> <span class="preprocessor">#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00165"></a><span class="lineno"> 165</span> <span class="preprocessor">#define PORT_OUT_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</span></div>
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<div class="line"><a name="l00166"></a><span class="lineno"> 166</span> <span class="preprocessor">#define PORT_PIN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</span></div>
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<div class="line"><a name="l00167"></a><span class="lineno"> 167</span> <span class="preprocessor">#define PORT_PMUXBIT0_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00168"></a><span class="lineno"> 168</span> <span class="preprocessor">#define PORT_PMUXBIT0_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFC1F, 0x00301F03 }</span></div>
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<div class="line"><a name="l00169"></a><span class="lineno"> 169</span> <span class="preprocessor">#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00170"></a><span class="lineno"> 170</span> <span class="preprocessor">#define PORT_PMUXBIT1_IMPLEMENTED { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFCF0, 0x00300F00 }</span></div>
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<div class="line"><a name="l00171"></a><span class="lineno"> 171</span> <span class="preprocessor">#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00172"></a><span class="lineno"> 172</span> <span class="preprocessor">#define PORT_PMUXBIT2_IMPLEMENTED { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFC10, 0x00301F00 }</span></div>
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<div class="line"><a name="l00173"></a><span class="lineno"> 173</span> <span class="preprocessor">#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00174"></a><span class="lineno"> 174</span> <span class="preprocessor">#define PORT_PMUXBIT3_IMPLEMENTED { 0xCBFFFFF8, 0x33FFFFFF, 0x18FFF8C0, 0x00300000 }</span></div>
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<div class="line"><a name="l00175"></a><span class="lineno"> 175</span> <span class="preprocessor">#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00176"></a><span class="lineno"> 176</span> <span class="preprocessor">#define PORT_PMUXEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</span></div>
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<div class="line"><a name="l00177"></a><span class="lineno"> 177</span> <span class="preprocessor">#define PORT_PPP_IMPLEMENTED { 0x00000001 } // IOBUS2 implemented?</span></div>
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<div class="line"><a name="l00178"></a><span class="lineno"> 178</span> <span class="preprocessor">#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00179"></a><span class="lineno"> 179</span> <span class="preprocessor">#define PORT_PULLEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }</span></div>
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<div class="line"><a name="l00180"></a><span class="lineno"> 180</span> <span class="preprocessor">#define PORT_SLEWLIM 0 // SLEWLIM supported</span></div>
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<div class="line"><a name="l00181"></a><span class="lineno"> 181</span> <span class="preprocessor">#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00182"></a><span class="lineno"> 182</span> <span class="preprocessor">#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }</span></div>
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<div class="line"><a name="l00183"></a><span class="lineno"> 183</span>  </div>
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<div class="line"><a name="l00184"></a><span class="lineno"> 184</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_PORT_INSTANCE_ */</span><span class="preprocessor"></span></div>
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