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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/pcc.h File Reference</title>
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<a href="#define-members">Macros</a> </div>
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<div class="title">pcc.h File Reference</div> </div>
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<p>Instance description for PCC.
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<a href="#details">More...</a></p>
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<p><a href="instance_2pcc_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a0d0618e4a2885c7571415f084e063735"><td class="memItemLeft" align="right" valign="top"><a id="a0d0618e4a2885c7571415f084e063735"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pcc_8h.html#a0d0618e4a2885c7571415f084e063735">REG_PCC_MR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43002C00UL)</td></tr>
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<tr class="memdesc:a0d0618e4a2885c7571415f084e063735"><td class="mdescLeft"> </td><td class="mdescRight">(PCC) Mode Register <br /></td></tr>
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<tr class="separator:a0d0618e4a2885c7571415f084e063735"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a816f7fcd5f923c8533a616761a7bf5b8"><td class="memItemLeft" align="right" valign="top"><a id="a816f7fcd5f923c8533a616761a7bf5b8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pcc_8h.html#a816f7fcd5f923c8533a616761a7bf5b8">REG_PCC_IER</a>   (*(<a class="el" href="same54n19a_8h.html#ac0f96d4e8018367b38f527007cf0eafd">WoReg</a> *)0x43002C04UL)</td></tr>
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<tr class="memdesc:a816f7fcd5f923c8533a616761a7bf5b8"><td class="mdescLeft"> </td><td class="mdescRight">(PCC) Interrupt Enable Register <br /></td></tr>
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<tr class="separator:a816f7fcd5f923c8533a616761a7bf5b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3c01478ccb9ff303f96448be8117f1bd"><td class="memItemLeft" align="right" valign="top"><a id="a3c01478ccb9ff303f96448be8117f1bd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pcc_8h.html#a3c01478ccb9ff303f96448be8117f1bd">REG_PCC_IDR</a>   (*(<a class="el" href="same54n19a_8h.html#ac0f96d4e8018367b38f527007cf0eafd">WoReg</a> *)0x43002C08UL)</td></tr>
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<tr class="memdesc:a3c01478ccb9ff303f96448be8117f1bd"><td class="mdescLeft"> </td><td class="mdescRight">(PCC) Interrupt Disable Register <br /></td></tr>
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<tr class="separator:a3c01478ccb9ff303f96448be8117f1bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad26c55a7f9f0d7335a00bf9d4e3e9e95"><td class="memItemLeft" align="right" valign="top"><a id="ad26c55a7f9f0d7335a00bf9d4e3e9e95"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pcc_8h.html#ad26c55a7f9f0d7335a00bf9d4e3e9e95">REG_PCC_IMR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x43002C0CUL)</td></tr>
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<tr class="memdesc:ad26c55a7f9f0d7335a00bf9d4e3e9e95"><td class="mdescLeft"> </td><td class="mdescRight">(PCC) Interrupt Mask Register <br /></td></tr>
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<tr class="separator:ad26c55a7f9f0d7335a00bf9d4e3e9e95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a89412e4c0b5e989a1ff9533423a90256"><td class="memItemLeft" align="right" valign="top"><a id="a89412e4c0b5e989a1ff9533423a90256"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pcc_8h.html#a89412e4c0b5e989a1ff9533423a90256">REG_PCC_ISR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x43002C10UL)</td></tr>
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<tr class="memdesc:a89412e4c0b5e989a1ff9533423a90256"><td class="mdescLeft"> </td><td class="mdescRight">(PCC) Interrupt Status Register <br /></td></tr>
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<tr class="separator:a89412e4c0b5e989a1ff9533423a90256"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad3ed7e33398142d4b4159342672247bc"><td class="memItemLeft" align="right" valign="top"><a id="ad3ed7e33398142d4b4159342672247bc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pcc_8h.html#ad3ed7e33398142d4b4159342672247bc">REG_PCC_RHR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x43002C14UL)</td></tr>
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<tr class="memdesc:ad3ed7e33398142d4b4159342672247bc"><td class="mdescLeft"> </td><td class="mdescRight">(PCC) Reception Holding Register <br /></td></tr>
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<tr class="separator:ad3ed7e33398142d4b4159342672247bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac999ec65b03d7696717a59c3d3bff1ed"><td class="memItemLeft" align="right" valign="top"><a id="ac999ec65b03d7696717a59c3d3bff1ed"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pcc_8h.html#ac999ec65b03d7696717a59c3d3bff1ed">REG_PCC_WPMR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43002CE0UL)</td></tr>
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<tr class="memdesc:ac999ec65b03d7696717a59c3d3bff1ed"><td class="mdescLeft"> </td><td class="mdescRight">(PCC) Write Protection Mode Register <br /></td></tr>
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<tr class="separator:ac999ec65b03d7696717a59c3d3bff1ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6882ace0ee2cd94ff8825e5c9493f57a"><td class="memItemLeft" align="right" valign="top"><a id="a6882ace0ee2cd94ff8825e5c9493f57a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pcc_8h.html#a6882ace0ee2cd94ff8825e5c9493f57a">REG_PCC_WPSR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x43002CE4UL)</td></tr>
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<tr class="memdesc:a6882ace0ee2cd94ff8825e5c9493f57a"><td class="mdescLeft"> </td><td class="mdescRight">(PCC) Write Protection Status Register <br /></td></tr>
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<tr class="separator:a6882ace0ee2cd94ff8825e5c9493f57a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a52212e35cbac02bfc8c5a3fc9709cde5"><td class="memItemLeft" align="right" valign="top"><a id="a52212e35cbac02bfc8c5a3fc9709cde5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PCC_DATA_SIZE</b>   14</td></tr>
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<tr class="separator:a52212e35cbac02bfc8c5a3fc9709cde5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af062fde024a4a3fcb8939342d14c5b9e"><td class="memItemLeft" align="right" valign="top"><a id="af062fde024a4a3fcb8939342d14c5b9e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PCC_DMAC_ID_RX</b>   80</td></tr>
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<tr class="separator:af062fde024a4a3fcb8939342d14c5b9e"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for PCC. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="instance_2pcc_8h_source.html">pcc.h</a>.</p>
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