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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">pac.h File Reference</div> </div>
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<div class="contents">
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<p>Instance description for PAC.
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<a href="#details">More...</a></p>
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<p><a href="instance_2pac_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a2c813e24be0a5dc439dcacbec1d52c25"><td class="memItemLeft" align="right" valign="top"><a id="a2c813e24be0a5dc439dcacbec1d52c25"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a2c813e24be0a5dc439dcacbec1d52c25">REG_PAC_WRCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40000000UL)</td></tr>
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<tr class="memdesc:a2c813e24be0a5dc439dcacbec1d52c25"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Write control <br /></td></tr>
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<tr class="separator:a2c813e24be0a5dc439dcacbec1d52c25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a71e1115efb820c095f882852fe67ed69"><td class="memItemLeft" align="right" valign="top"><a id="a71e1115efb820c095f882852fe67ed69"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a71e1115efb820c095f882852fe67ed69">REG_PAC_EVCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40000004UL)</td></tr>
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<tr class="memdesc:a71e1115efb820c095f882852fe67ed69"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Event control <br /></td></tr>
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<tr class="separator:a71e1115efb820c095f882852fe67ed69"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a11262fd9a899c7ef8d646dca97f3e947"><td class="memItemLeft" align="right" valign="top"><a id="a11262fd9a899c7ef8d646dca97f3e947"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a11262fd9a899c7ef8d646dca97f3e947">REG_PAC_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40000008UL)</td></tr>
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<tr class="memdesc:a11262fd9a899c7ef8d646dca97f3e947"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Interrupt enable clear <br /></td></tr>
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<tr class="separator:a11262fd9a899c7ef8d646dca97f3e947"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7ca289c89f7f775f714e248d2b33ef8a"><td class="memItemLeft" align="right" valign="top"><a id="a7ca289c89f7f775f714e248d2b33ef8a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a7ca289c89f7f775f714e248d2b33ef8a">REG_PAC_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40000009UL)</td></tr>
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<tr class="memdesc:a7ca289c89f7f775f714e248d2b33ef8a"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Interrupt enable set <br /></td></tr>
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<tr class="separator:a7ca289c89f7f775f714e248d2b33ef8a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5d018523bfba841d97c1c82fdaae8dea"><td class="memItemLeft" align="right" valign="top"><a id="a5d018523bfba841d97c1c82fdaae8dea"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a5d018523bfba841d97c1c82fdaae8dea">REG_PAC_INTFLAGAHB</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40000010UL)</td></tr>
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<tr class="memdesc:a5d018523bfba841d97c1c82fdaae8dea"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Bridge interrupt flag status <br /></td></tr>
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<tr class="separator:a5d018523bfba841d97c1c82fdaae8dea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a171f4308d650dab214e7420b4124775d"><td class="memItemLeft" align="right" valign="top"><a id="a171f4308d650dab214e7420b4124775d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a171f4308d650dab214e7420b4124775d">REG_PAC_INTFLAGA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40000014UL)</td></tr>
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<tr class="memdesc:a171f4308d650dab214e7420b4124775d"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Peripheral interrupt flag status - Bridge A <br /></td></tr>
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<tr class="separator:a171f4308d650dab214e7420b4124775d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4e856217750c485cc5d820d4533484c7"><td class="memItemLeft" align="right" valign="top"><a id="a4e856217750c485cc5d820d4533484c7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a4e856217750c485cc5d820d4533484c7">REG_PAC_INTFLAGB</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40000018UL)</td></tr>
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<tr class="memdesc:a4e856217750c485cc5d820d4533484c7"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Peripheral interrupt flag status - Bridge B <br /></td></tr>
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<tr class="separator:a4e856217750c485cc5d820d4533484c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2167a8be15c3d5544d80bdf400bc7867"><td class="memItemLeft" align="right" valign="top"><a id="a2167a8be15c3d5544d80bdf400bc7867"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a2167a8be15c3d5544d80bdf400bc7867">REG_PAC_INTFLAGC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4000001CUL)</td></tr>
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<tr class="memdesc:a2167a8be15c3d5544d80bdf400bc7867"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Peripheral interrupt flag status - Bridge C <br /></td></tr>
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<tr class="separator:a2167a8be15c3d5544d80bdf400bc7867"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a11777bc0bc82acf1086dc08aa2190310"><td class="memItemLeft" align="right" valign="top"><a id="a11777bc0bc82acf1086dc08aa2190310"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a11777bc0bc82acf1086dc08aa2190310">REG_PAC_INTFLAGD</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40000020UL)</td></tr>
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<tr class="memdesc:a11777bc0bc82acf1086dc08aa2190310"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Peripheral interrupt flag status - Bridge D <br /></td></tr>
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<tr class="separator:a11777bc0bc82acf1086dc08aa2190310"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9ade455d04b34019bd988c7ecdf8e673"><td class="memItemLeft" align="right" valign="top"><a id="a9ade455d04b34019bd988c7ecdf8e673"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a9ade455d04b34019bd988c7ecdf8e673">REG_PAC_STATUSA</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x40000034UL)</td></tr>
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<tr class="memdesc:a9ade455d04b34019bd988c7ecdf8e673"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Peripheral write protection status - Bridge A <br /></td></tr>
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<tr class="separator:a9ade455d04b34019bd988c7ecdf8e673"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7333d344bbb2feffed565c389fe27f2b"><td class="memItemLeft" align="right" valign="top"><a id="a7333d344bbb2feffed565c389fe27f2b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a7333d344bbb2feffed565c389fe27f2b">REG_PAC_STATUSB</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x40000038UL)</td></tr>
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<tr class="memdesc:a7333d344bbb2feffed565c389fe27f2b"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Peripheral write protection status - Bridge B <br /></td></tr>
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<tr class="separator:a7333d344bbb2feffed565c389fe27f2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2730ed3b8127b8c31baa67645ef7af57"><td class="memItemLeft" align="right" valign="top"><a id="a2730ed3b8127b8c31baa67645ef7af57"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a2730ed3b8127b8c31baa67645ef7af57">REG_PAC_STATUSC</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4000003CUL)</td></tr>
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<tr class="memdesc:a2730ed3b8127b8c31baa67645ef7af57"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Peripheral write protection status - Bridge C <br /></td></tr>
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<tr class="separator:a2730ed3b8127b8c31baa67645ef7af57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5576464cd7ef03cc024872ed888b2583"><td class="memItemLeft" align="right" valign="top"><a id="a5576464cd7ef03cc024872ed888b2583"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2pac_8h.html#a5576464cd7ef03cc024872ed888b2583">REG_PAC_STATUSD</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x40000040UL)</td></tr>
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<tr class="memdesc:a5576464cd7ef03cc024872ed888b2583"><td class="mdescLeft"> </td><td class="mdescRight">(PAC) Peripheral write protection status - Bridge D <br /></td></tr>
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<tr class="separator:a5576464cd7ef03cc024872ed888b2583"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5937d48232ad35f419bd7ac60a8b4eee"><td class="memItemLeft" align="right" valign="top"><a id="a5937d48232ad35f419bd7ac60a8b4eee"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PAC_CLK_AHB_DOMAIN</b></td></tr>
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<tr class="separator:a5937d48232ad35f419bd7ac60a8b4eee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a800478e8ee70cda339215bcecc5965e9"><td class="memItemLeft" align="right" valign="top"><a id="a800478e8ee70cda339215bcecc5965e9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PAC_CLK_AHB_ID</b>   12</td></tr>
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<tr class="separator:a800478e8ee70cda339215bcecc5965e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab65a3f948109ab90db3e1cbb406a6055"><td class="memItemLeft" align="right" valign="top"><a id="ab65a3f948109ab90db3e1cbb406a6055"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>PAC_HPB_NUM</b>   4</td></tr>
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<tr class="separator:ab65a3f948109ab90db3e1cbb406a6055"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for PAC. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="instance_2pac_8h_source.html">pac.h</a>.</p>
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