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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">oscctrl.h</div> </div>
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<div class="contents">
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<a href="instance_2oscctrl_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_OSCCTRL_INSTANCE_</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_OSCCTRL_INSTANCE_</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for OSCCTRL peripheral ========== */</span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_OSCCTRL_EVCTRL (0x40001000) </span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_OSCCTRL_INTENCLR (0x40001004) </span></div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_OSCCTRL_INTENSET (0x40001008) </span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_OSCCTRL_INTFLAG (0x4000100C) </span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_OSCCTRL_STATUS (0x40001010) </span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_OSCCTRL_XOSCCTRL0 (0x40001014) </span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_OSCCTRL_XOSCCTRL1 (0x40001018) </span></div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_OSCCTRL_DFLLCTRLA (0x4000101C) </span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_OSCCTRL_DFLLCTRLB (0x40001020) </span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_OSCCTRL_DFLLVAL (0x40001024) </span></div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_OSCCTRL_DFLLMUL (0x40001028) </span></div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_OSCCTRL_DFLLSYNC (0x4000102C) </span></div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_OSCCTRL_DPLLCTRLA0 (0x40001030) </span></div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_OSCCTRL_DPLLRATIO0 (0x40001034) </span></div>
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<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_OSCCTRL_DPLLCTRLB0 (0x40001038) </span></div>
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<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_OSCCTRL_DPLLSYNCBUSY0 (0x4000103C) </span></div>
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<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_OSCCTRL_DPLLSTATUS0 (0x40001040) </span></div>
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<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_OSCCTRL_DPLLCTRLA1 (0x40001044) </span></div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_OSCCTRL_DPLLRATIO1 (0x40001048) </span></div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_OSCCTRL_DPLLCTRLB1 (0x4000104C) </span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_OSCCTRL_DPLLSYNCBUSY1 (0x40001050) </span></div>
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<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_OSCCTRL_DPLLSTATUS1 (0x40001054) </span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#else</span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#aff644ca116bc0af046a7964efa84682b"> 58</a></span> <span class="preprocessor">#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001000UL) </span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a7e9b622e8fc95d623b408abd4b1545e2"> 59</a></span> <span class="preprocessor">#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001004UL) </span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#ae410e6f2c6a7e5b42b941f2e5b56b4e1"> 60</a></span> <span class="preprocessor">#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001008UL) </span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a6b40cae9ee4cef4935526df784895d4d"> 61</a></span> <span class="preprocessor">#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x4000100CUL) </span></div>
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<div class="line"><a name="l00062"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#ad52e8e5549de332d10ba70fe66c07e81"> 62</a></span> <span class="preprocessor">#define REG_OSCCTRL_STATUS (*(RoReg *)0x40001010UL) </span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a9ef36078deda7ab0b03cdab64a1fd53b"> 63</a></span> <span class="preprocessor">#define REG_OSCCTRL_XOSCCTRL0 (*(RwReg *)0x40001014UL) </span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#ae300304038901ce1e14013d528b95865"> 64</a></span> <span class="preprocessor">#define REG_OSCCTRL_XOSCCTRL1 (*(RwReg *)0x40001018UL) </span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a68979fd83198a3dabd3eadfdd3bc29ae"> 65</a></span> <span class="preprocessor">#define REG_OSCCTRL_DFLLCTRLA (*(RwReg8 *)0x4000101CUL) </span></div>
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<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#af6c936661ce71c06830dc7f65ff9cf36"> 66</a></span> <span class="preprocessor">#define REG_OSCCTRL_DFLLCTRLB (*(RwReg8 *)0x40001020UL) </span></div>
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<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a6aa758f4e1e1ccf9227e53f98fe05b53"> 67</a></span> <span class="preprocessor">#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x40001024UL) </span></div>
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<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a5156a9f0b7a33b0bce42e8636aaee7a4"> 68</a></span> <span class="preprocessor">#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001028UL) </span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#aca324bd12a40210f15fffe81693f5579"> 69</a></span> <span class="preprocessor">#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x4000102CUL) </span></div>
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<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#aac2c32801745e843dfade2fc83d71ba8"> 70</a></span> <span class="preprocessor">#define REG_OSCCTRL_DPLLCTRLA0 (*(RwReg8 *)0x40001030UL) </span></div>
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<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a5547f4c945f46044fed11b2efec37af3"> 71</a></span> <span class="preprocessor">#define REG_OSCCTRL_DPLLRATIO0 (*(RwReg *)0x40001034UL) </span></div>
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<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a15039c180349b6c462a7a974cc2f5488"> 72</a></span> <span class="preprocessor">#define REG_OSCCTRL_DPLLCTRLB0 (*(RwReg *)0x40001038UL) </span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a7d8232058d72655451c93bcf6e0fec97"> 73</a></span> <span class="preprocessor">#define REG_OSCCTRL_DPLLSYNCBUSY0 (*(RoReg *)0x4000103CUL) </span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a47e3f738aa0b4f77964259636649300b"> 74</a></span> <span class="preprocessor">#define REG_OSCCTRL_DPLLSTATUS0 (*(RoReg *)0x40001040UL) </span></div>
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<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a2b784da749c980a75b7dbcb80b187c06"> 75</a></span> <span class="preprocessor">#define REG_OSCCTRL_DPLLCTRLA1 (*(RwReg8 *)0x40001044UL) </span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a1a6b8c6f57ff69aec079be6f02ff4283"> 76</a></span> <span class="preprocessor">#define REG_OSCCTRL_DPLLRATIO1 (*(RwReg *)0x40001048UL) </span></div>
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<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a4fad8b722c4ad1d05a3d1a13276d9510"> 77</a></span> <span class="preprocessor">#define REG_OSCCTRL_DPLLCTRLB1 (*(RwReg *)0x4000104CUL) </span></div>
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<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a2f53c0ec3adef4e0583a63009d12c028"> 78</a></span> <span class="preprocessor">#define REG_OSCCTRL_DPLLSYNCBUSY1 (*(RoReg *)0x40001050UL) </span></div>
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<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="instance_2oscctrl_8h.html#a62baf8ad29c2035310513cf224711c7a"> 79</a></span> <span class="preprocessor">#define REG_OSCCTRL_DPLLSTATUS1 (*(RoReg *)0x40001054UL) </span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"> 80</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"> 81</span>  </div>
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<div class="line"><a name="l00082"></a><span class="lineno"> 82</span> <span class="comment">/* ========== Instance parameters for OSCCTRL peripheral ========== */</span></div>
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<div class="line"><a name="l00083"></a><span class="lineno"> 83</span> <span class="preprocessor">#define OSCCTRL_DFLLS_NUM 1 // Number of DFLLs</span></div>
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<div class="line"><a name="l00084"></a><span class="lineno"> 84</span> <span class="preprocessor">#define OSCCTRL_DFLL_IMPLEMENTED 1 // DFLL implemented</span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"> 85</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_BIASTESTPT_IMPLEMENTED 0 // DFLL48M bias test mode implemented</span></div>
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<div class="line"><a name="l00086"></a><span class="lineno"> 86</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_CDACSTEPSIZE_SIZE 2 // Size COARSE DAC STEP</span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"> 87</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_COARSE_RESET_VALUE 32 // DFLL48M Frequency Coarse Reset Value (Before Calibration)</span></div>
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<div class="line"><a name="l00088"></a><span class="lineno"> 88</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_COARSE_SIZE 6 // Size COARSE CALIBRATION</span></div>
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<div class="line"><a name="l00089"></a><span class="lineno"> 89</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_ENABLE_RESET_VALUE 1 // Run oscillator at reset</span></div>
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<div class="line"><a name="l00090"></a><span class="lineno"> 90</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_FDACSTEPSIZE_SIZE 2 // Size FINE DAC STEP</span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"> 91</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_FINE_RESET_VALUE 128 // DFLL48M Frequency Fine Reset Value (Before Calibration)</span></div>
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<div class="line"><a name="l00092"></a><span class="lineno"> 92</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_FINE_SIZE 8 // Size FINE CALIBRATION</span></div>
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<div class="line"><a name="l00093"></a><span class="lineno"> 93</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested</span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode</span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_TCAL_SIZE 4 // Size TEMP CALIBRATION</span></div>
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<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_TCBIAS_SIZE 2 // Size TC BIAS CALIBRATION</span></div>
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<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_TESTPTSEL_SIZE 3 // Size TEST POINT SELECTOR</span></div>
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<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_WAITLOCK_ACTIVE 1 // Enable Wait Lock Feature</span></div>
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<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor">#define OSCCTRL_DPLLS_NUM 2 // Number of DPLLs</span></div>
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<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor">#define OSCCTRL_DPLL0_IMPLEMENTED 1 // DPLL0 implemented</span></div>
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<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor">#define OSCCTRL_DPLL0_I12ND_I12NDFRAC_PAD_CONTROL 0 // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead</span></div>
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<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="preprocessor">#define OSCCTRL_DPLL0_OCC_IMPLEMENTED 1 // DPLL0 OCC Implemented</span></div>
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<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#define OSCCTRL_DPLL1_IMPLEMENTED 1 // DPLL1 implemented</span></div>
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<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> <span class="preprocessor">#define OSCCTRL_DPLL1_I12ND_I12NDFRAC_PAD_CONTROL 0 // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead</span></div>
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<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor">#define OSCCTRL_DPLL1_OCC_IMPLEMENTED 0 // DPLL1 OCC Implemented</span></div>
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<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> <span class="preprocessor">#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48</span></div>
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<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="preprocessor">#define OSCCTRL_GCLK_ID_FDPLL0 1 // Index of Generic Clock for DPLL0</span></div>
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<div class="line"><a name="l00108"></a><span class="lineno"> 108</span> <span class="preprocessor">#define OSCCTRL_GCLK_ID_FDPLL1 2 // Index of Generic Clock for DPLL1</span></div>
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<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor">#define OSCCTRL_GCLK_ID_FDPLL032K 3 // Index of Generic Clock for DPLL0 32K</span></div>
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<div class="line"><a name="l00110"></a><span class="lineno"> 110</span> <span class="preprocessor">#define OSCCTRL_GCLK_ID_FDPLL132K 3 // Index of Generic Clock for DPLL1 32K</span></div>
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<div class="line"><a name="l00111"></a><span class="lineno"> 111</span> <span class="preprocessor">#define OSCCTRL_OSC16M_IMPLEMENTED 0 // OSC16M implemented</span></div>
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<div class="line"><a name="l00112"></a><span class="lineno"> 112</span> <span class="preprocessor">#define OSCCTRL_OSC48M_IMPLEMENTED 0 // OSC48M implemented</span></div>
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<div class="line"><a name="l00113"></a><span class="lineno"> 113</span> <span class="preprocessor">#define OSCCTRL_OSC48M_NUM 1 </span></div>
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<div class="line"><a name="l00114"></a><span class="lineno"> 114</span> <span class="preprocessor">#define OSCCTRL_RCOSCS_NUM 1 // Number of RCOSCs (min 1)</span></div>
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<div class="line"><a name="l00115"></a><span class="lineno"> 115</span> <span class="preprocessor">#define OSCCTRL_XOSCS_NUM 2 // Number of XOSCs</span></div>
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<div class="line"><a name="l00116"></a><span class="lineno"> 116</span> <span class="preprocessor">#define OSCCTRL_XOSC0_CFD_CLK_SELECT_SIZE 4 // Clock fail prescaler size</span></div>
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<div class="line"><a name="l00117"></a><span class="lineno"> 117</span> <span class="preprocessor">#define OSCCTRL_XOSC0_CFD_IMPLEMENTED 1 // Clock fail detected for xosc implemented</span></div>
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<div class="line"><a name="l00118"></a><span class="lineno"> 118</span> <span class="preprocessor">#define OSCCTRL_XOSC0_IMPLEMENTED 1 // XOSC0 implemented</span></div>
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<div class="line"><a name="l00119"></a><span class="lineno"> 119</span> <span class="preprocessor">#define OSCCTRL_XOSC0_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested</span></div>
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<div class="line"><a name="l00120"></a><span class="lineno"> 120</span> <span class="preprocessor">#define OSCCTRL_XOSC0_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode</span></div>
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<div class="line"><a name="l00121"></a><span class="lineno"> 121</span> <span class="preprocessor">#define OSCCTRL_XOSC1_CFD_CLK_SELECT_SIZE 4 // Clock fail prescaler size</span></div>
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<div class="line"><a name="l00122"></a><span class="lineno"> 122</span> <span class="preprocessor">#define OSCCTRL_XOSC1_CFD_IMPLEMENTED 1 // Clock fail detected for xosc implemented</span></div>
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<div class="line"><a name="l00123"></a><span class="lineno"> 123</span> <span class="preprocessor">#define OSCCTRL_XOSC1_IMPLEMENTED 1 // XOSC1 implemented</span></div>
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<div class="line"><a name="l00124"></a><span class="lineno"> 124</span> <span class="preprocessor">#define OSCCTRL_XOSC1_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested</span></div>
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<div class="line"><a name="l00125"></a><span class="lineno"> 125</span> <span class="preprocessor">#define OSCCTRL_XOSC1_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode</span></div>
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<div class="line"><a name="l00126"></a><span class="lineno"> 126</span> <span class="preprocessor">#define OSCCTRL_DFLL48M_VERSION 0x100 </span></div>
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<div class="line"><a name="l00127"></a><span class="lineno"> 127</span> <span class="preprocessor">#define OSCCTRL_FDPLL_VERSION 0x100 </span></div>
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<div class="line"><a name="l00128"></a><span class="lineno"> 128</span> <span class="preprocessor">#define OSCCTRL_XOSC_VERSION 0x100 </span></div>
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<div class="line"><a name="l00129"></a><span class="lineno"> 129</span>  </div>
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<div class="line"><a name="l00130"></a><span class="lineno"> 130</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_OSCCTRL_INSTANCE_ */</span><span class="preprocessor"></span></div>
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