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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/osc32kctrl.h File Reference</title>
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<div class="title">osc32kctrl.h File Reference</div> </div>
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<div class="contents">
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<p>Instance description for OSC32KCTRL.
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<a href="#details">More...</a></p>
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<p><a href="instance_2osc32kctrl_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a4516c574ba0ca7f3cb40db4d3ff82120"><td class="memItemLeft" align="right" valign="top"><a id="a4516c574ba0ca7f3cb40db4d3ff82120"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2osc32kctrl_8h.html#a4516c574ba0ca7f3cb40db4d3ff82120">REG_OSC32KCTRL_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001400UL)</td></tr>
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<tr class="memdesc:a4516c574ba0ca7f3cb40db4d3ff82120"><td class="mdescLeft"> </td><td class="mdescRight">(OSC32KCTRL) Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a4516c574ba0ca7f3cb40db4d3ff82120"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3cf5149238ecdf4860e34a186d944754"><td class="memItemLeft" align="right" valign="top"><a id="a3cf5149238ecdf4860e34a186d944754"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2osc32kctrl_8h.html#a3cf5149238ecdf4860e34a186d944754">REG_OSC32KCTRL_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001404UL)</td></tr>
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<tr class="memdesc:a3cf5149238ecdf4860e34a186d944754"><td class="mdescLeft"> </td><td class="mdescRight">(OSC32KCTRL) Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a3cf5149238ecdf4860e34a186d944754"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae8fc194efc88d5139c9193fa77912260"><td class="memItemLeft" align="right" valign="top"><a id="ae8fc194efc88d5139c9193fa77912260"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2osc32kctrl_8h.html#ae8fc194efc88d5139c9193fa77912260">REG_OSC32KCTRL_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40001408UL)</td></tr>
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<tr class="memdesc:ae8fc194efc88d5139c9193fa77912260"><td class="mdescLeft"> </td><td class="mdescRight">(OSC32KCTRL) Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:ae8fc194efc88d5139c9193fa77912260"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4d456335448505372200041d529e31cd"><td class="memItemLeft" align="right" valign="top"><a id="a4d456335448505372200041d529e31cd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2osc32kctrl_8h.html#a4d456335448505372200041d529e31cd">REG_OSC32KCTRL_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4000140CUL)</td></tr>
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<tr class="memdesc:a4d456335448505372200041d529e31cd"><td class="mdescLeft"> </td><td class="mdescRight">(OSC32KCTRL) Power and Clocks Status <br /></td></tr>
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<tr class="separator:a4d456335448505372200041d529e31cd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af380aa5c6e8a9185e6e919eb0fe494b6"><td class="memItemLeft" align="right" valign="top"><a id="af380aa5c6e8a9185e6e919eb0fe494b6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2osc32kctrl_8h.html#af380aa5c6e8a9185e6e919eb0fe494b6">REG_OSC32KCTRL_RTCCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40001410UL)</td></tr>
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<tr class="memdesc:af380aa5c6e8a9185e6e919eb0fe494b6"><td class="mdescLeft"> </td><td class="mdescRight">(OSC32KCTRL) RTC Clock Selection <br /></td></tr>
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<tr class="separator:af380aa5c6e8a9185e6e919eb0fe494b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8b60d5a4b5259da502c462794c7e777"><td class="memItemLeft" align="right" valign="top"><a id="af8b60d5a4b5259da502c462794c7e777"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2osc32kctrl_8h.html#af8b60d5a4b5259da502c462794c7e777">REG_OSC32KCTRL_XOSC32K</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x40001414UL)</td></tr>
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<tr class="memdesc:af8b60d5a4b5259da502c462794c7e777"><td class="mdescLeft"> </td><td class="mdescRight">(OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control <br /></td></tr>
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<tr class="separator:af8b60d5a4b5259da502c462794c7e777"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a95f42726eee4ca3b74c9d3fb36a7e86a"><td class="memItemLeft" align="right" valign="top"><a id="a95f42726eee4ca3b74c9d3fb36a7e86a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2osc32kctrl_8h.html#a95f42726eee4ca3b74c9d3fb36a7e86a">REG_OSC32KCTRL_CFDCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40001416UL)</td></tr>
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<tr class="memdesc:a95f42726eee4ca3b74c9d3fb36a7e86a"><td class="mdescLeft"> </td><td class="mdescRight">(OSC32KCTRL) Clock Failure Detector Control <br /></td></tr>
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<tr class="separator:a95f42726eee4ca3b74c9d3fb36a7e86a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae4a45caca1072ef739d5d0ea28a6621c"><td class="memItemLeft" align="right" valign="top"><a id="ae4a45caca1072ef739d5d0ea28a6621c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2osc32kctrl_8h.html#ae4a45caca1072ef739d5d0ea28a6621c">REG_OSC32KCTRL_EVCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40001417UL)</td></tr>
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<tr class="memdesc:ae4a45caca1072ef739d5d0ea28a6621c"><td class="mdescLeft"> </td><td class="mdescRight">(OSC32KCTRL) Event Control <br /></td></tr>
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<tr class="separator:ae4a45caca1072ef739d5d0ea28a6621c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5c7e17f5a9ed84dfc0ad0c6c611469b6"><td class="memItemLeft" align="right" valign="top"><a id="a5c7e17f5a9ed84dfc0ad0c6c611469b6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2osc32kctrl_8h.html#a5c7e17f5a9ed84dfc0ad0c6c611469b6">REG_OSC32KCTRL_OSCULP32K</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4000141CUL)</td></tr>
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<tr class="memdesc:a5c7e17f5a9ed84dfc0ad0c6c611469b6"><td class="mdescLeft"> </td><td class="mdescRight">(OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control <br /></td></tr>
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<tr class="separator:a5c7e17f5a9ed84dfc0ad0c6c611469b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad43ecf0cd03e57e952a51c0841168932"><td class="memItemLeft" align="right" valign="top"><a id="ad43ecf0cd03e57e952a51c0841168932"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>OSC32KCTRL_OSC32K_COARSE_CALIB_MSB</b>   0</td></tr>
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<tr class="separator:ad43ecf0cd03e57e952a51c0841168932"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for OSC32KCTRL. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="instance_2osc32kctrl_8h_source.html">osc32kctrl.h</a>.</p>
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