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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/mclk.h File Reference</title>
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<a href="#define-members">Macros</a> </div>
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<div class="title">mclk.h File Reference</div> </div>
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<div class="contents">
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<p>Instance description for MCLK.
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<a href="#details">More...</a></p>
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<p><a href="instance_2mclk_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a802dfb521a453e6332d2610468547db7"><td class="memItemLeft" align="right" valign="top"><a id="a802dfb521a453e6332d2610468547db7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2mclk_8h.html#a802dfb521a453e6332d2610468547db7">REG_MCLK_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40000801UL)</td></tr>
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<tr class="memdesc:a802dfb521a453e6332d2610468547db7"><td class="mdescLeft"> </td><td class="mdescRight">(MCLK) Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a802dfb521a453e6332d2610468547db7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a915113896b34c37330c2a9ff1f94eeed"><td class="memItemLeft" align="right" valign="top"><a id="a915113896b34c37330c2a9ff1f94eeed"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2mclk_8h.html#a915113896b34c37330c2a9ff1f94eeed">REG_MCLK_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40000802UL)</td></tr>
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<tr class="memdesc:a915113896b34c37330c2a9ff1f94eeed"><td class="mdescLeft"> </td><td class="mdescRight">(MCLK) Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a915113896b34c37330c2a9ff1f94eeed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0774b23bb760b55775f8670e65382f56"><td class="memItemLeft" align="right" valign="top"><a id="a0774b23bb760b55775f8670e65382f56"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2mclk_8h.html#a0774b23bb760b55775f8670e65382f56">REG_MCLK_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40000803UL)</td></tr>
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<tr class="memdesc:a0774b23bb760b55775f8670e65382f56"><td class="mdescLeft"> </td><td class="mdescRight">(MCLK) Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:a0774b23bb760b55775f8670e65382f56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9a5903dabe1e3e0c6ff4b78f64d92038"><td class="memItemLeft" align="right" valign="top"><a id="a9a5903dabe1e3e0c6ff4b78f64d92038"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2mclk_8h.html#a9a5903dabe1e3e0c6ff4b78f64d92038">REG_MCLK_HSDIV</a>   (*(<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> *)0x40000804UL)</td></tr>
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<tr class="memdesc:a9a5903dabe1e3e0c6ff4b78f64d92038"><td class="mdescLeft"> </td><td class="mdescRight">(MCLK) HS Clock Division <br /></td></tr>
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<tr class="separator:a9a5903dabe1e3e0c6ff4b78f64d92038"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3fa045bead3e2219138def910cccce75"><td class="memItemLeft" align="right" valign="top"><a id="a3fa045bead3e2219138def910cccce75"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2mclk_8h.html#a3fa045bead3e2219138def910cccce75">REG_MCLK_CPUDIV</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40000805UL)</td></tr>
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<tr class="memdesc:a3fa045bead3e2219138def910cccce75"><td class="mdescLeft"> </td><td class="mdescRight">(MCLK) CPU Clock Division <br /></td></tr>
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<tr class="separator:a3fa045bead3e2219138def910cccce75"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a19e1955b46ba4babdb58e95656f0988a"><td class="memItemLeft" align="right" valign="top"><a id="a19e1955b46ba4babdb58e95656f0988a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2mclk_8h.html#a19e1955b46ba4babdb58e95656f0988a">REG_MCLK_AHBMASK</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40000810UL)</td></tr>
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<tr class="memdesc:a19e1955b46ba4babdb58e95656f0988a"><td class="mdescLeft"> </td><td class="mdescRight">(MCLK) AHB Mask <br /></td></tr>
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<tr class="separator:a19e1955b46ba4babdb58e95656f0988a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaa155650364f991d950aa6730b2a8384"><td class="memItemLeft" align="right" valign="top"><a id="aaa155650364f991d950aa6730b2a8384"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2mclk_8h.html#aaa155650364f991d950aa6730b2a8384">REG_MCLK_APBAMASK</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40000814UL)</td></tr>
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<tr class="memdesc:aaa155650364f991d950aa6730b2a8384"><td class="mdescLeft"> </td><td class="mdescRight">(MCLK) APBA Mask <br /></td></tr>
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<tr class="separator:aaa155650364f991d950aa6730b2a8384"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aebc83a404d1bac68b91b34df4f12792b"><td class="memItemLeft" align="right" valign="top"><a id="aebc83a404d1bac68b91b34df4f12792b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2mclk_8h.html#aebc83a404d1bac68b91b34df4f12792b">REG_MCLK_APBBMASK</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40000818UL)</td></tr>
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<tr class="memdesc:aebc83a404d1bac68b91b34df4f12792b"><td class="mdescLeft"> </td><td class="mdescRight">(MCLK) APBB Mask <br /></td></tr>
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<tr class="separator:aebc83a404d1bac68b91b34df4f12792b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa07a18c90289574b867282e372273eae"><td class="memItemLeft" align="right" valign="top"><a id="aa07a18c90289574b867282e372273eae"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2mclk_8h.html#aa07a18c90289574b867282e372273eae">REG_MCLK_APBCMASK</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4000081CUL)</td></tr>
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<tr class="memdesc:aa07a18c90289574b867282e372273eae"><td class="mdescLeft"> </td><td class="mdescRight">(MCLK) APBC Mask <br /></td></tr>
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<tr class="separator:aa07a18c90289574b867282e372273eae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5268d589df71f8b26715ef3187d7d978"><td class="memItemLeft" align="right" valign="top"><a id="a5268d589df71f8b26715ef3187d7d978"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2mclk_8h.html#a5268d589df71f8b26715ef3187d7d978">REG_MCLK_APBDMASK</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x40000820UL)</td></tr>
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<tr class="memdesc:a5268d589df71f8b26715ef3187d7d978"><td class="mdescLeft"> </td><td class="mdescRight">(MCLK) APBD Mask <br /></td></tr>
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<tr class="separator:a5268d589df71f8b26715ef3187d7d978"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae060818e15612d11a69d8d633ed6d372"><td class="memItemLeft" align="right" valign="top"><a id="ae060818e15612d11a69d8d633ed6d372"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>MCLK_SYSTEM_CLOCK</b>   48000000</td></tr>
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<tr class="separator:ae060818e15612d11a69d8d633ed6d372"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for MCLK. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="instance_2mclk_8h_source.html">mclk.h</a>.</p>
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