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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/dsu.h Source File</title>
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<div id="projectname">SAME54P20A Test Project
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">dsu.h</div> </div>
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<div class="contents">
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<a href="instance_2dsu_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_DSU_INSTANCE_</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_DSU_INSTANCE_</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for DSU peripheral ========== */</span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_DSU_CTRL (0x41002000) </span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_DSU_STATUSA (0x41002001) </span></div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_DSU_STATUSB (0x41002002) </span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_DSU_ADDR (0x41002004) </span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_DSU_LENGTH (0x41002008) </span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_DSU_DATA (0x4100200C) </span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_DSU_DCC0 (0x41002010) </span></div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_DSU_DCC1 (0x41002014) </span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_DSU_DID (0x41002018) </span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_DSU_CFG (0x4100201C) </span></div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_DSU_ENTRY0 (0x41003000) </span></div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_DSU_ENTRY1 (0x41003004) </span></div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_DSU_END (0x41003008) </span></div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_DSU_MEMTYPE (0x41003FCC) </span></div>
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<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_DSU_PID4 (0x41003FD0) </span></div>
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<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_DSU_PID5 (0x41003FD4) </span></div>
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<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_DSU_PID6 (0x41003FD8) </span></div>
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<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_DSU_PID7 (0x41003FDC) </span></div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_DSU_PID0 (0x41003FE0) </span></div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_DSU_PID1 (0x41003FE4) </span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_DSU_PID2 (0x41003FE8) </span></div>
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<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_DSU_PID3 (0x41003FEC) </span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define REG_DSU_CID0 (0x41003FF0) </span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define REG_DSU_CID1 (0x41003FF4) </span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#define REG_DSU_CID2 (0x41003FF8) </span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor">#define REG_DSU_CID3 (0x41003FFC) </span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="preprocessor">#else</span></div>
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<div class="line"><a name="l00062"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#ae17c72b6a745f941327bfa46a6692ce8"> 62</a></span> <span class="preprocessor">#define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) </span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#ae06d68d5e28613ccb51ed17dca062817"> 63</a></span> <span class="preprocessor">#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) </span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a0fc027dd9bd0cec26cf63d267fe154f7"> 64</a></span> <span class="preprocessor">#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) </span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a2ee1fbb234a693105acadc785d24efae"> 65</a></span> <span class="preprocessor">#define REG_DSU_ADDR (*(RwReg *)0x41002004UL) </span></div>
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<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#aacdf19047f3059012446eb9563bc9e2e"> 66</a></span> <span class="preprocessor">#define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) </span></div>
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<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#af4dea8f8bf99b393b669470fcd047ace"> 67</a></span> <span class="preprocessor">#define REG_DSU_DATA (*(RwReg *)0x4100200CUL) </span></div>
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<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a30c2baa6ed6e0977650fa2db6619919f"> 68</a></span> <span class="preprocessor">#define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) </span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a593d74e4d66b106f7deec50cf190a7fd"> 69</a></span> <span class="preprocessor">#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) </span></div>
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<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#aed16fccc4ab0e060b2a3dbaddd7b683a"> 70</a></span> <span class="preprocessor">#define REG_DSU_DID (*(RoReg *)0x41002018UL) </span></div>
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<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#afcf7ada50381d999f257f9c1d533ea68"> 71</a></span> <span class="preprocessor">#define REG_DSU_CFG (*(RwReg *)0x4100201CUL) </span></div>
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<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#ad8af65a30bc18e5ff87c52e6177300f8"> 72</a></span> <span class="preprocessor">#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) </span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a1b38af2a82d68d8a73c22296df883346"> 73</a></span> <span class="preprocessor">#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) </span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a7396a90608b11defadbff9f636863a1c"> 74</a></span> <span class="preprocessor">#define REG_DSU_END (*(RoReg *)0x41003008UL) </span></div>
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<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#acec2f871a280f435396bcc69e2948d0f"> 75</a></span> <span class="preprocessor">#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) </span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a30ceced7787ad791bafa40d2ec6838a4"> 76</a></span> <span class="preprocessor">#define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) </span></div>
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<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a5413add31ded06422b78505d808cf6bf"> 77</a></span> <span class="preprocessor">#define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) </span></div>
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<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a4e725f47dfbce1a7aa567c1ccabbb94d"> 78</a></span> <span class="preprocessor">#define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) </span></div>
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<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a740bf32b8af9f432c2d78a5159d3964f"> 79</a></span> <span class="preprocessor">#define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) </span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#ad5aaa625886c89be3c72fba3823eff34"> 80</a></span> <span class="preprocessor">#define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) </span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a173e7bcfc7dfaac976882f1bc4bdc735"> 81</a></span> <span class="preprocessor">#define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) </span></div>
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<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a10216c226fd45ee30ca466f25867395a"> 82</a></span> <span class="preprocessor">#define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) </span></div>
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<div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a463fa28d9787bbaeb82afd253e1d8acf"> 83</a></span> <span class="preprocessor">#define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) </span></div>
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<div class="line"><a name="l00084"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#a0f9e40fce594549bbf87b0fb45e8e8d3"> 84</a></span> <span class="preprocessor">#define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) </span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#ab009a9f2376853164a097c90af1dcda8"> 85</a></span> <span class="preprocessor">#define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) </span></div>
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<div class="line"><a name="l00086"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#ac0bbcd6daf6851e1cd49f001d7478997"> 86</a></span> <span class="preprocessor">#define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) </span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"><a class="line" href="instance_2dsu_8h.html#ac6c8fbe20ec18ace2351c51eb28266b4"> 87</a></span> <span class="preprocessor">#define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) </span></div>
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<div class="line"><a name="l00088"></a><span class="lineno"> 88</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00089"></a><span class="lineno"> 89</span>  </div>
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<div class="line"><a name="l00090"></a><span class="lineno"> 90</span> <span class="comment">/* ========== Instance parameters for DSU peripheral ========== */</span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"> 91</span> <span class="preprocessor">#define DSU_CLK_AHB_ID 4 </span></div>
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<div class="line"><a name="l00092"></a><span class="lineno"> 92</span> <span class="preprocessor">#define DSU_DMAC_ID_DCC0 2 // DMAC ID for DCC0 register</span></div>
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<div class="line"><a name="l00093"></a><span class="lineno"> 93</span> <span class="preprocessor">#define DSU_DMAC_ID_DCC1 3 // DMAC ID for DCC1 register</span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span>  </div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_DSU_INSTANCE_ */</span><span class="preprocessor"></span></div>
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