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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<a href="#define-members">Macros</a> </div>
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<div class="title">dsu.h File Reference</div> </div>
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</div><!--header-->
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<div class="contents">
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<p>Instance description for DSU.
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<a href="#details">More...</a></p>
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<p><a href="instance_2dsu_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:ae17c72b6a745f941327bfa46a6692ce8"><td class="memItemLeft" align="right" valign="top"><a id="ae17c72b6a745f941327bfa46a6692ce8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#ae17c72b6a745f941327bfa46a6692ce8">REG_DSU_CTRL</a>   (*(<a class="el" href="same54n19a_8h.html#a5e336e5a36ee12ebeafb021108e5275b">WoReg8</a> *)0x41002000UL)</td></tr>
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<tr class="memdesc:ae17c72b6a745f941327bfa46a6692ce8"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Control <br /></td></tr>
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<tr class="separator:ae17c72b6a745f941327bfa46a6692ce8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae06d68d5e28613ccb51ed17dca062817"><td class="memItemLeft" align="right" valign="top"><a id="ae06d68d5e28613ccb51ed17dca062817"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#ae06d68d5e28613ccb51ed17dca062817">REG_DSU_STATUSA</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41002001UL)</td></tr>
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<tr class="memdesc:ae06d68d5e28613ccb51ed17dca062817"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Status A <br /></td></tr>
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<tr class="separator:ae06d68d5e28613ccb51ed17dca062817"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0fc027dd9bd0cec26cf63d267fe154f7"><td class="memItemLeft" align="right" valign="top"><a id="a0fc027dd9bd0cec26cf63d267fe154f7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a0fc027dd9bd0cec26cf63d267fe154f7">REG_DSU_STATUSB</a>   (*(<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> *)0x41002002UL)</td></tr>
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<tr class="memdesc:a0fc027dd9bd0cec26cf63d267fe154f7"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Status B <br /></td></tr>
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<tr class="separator:a0fc027dd9bd0cec26cf63d267fe154f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2ee1fbb234a693105acadc785d24efae"><td class="memItemLeft" align="right" valign="top"><a id="a2ee1fbb234a693105acadc785d24efae"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a2ee1fbb234a693105acadc785d24efae">REG_DSU_ADDR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41002004UL)</td></tr>
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<tr class="memdesc:a2ee1fbb234a693105acadc785d24efae"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Address <br /></td></tr>
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<tr class="separator:a2ee1fbb234a693105acadc785d24efae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aacdf19047f3059012446eb9563bc9e2e"><td class="memItemLeft" align="right" valign="top"><a id="aacdf19047f3059012446eb9563bc9e2e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#aacdf19047f3059012446eb9563bc9e2e">REG_DSU_LENGTH</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41002008UL)</td></tr>
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<tr class="memdesc:aacdf19047f3059012446eb9563bc9e2e"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Length <br /></td></tr>
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<tr class="separator:aacdf19047f3059012446eb9563bc9e2e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af4dea8f8bf99b393b669470fcd047ace"><td class="memItemLeft" align="right" valign="top"><a id="af4dea8f8bf99b393b669470fcd047ace"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#af4dea8f8bf99b393b669470fcd047ace">REG_DSU_DATA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100200CUL)</td></tr>
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<tr class="memdesc:af4dea8f8bf99b393b669470fcd047ace"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Data <br /></td></tr>
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<tr class="separator:af4dea8f8bf99b393b669470fcd047ace"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a30c2baa6ed6e0977650fa2db6619919f"><td class="memItemLeft" align="right" valign="top"><a id="a30c2baa6ed6e0977650fa2db6619919f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a30c2baa6ed6e0977650fa2db6619919f">REG_DSU_DCC0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41002010UL)</td></tr>
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<tr class="memdesc:a30c2baa6ed6e0977650fa2db6619919f"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Debug Communication Channel 0 <br /></td></tr>
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<tr class="separator:a30c2baa6ed6e0977650fa2db6619919f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a593d74e4d66b106f7deec50cf190a7fd"><td class="memItemLeft" align="right" valign="top"><a id="a593d74e4d66b106f7deec50cf190a7fd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a593d74e4d66b106f7deec50cf190a7fd">REG_DSU_DCC1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41002014UL)</td></tr>
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<tr class="memdesc:a593d74e4d66b106f7deec50cf190a7fd"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Debug Communication Channel 1 <br /></td></tr>
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<tr class="separator:a593d74e4d66b106f7deec50cf190a7fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aed16fccc4ab0e060b2a3dbaddd7b683a"><td class="memItemLeft" align="right" valign="top"><a id="aed16fccc4ab0e060b2a3dbaddd7b683a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#aed16fccc4ab0e060b2a3dbaddd7b683a">REG_DSU_DID</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41002018UL)</td></tr>
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<tr class="memdesc:aed16fccc4ab0e060b2a3dbaddd7b683a"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Device Identification <br /></td></tr>
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<tr class="separator:aed16fccc4ab0e060b2a3dbaddd7b683a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afcf7ada50381d999f257f9c1d533ea68"><td class="memItemLeft" align="right" valign="top"><a id="afcf7ada50381d999f257f9c1d533ea68"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#afcf7ada50381d999f257f9c1d533ea68">REG_DSU_CFG</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100201CUL)</td></tr>
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<tr class="memdesc:afcf7ada50381d999f257f9c1d533ea68"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Configuration <br /></td></tr>
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<tr class="separator:afcf7ada50381d999f257f9c1d533ea68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad8af65a30bc18e5ff87c52e6177300f8"><td class="memItemLeft" align="right" valign="top"><a id="ad8af65a30bc18e5ff87c52e6177300f8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#ad8af65a30bc18e5ff87c52e6177300f8">REG_DSU_ENTRY0</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003000UL)</td></tr>
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<tr class="memdesc:ad8af65a30bc18e5ff87c52e6177300f8"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) CoreSight ROM Table Entry 0 <br /></td></tr>
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<tr class="separator:ad8af65a30bc18e5ff87c52e6177300f8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1b38af2a82d68d8a73c22296df883346"><td class="memItemLeft" align="right" valign="top"><a id="a1b38af2a82d68d8a73c22296df883346"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a1b38af2a82d68d8a73c22296df883346">REG_DSU_ENTRY1</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003004UL)</td></tr>
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<tr class="memdesc:a1b38af2a82d68d8a73c22296df883346"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) CoreSight ROM Table Entry 1 <br /></td></tr>
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<tr class="separator:a1b38af2a82d68d8a73c22296df883346"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7396a90608b11defadbff9f636863a1c"><td class="memItemLeft" align="right" valign="top"><a id="a7396a90608b11defadbff9f636863a1c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a7396a90608b11defadbff9f636863a1c">REG_DSU_END</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003008UL)</td></tr>
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<tr class="memdesc:a7396a90608b11defadbff9f636863a1c"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) CoreSight ROM Table End <br /></td></tr>
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<tr class="separator:a7396a90608b11defadbff9f636863a1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acec2f871a280f435396bcc69e2948d0f"><td class="memItemLeft" align="right" valign="top"><a id="acec2f871a280f435396bcc69e2948d0f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#acec2f871a280f435396bcc69e2948d0f">REG_DSU_MEMTYPE</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FCCUL)</td></tr>
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<tr class="memdesc:acec2f871a280f435396bcc69e2948d0f"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) CoreSight ROM Table Memory Type <br /></td></tr>
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<tr class="separator:acec2f871a280f435396bcc69e2948d0f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a30ceced7787ad791bafa40d2ec6838a4"><td class="memItemLeft" align="right" valign="top"><a id="a30ceced7787ad791bafa40d2ec6838a4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a30ceced7787ad791bafa40d2ec6838a4">REG_DSU_PID4</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FD0UL)</td></tr>
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<tr class="memdesc:a30ceced7787ad791bafa40d2ec6838a4"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Peripheral Identification 4 <br /></td></tr>
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<tr class="separator:a30ceced7787ad791bafa40d2ec6838a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5413add31ded06422b78505d808cf6bf"><td class="memItemLeft" align="right" valign="top"><a id="a5413add31ded06422b78505d808cf6bf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a5413add31ded06422b78505d808cf6bf">REG_DSU_PID5</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FD4UL)</td></tr>
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<tr class="memdesc:a5413add31ded06422b78505d808cf6bf"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Peripheral Identification 5 <br /></td></tr>
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<tr class="separator:a5413add31ded06422b78505d808cf6bf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4e725f47dfbce1a7aa567c1ccabbb94d"><td class="memItemLeft" align="right" valign="top"><a id="a4e725f47dfbce1a7aa567c1ccabbb94d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a4e725f47dfbce1a7aa567c1ccabbb94d">REG_DSU_PID6</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FD8UL)</td></tr>
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<tr class="memdesc:a4e725f47dfbce1a7aa567c1ccabbb94d"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Peripheral Identification 6 <br /></td></tr>
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<tr class="separator:a4e725f47dfbce1a7aa567c1ccabbb94d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a740bf32b8af9f432c2d78a5159d3964f"><td class="memItemLeft" align="right" valign="top"><a id="a740bf32b8af9f432c2d78a5159d3964f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a740bf32b8af9f432c2d78a5159d3964f">REG_DSU_PID7</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FDCUL)</td></tr>
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<tr class="memdesc:a740bf32b8af9f432c2d78a5159d3964f"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Peripheral Identification 7 <br /></td></tr>
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<tr class="separator:a740bf32b8af9f432c2d78a5159d3964f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad5aaa625886c89be3c72fba3823eff34"><td class="memItemLeft" align="right" valign="top"><a id="ad5aaa625886c89be3c72fba3823eff34"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#ad5aaa625886c89be3c72fba3823eff34">REG_DSU_PID0</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FE0UL)</td></tr>
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<tr class="memdesc:ad5aaa625886c89be3c72fba3823eff34"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Peripheral Identification 0 <br /></td></tr>
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<tr class="separator:ad5aaa625886c89be3c72fba3823eff34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a173e7bcfc7dfaac976882f1bc4bdc735"><td class="memItemLeft" align="right" valign="top"><a id="a173e7bcfc7dfaac976882f1bc4bdc735"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a173e7bcfc7dfaac976882f1bc4bdc735">REG_DSU_PID1</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FE4UL)</td></tr>
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<tr class="memdesc:a173e7bcfc7dfaac976882f1bc4bdc735"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Peripheral Identification 1 <br /></td></tr>
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<tr class="separator:a173e7bcfc7dfaac976882f1bc4bdc735"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10216c226fd45ee30ca466f25867395a"><td class="memItemLeft" align="right" valign="top"><a id="a10216c226fd45ee30ca466f25867395a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a10216c226fd45ee30ca466f25867395a">REG_DSU_PID2</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FE8UL)</td></tr>
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<tr class="memdesc:a10216c226fd45ee30ca466f25867395a"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Peripheral Identification 2 <br /></td></tr>
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<tr class="separator:a10216c226fd45ee30ca466f25867395a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a463fa28d9787bbaeb82afd253e1d8acf"><td class="memItemLeft" align="right" valign="top"><a id="a463fa28d9787bbaeb82afd253e1d8acf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a463fa28d9787bbaeb82afd253e1d8acf">REG_DSU_PID3</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FECUL)</td></tr>
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<tr class="memdesc:a463fa28d9787bbaeb82afd253e1d8acf"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Peripheral Identification 3 <br /></td></tr>
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<tr class="separator:a463fa28d9787bbaeb82afd253e1d8acf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0f9e40fce594549bbf87b0fb45e8e8d3"><td class="memItemLeft" align="right" valign="top"><a id="a0f9e40fce594549bbf87b0fb45e8e8d3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#a0f9e40fce594549bbf87b0fb45e8e8d3">REG_DSU_CID0</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FF0UL)</td></tr>
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<tr class="memdesc:a0f9e40fce594549bbf87b0fb45e8e8d3"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Component Identification 0 <br /></td></tr>
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<tr class="separator:a0f9e40fce594549bbf87b0fb45e8e8d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab009a9f2376853164a097c90af1dcda8"><td class="memItemLeft" align="right" valign="top"><a id="ab009a9f2376853164a097c90af1dcda8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#ab009a9f2376853164a097c90af1dcda8">REG_DSU_CID1</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FF4UL)</td></tr>
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<tr class="memdesc:ab009a9f2376853164a097c90af1dcda8"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Component Identification 1 <br /></td></tr>
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<tr class="separator:ab009a9f2376853164a097c90af1dcda8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac0bbcd6daf6851e1cd49f001d7478997"><td class="memItemLeft" align="right" valign="top"><a id="ac0bbcd6daf6851e1cd49f001d7478997"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#ac0bbcd6daf6851e1cd49f001d7478997">REG_DSU_CID2</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FF8UL)</td></tr>
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<tr class="memdesc:ac0bbcd6daf6851e1cd49f001d7478997"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Component Identification 2 <br /></td></tr>
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<tr class="separator:ac0bbcd6daf6851e1cd49f001d7478997"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac6c8fbe20ec18ace2351c51eb28266b4"><td class="memItemLeft" align="right" valign="top"><a id="ac6c8fbe20ec18ace2351c51eb28266b4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dsu_8h.html#ac6c8fbe20ec18ace2351c51eb28266b4">REG_DSU_CID3</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41003FFCUL)</td></tr>
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<tr class="memdesc:ac6c8fbe20ec18ace2351c51eb28266b4"><td class="mdescLeft"> </td><td class="mdescRight">(DSU) Component Identification 3 <br /></td></tr>
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<tr class="separator:ac6c8fbe20ec18ace2351c51eb28266b4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acb0a96ed90b2631a32707ed4b0a7dafb"><td class="memItemLeft" align="right" valign="top"><a id="acb0a96ed90b2631a32707ed4b0a7dafb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CLK_AHB_ID</b>   4</td></tr>
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<tr class="separator:acb0a96ed90b2631a32707ed4b0a7dafb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac11eb576e3afb63ccd46970d25f7444a"><td class="memItemLeft" align="right" valign="top"><a id="ac11eb576e3afb63ccd46970d25f7444a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DMAC_ID_DCC0</b>   2</td></tr>
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<tr class="separator:ac11eb576e3afb63ccd46970d25f7444a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0ff9afbf3d7f07b8e0c3d2e18f0b0e0c"><td class="memItemLeft" align="right" valign="top"><a id="a0ff9afbf3d7f07b8e0c3d2e18f0b0e0c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DMAC_ID_DCC1</b>   3</td></tr>
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<tr class="separator:a0ff9afbf3d7f07b8e0c3d2e18f0b0e0c"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for DSU. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="instance_2dsu_8h_source.html">dsu.h</a>.</p>
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