You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
1222 lines
199 KiB
HTML
1222 lines
199 KiB
HTML
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "https://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
|
<html xmlns="http://www.w3.org/1999/xhtml">
|
|
<head>
|
|
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
|
|
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
|
|
<meta name="generator" content="Doxygen 1.8.20"/>
|
|
<meta name="viewport" content="width=device-width, initial-scale=1"/>
|
|
<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/dmac.h File Reference</title>
|
|
<link href="tabs.css" rel="stylesheet" type="text/css"/>
|
|
<script type="text/javascript" src="jquery.js"></script>
|
|
<script type="text/javascript" src="dynsections.js"></script>
|
|
<link href="search/search.css" rel="stylesheet" type="text/css"/>
|
|
<script type="text/javascript" src="search/searchdata.js"></script>
|
|
<script type="text/javascript" src="search/search.js"></script>
|
|
<link href="doxygen.css" rel="stylesheet" type="text/css" />
|
|
</head>
|
|
<body>
|
|
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
|
|
<div id="titlearea">
|
|
<table cellspacing="0" cellpadding="0">
|
|
<tbody>
|
|
<tr style="height: 56px;">
|
|
<td id="projectalign" style="padding-left: 0.5em;">
|
|
<div id="projectname">SAME54P20A Test Project
|
|
</div>
|
|
</td>
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
</div>
|
|
<!-- end header part -->
|
|
<!-- Generated by Doxygen 1.8.20 -->
|
|
<script type="text/javascript">
|
|
/* @license magnet:?xt=urn:btih:cf05388f2679ee054f2beb29a391d25f4e673ac3&dn=gpl-2.0.txt GPL-v2 */
|
|
var searchBox = new SearchBox("searchBox", "search",false,'Search');
|
|
/* @license-end */
|
|
</script>
|
|
<script type="text/javascript" src="menudata.js"></script>
|
|
<script type="text/javascript" src="menu.js"></script>
|
|
<script type="text/javascript">
|
|
/* @license magnet:?xt=urn:btih:cf05388f2679ee054f2beb29a391d25f4e673ac3&dn=gpl-2.0.txt GPL-v2 */
|
|
$(function() {
|
|
initMenu('',true,false,'search.php','Search');
|
|
$(document).ready(function() { init_search(); });
|
|
});
|
|
/* @license-end */</script>
|
|
<div id="main-nav"></div>
|
|
<!-- window showing the filter options -->
|
|
<div id="MSearchSelectWindow"
|
|
onmouseover="return searchBox.OnSearchSelectShow()"
|
|
onmouseout="return searchBox.OnSearchSelectHide()"
|
|
onkeydown="return searchBox.OnSearchSelectKey(event)">
|
|
</div>
|
|
|
|
<!-- iframe showing the search results (closed by default) -->
|
|
<div id="MSearchResultsWindow">
|
|
<iframe src="javascript:void(0)" frameborder="0"
|
|
name="MSearchResults" id="MSearchResults">
|
|
</iframe>
|
|
</div>
|
|
|
|
<div id="nav-path" class="navpath">
|
|
<ul>
|
|
<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
|
|
</div>
|
|
</div><!-- top -->
|
|
<div class="header">
|
|
<div class="summary">
|
|
<a href="#define-members">Macros</a> </div>
|
|
<div class="headertitle">
|
|
<div class="title">dmac.h File Reference</div> </div>
|
|
</div><!--header-->
|
|
<div class="contents">
|
|
|
|
<p>Instance description for DMAC.
|
|
<a href="#details">More...</a></p>
|
|
|
|
<p><a href="instance_2dmac_8h_source.html">Go to the source code of this file.</a></p>
|
|
<table class="memberdecls">
|
|
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
|
|
Macros</h2></td></tr>
|
|
<tr class="memitem:a719f34193672dd9a2c9fffbb6dfdea9d"><td class="memItemLeft" align="right" valign="top"><a id="a719f34193672dd9a2c9fffbb6dfdea9d"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a719f34193672dd9a2c9fffbb6dfdea9d">REG_DMAC_CTRL</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4100A000UL)</td></tr>
|
|
<tr class="memdesc:a719f34193672dd9a2c9fffbb6dfdea9d"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Control <br /></td></tr>
|
|
<tr class="separator:a719f34193672dd9a2c9fffbb6dfdea9d"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1372d49e96da14318d9a00cf60163994"><td class="memItemLeft" align="right" valign="top"><a id="a1372d49e96da14318d9a00cf60163994"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1372d49e96da14318d9a00cf60163994">REG_DMAC_CRCCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4100A002UL)</td></tr>
|
|
<tr class="memdesc:a1372d49e96da14318d9a00cf60163994"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) CRC Control <br /></td></tr>
|
|
<tr class="separator:a1372d49e96da14318d9a00cf60163994"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aae1a17c500e6e778ef64f239379306f4"><td class="memItemLeft" align="right" valign="top"><a id="aae1a17c500e6e778ef64f239379306f4"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aae1a17c500e6e778ef64f239379306f4">REG_DMAC_CRCDATAIN</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A004UL)</td></tr>
|
|
<tr class="memdesc:aae1a17c500e6e778ef64f239379306f4"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) CRC Data Input <br /></td></tr>
|
|
<tr class="separator:aae1a17c500e6e778ef64f239379306f4"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af683566d356110dbb8f3a3bb81dd0570"><td class="memItemLeft" align="right" valign="top"><a id="af683566d356110dbb8f3a3bb81dd0570"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af683566d356110dbb8f3a3bb81dd0570">REG_DMAC_CRCCHKSUM</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A008UL)</td></tr>
|
|
<tr class="memdesc:af683566d356110dbb8f3a3bb81dd0570"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) CRC Checksum <br /></td></tr>
|
|
<tr class="separator:af683566d356110dbb8f3a3bb81dd0570"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a8e6e408ad573fa1dff504ea3f1a7080c"><td class="memItemLeft" align="right" valign="top"><a id="a8e6e408ad573fa1dff504ea3f1a7080c"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a8e6e408ad573fa1dff504ea3f1a7080c">REG_DMAC_CRCSTATUS</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A00CUL)</td></tr>
|
|
<tr class="memdesc:a8e6e408ad573fa1dff504ea3f1a7080c"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) CRC Status <br /></td></tr>
|
|
<tr class="separator:a8e6e408ad573fa1dff504ea3f1a7080c"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a762108bddf5367757aefe080c7fe2643"><td class="memItemLeft" align="right" valign="top"><a id="a762108bddf5367757aefe080c7fe2643"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a762108bddf5367757aefe080c7fe2643">REG_DMAC_DBGCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A00DUL)</td></tr>
|
|
<tr class="memdesc:a762108bddf5367757aefe080c7fe2643"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Debug Control <br /></td></tr>
|
|
<tr class="separator:a762108bddf5367757aefe080c7fe2643"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a929785acdf7fa48187b09600c0cf7d3b"><td class="memItemLeft" align="right" valign="top"><a id="a929785acdf7fa48187b09600c0cf7d3b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a929785acdf7fa48187b09600c0cf7d3b">REG_DMAC_SWTRIGCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A010UL)</td></tr>
|
|
<tr class="memdesc:a929785acdf7fa48187b09600c0cf7d3b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Software Trigger Control <br /></td></tr>
|
|
<tr class="separator:a929785acdf7fa48187b09600c0cf7d3b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ab3cfe5d78ab9654adeaf801ca0761c2d"><td class="memItemLeft" align="right" valign="top"><a id="ab3cfe5d78ab9654adeaf801ca0761c2d"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ab3cfe5d78ab9654adeaf801ca0761c2d">REG_DMAC_PRICTRL0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A014UL)</td></tr>
|
|
<tr class="memdesc:ab3cfe5d78ab9654adeaf801ca0761c2d"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Priority Control 0 <br /></td></tr>
|
|
<tr class="separator:ab3cfe5d78ab9654adeaf801ca0761c2d"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:affe02fc253076a5d922bd3ae69f3b80b"><td class="memItemLeft" align="right" valign="top"><a id="affe02fc253076a5d922bd3ae69f3b80b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#affe02fc253076a5d922bd3ae69f3b80b">REG_DMAC_INTPEND</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4100A020UL)</td></tr>
|
|
<tr class="memdesc:affe02fc253076a5d922bd3ae69f3b80b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Interrupt Pending <br /></td></tr>
|
|
<tr class="separator:affe02fc253076a5d922bd3ae69f3b80b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1fcddb6e682b73ea81433b5e05bac7b6"><td class="memItemLeft" align="right" valign="top"><a id="a1fcddb6e682b73ea81433b5e05bac7b6"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1fcddb6e682b73ea81433b5e05bac7b6">REG_DMAC_INTSTATUS</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4100A024UL)</td></tr>
|
|
<tr class="memdesc:a1fcddb6e682b73ea81433b5e05bac7b6"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Interrupt Status <br /></td></tr>
|
|
<tr class="separator:a1fcddb6e682b73ea81433b5e05bac7b6"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a8e0fafca25adbe8d643f2a6f338dc48e"><td class="memItemLeft" align="right" valign="top"><a id="a8e0fafca25adbe8d643f2a6f338dc48e"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a8e0fafca25adbe8d643f2a6f338dc48e">REG_DMAC_BUSYCH</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4100A028UL)</td></tr>
|
|
<tr class="memdesc:a8e0fafca25adbe8d643f2a6f338dc48e"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Busy Channels <br /></td></tr>
|
|
<tr class="separator:a8e0fafca25adbe8d643f2a6f338dc48e"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a0edba9cf9c70e0b9f84243531bd7208a"><td class="memItemLeft" align="right" valign="top"><a id="a0edba9cf9c70e0b9f84243531bd7208a"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a0edba9cf9c70e0b9f84243531bd7208a">REG_DMAC_PENDCH</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4100A02CUL)</td></tr>
|
|
<tr class="memdesc:a0edba9cf9c70e0b9f84243531bd7208a"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Pending Channels <br /></td></tr>
|
|
<tr class="separator:a0edba9cf9c70e0b9f84243531bd7208a"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad1ed98c7dc61675001e9e5a14f83c8e7"><td class="memItemLeft" align="right" valign="top"><a id="ad1ed98c7dc61675001e9e5a14f83c8e7"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad1ed98c7dc61675001e9e5a14f83c8e7">REG_DMAC_ACTIVE</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4100A030UL)</td></tr>
|
|
<tr class="memdesc:ad1ed98c7dc61675001e9e5a14f83c8e7"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Active Channel and Levels <br /></td></tr>
|
|
<tr class="separator:ad1ed98c7dc61675001e9e5a14f83c8e7"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ab83eb3baa71007852b8aac15c37dbaa1"><td class="memItemLeft" align="right" valign="top"><a id="ab83eb3baa71007852b8aac15c37dbaa1"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ab83eb3baa71007852b8aac15c37dbaa1">REG_DMAC_BASEADDR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A034UL)</td></tr>
|
|
<tr class="memdesc:ab83eb3baa71007852b8aac15c37dbaa1"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Descriptor Memory Section Base Address <br /></td></tr>
|
|
<tr class="separator:ab83eb3baa71007852b8aac15c37dbaa1"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3573c7537ecdb9918920480d637ea25f"><td class="memItemLeft" align="right" valign="top"><a id="a3573c7537ecdb9918920480d637ea25f"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3573c7537ecdb9918920480d637ea25f">REG_DMAC_WRBADDR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A038UL)</td></tr>
|
|
<tr class="memdesc:a3573c7537ecdb9918920480d637ea25f"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Write-Back Memory Section Base Address <br /></td></tr>
|
|
<tr class="separator:a3573c7537ecdb9918920480d637ea25f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a880b7844a28f522cfec6be2df09213c3"><td class="memItemLeft" align="right" valign="top"><a id="a880b7844a28f522cfec6be2df09213c3"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a880b7844a28f522cfec6be2df09213c3">REG_DMAC_CHCTRLA0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A040UL)</td></tr>
|
|
<tr class="memdesc:a880b7844a28f522cfec6be2df09213c3"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 0 Control A <br /></td></tr>
|
|
<tr class="separator:a880b7844a28f522cfec6be2df09213c3"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a10524fd3a00da0ba124c362b93da7476"><td class="memItemLeft" align="right" valign="top"><a id="a10524fd3a00da0ba124c362b93da7476"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a10524fd3a00da0ba124c362b93da7476">REG_DMAC_CHCTRLB0</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A044UL)</td></tr>
|
|
<tr class="memdesc:a10524fd3a00da0ba124c362b93da7476"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 0 Control B <br /></td></tr>
|
|
<tr class="separator:a10524fd3a00da0ba124c362b93da7476"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a9cdb5f2f764403a0daa02825128f6d33"><td class="memItemLeft" align="right" valign="top"><a id="a9cdb5f2f764403a0daa02825128f6d33"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a9cdb5f2f764403a0daa02825128f6d33">REG_DMAC_CHPRILVL0</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A045UL)</td></tr>
|
|
<tr class="memdesc:a9cdb5f2f764403a0daa02825128f6d33"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 0 Priority Level <br /></td></tr>
|
|
<tr class="separator:a9cdb5f2f764403a0daa02825128f6d33"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:abf63f6ffe6d6d9d22504d037574e2226"><td class="memItemLeft" align="right" valign="top"><a id="abf63f6ffe6d6d9d22504d037574e2226"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#abf63f6ffe6d6d9d22504d037574e2226">REG_DMAC_CHEVCTRL0</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A046UL)</td></tr>
|
|
<tr class="memdesc:abf63f6ffe6d6d9d22504d037574e2226"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 0 Event Control <br /></td></tr>
|
|
<tr class="separator:abf63f6ffe6d6d9d22504d037574e2226"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1600ef63e967aa2edf0b322df2d7391f"><td class="memItemLeft" align="right" valign="top"><a id="a1600ef63e967aa2edf0b322df2d7391f"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1600ef63e967aa2edf0b322df2d7391f">REG_DMAC_CHINTENCLR0</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A04CUL)</td></tr>
|
|
<tr class="memdesc:a1600ef63e967aa2edf0b322df2d7391f"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 0 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a1600ef63e967aa2edf0b322df2d7391f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:acbd84416ece057bb7500ac6ae7991588"><td class="memItemLeft" align="right" valign="top"><a id="acbd84416ece057bb7500ac6ae7991588"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#acbd84416ece057bb7500ac6ae7991588">REG_DMAC_CHINTENSET0</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A04DUL)</td></tr>
|
|
<tr class="memdesc:acbd84416ece057bb7500ac6ae7991588"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 0 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:acbd84416ece057bb7500ac6ae7991588"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a311acd30a07ecd1be3b65264e090102c"><td class="memItemLeft" align="right" valign="top"><a id="a311acd30a07ecd1be3b65264e090102c"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a311acd30a07ecd1be3b65264e090102c">REG_DMAC_CHINTFLAG0</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A04EUL)</td></tr>
|
|
<tr class="memdesc:a311acd30a07ecd1be3b65264e090102c"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 0 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a311acd30a07ecd1be3b65264e090102c"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad5c8b9166f28acbd7a8ad7d21a0caf55"><td class="memItemLeft" align="right" valign="top"><a id="ad5c8b9166f28acbd7a8ad7d21a0caf55"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad5c8b9166f28acbd7a8ad7d21a0caf55">REG_DMAC_CHSTATUS0</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A04FUL)</td></tr>
|
|
<tr class="memdesc:ad5c8b9166f28acbd7a8ad7d21a0caf55"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 0 Status <br /></td></tr>
|
|
<tr class="separator:ad5c8b9166f28acbd7a8ad7d21a0caf55"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a57c5c9bda8d63bc5c4859dde6c11b7df"><td class="memItemLeft" align="right" valign="top"><a id="a57c5c9bda8d63bc5c4859dde6c11b7df"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a57c5c9bda8d63bc5c4859dde6c11b7df">REG_DMAC_CHCTRLA1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A050UL)</td></tr>
|
|
<tr class="memdesc:a57c5c9bda8d63bc5c4859dde6c11b7df"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 1 Control A <br /></td></tr>
|
|
<tr class="separator:a57c5c9bda8d63bc5c4859dde6c11b7df"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ae01522377d95da09bb8632e668cd1151"><td class="memItemLeft" align="right" valign="top"><a id="ae01522377d95da09bb8632e668cd1151"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ae01522377d95da09bb8632e668cd1151">REG_DMAC_CHCTRLB1</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A054UL)</td></tr>
|
|
<tr class="memdesc:ae01522377d95da09bb8632e668cd1151"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 1 Control B <br /></td></tr>
|
|
<tr class="separator:ae01522377d95da09bb8632e668cd1151"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a556f49773c2f46cbb61ad8ca03fbb8a7"><td class="memItemLeft" align="right" valign="top"><a id="a556f49773c2f46cbb61ad8ca03fbb8a7"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a556f49773c2f46cbb61ad8ca03fbb8a7">REG_DMAC_CHPRILVL1</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A055UL)</td></tr>
|
|
<tr class="memdesc:a556f49773c2f46cbb61ad8ca03fbb8a7"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 1 Priority Level <br /></td></tr>
|
|
<tr class="separator:a556f49773c2f46cbb61ad8ca03fbb8a7"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a618d6892ad555b234533bdbea2d8967a"><td class="memItemLeft" align="right" valign="top"><a id="a618d6892ad555b234533bdbea2d8967a"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a618d6892ad555b234533bdbea2d8967a">REG_DMAC_CHEVCTRL1</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A056UL)</td></tr>
|
|
<tr class="memdesc:a618d6892ad555b234533bdbea2d8967a"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 1 Event Control <br /></td></tr>
|
|
<tr class="separator:a618d6892ad555b234533bdbea2d8967a"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a6180e6e02c8b6afcdfcee35e646f095a"><td class="memItemLeft" align="right" valign="top"><a id="a6180e6e02c8b6afcdfcee35e646f095a"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a6180e6e02c8b6afcdfcee35e646f095a">REG_DMAC_CHINTENCLR1</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A05CUL)</td></tr>
|
|
<tr class="memdesc:a6180e6e02c8b6afcdfcee35e646f095a"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 1 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a6180e6e02c8b6afcdfcee35e646f095a"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a002b7ae8bb3fbd280dbe51c78fecdafc"><td class="memItemLeft" align="right" valign="top"><a id="a002b7ae8bb3fbd280dbe51c78fecdafc"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a002b7ae8bb3fbd280dbe51c78fecdafc">REG_DMAC_CHINTENSET1</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A05DUL)</td></tr>
|
|
<tr class="memdesc:a002b7ae8bb3fbd280dbe51c78fecdafc"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 1 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a002b7ae8bb3fbd280dbe51c78fecdafc"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ab23f513054d33d02bed93e4f57daacc6"><td class="memItemLeft" align="right" valign="top"><a id="ab23f513054d33d02bed93e4f57daacc6"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ab23f513054d33d02bed93e4f57daacc6">REG_DMAC_CHINTFLAG1</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A05EUL)</td></tr>
|
|
<tr class="memdesc:ab23f513054d33d02bed93e4f57daacc6"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 1 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:ab23f513054d33d02bed93e4f57daacc6"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ae53051d5dbe5d1548c61f38cbfca3ac4"><td class="memItemLeft" align="right" valign="top"><a id="ae53051d5dbe5d1548c61f38cbfca3ac4"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ae53051d5dbe5d1548c61f38cbfca3ac4">REG_DMAC_CHSTATUS1</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A05FUL)</td></tr>
|
|
<tr class="memdesc:ae53051d5dbe5d1548c61f38cbfca3ac4"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 1 Status <br /></td></tr>
|
|
<tr class="separator:ae53051d5dbe5d1548c61f38cbfca3ac4"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a088334e84569e8d10db013efca287034"><td class="memItemLeft" align="right" valign="top"><a id="a088334e84569e8d10db013efca287034"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a088334e84569e8d10db013efca287034">REG_DMAC_CHCTRLA2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A060UL)</td></tr>
|
|
<tr class="memdesc:a088334e84569e8d10db013efca287034"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 2 Control A <br /></td></tr>
|
|
<tr class="separator:a088334e84569e8d10db013efca287034"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa69a09f1ea8e887fa36a1e366f82c970"><td class="memItemLeft" align="right" valign="top"><a id="aa69a09f1ea8e887fa36a1e366f82c970"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aa69a09f1ea8e887fa36a1e366f82c970">REG_DMAC_CHCTRLB2</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A064UL)</td></tr>
|
|
<tr class="memdesc:aa69a09f1ea8e887fa36a1e366f82c970"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 2 Control B <br /></td></tr>
|
|
<tr class="separator:aa69a09f1ea8e887fa36a1e366f82c970"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ab08af01b472179a32197567c1ff47981"><td class="memItemLeft" align="right" valign="top"><a id="ab08af01b472179a32197567c1ff47981"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ab08af01b472179a32197567c1ff47981">REG_DMAC_CHPRILVL2</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A065UL)</td></tr>
|
|
<tr class="memdesc:ab08af01b472179a32197567c1ff47981"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 2 Priority Level <br /></td></tr>
|
|
<tr class="separator:ab08af01b472179a32197567c1ff47981"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a43f0c292b14a0fe6f2c33015d9a7eb48"><td class="memItemLeft" align="right" valign="top"><a id="a43f0c292b14a0fe6f2c33015d9a7eb48"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a43f0c292b14a0fe6f2c33015d9a7eb48">REG_DMAC_CHEVCTRL2</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A066UL)</td></tr>
|
|
<tr class="memdesc:a43f0c292b14a0fe6f2c33015d9a7eb48"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 2 Event Control <br /></td></tr>
|
|
<tr class="separator:a43f0c292b14a0fe6f2c33015d9a7eb48"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a754bfc20a71f0607e2e4d516e1c2136e"><td class="memItemLeft" align="right" valign="top"><a id="a754bfc20a71f0607e2e4d516e1c2136e"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a754bfc20a71f0607e2e4d516e1c2136e">REG_DMAC_CHINTENCLR2</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A06CUL)</td></tr>
|
|
<tr class="memdesc:a754bfc20a71f0607e2e4d516e1c2136e"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 2 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a754bfc20a71f0607e2e4d516e1c2136e"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a71e4ecd5f20606cd37202fe152811402"><td class="memItemLeft" align="right" valign="top"><a id="a71e4ecd5f20606cd37202fe152811402"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a71e4ecd5f20606cd37202fe152811402">REG_DMAC_CHINTENSET2</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A06DUL)</td></tr>
|
|
<tr class="memdesc:a71e4ecd5f20606cd37202fe152811402"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 2 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a71e4ecd5f20606cd37202fe152811402"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a6d9e8f77bd7a6cd914f663e47b4cdd3b"><td class="memItemLeft" align="right" valign="top"><a id="a6d9e8f77bd7a6cd914f663e47b4cdd3b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a6d9e8f77bd7a6cd914f663e47b4cdd3b">REG_DMAC_CHINTFLAG2</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A06EUL)</td></tr>
|
|
<tr class="memdesc:a6d9e8f77bd7a6cd914f663e47b4cdd3b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 2 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a6d9e8f77bd7a6cd914f663e47b4cdd3b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad1addd60a3af0c1b7539120885968ebb"><td class="memItemLeft" align="right" valign="top"><a id="ad1addd60a3af0c1b7539120885968ebb"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad1addd60a3af0c1b7539120885968ebb">REG_DMAC_CHSTATUS2</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A06FUL)</td></tr>
|
|
<tr class="memdesc:ad1addd60a3af0c1b7539120885968ebb"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 2 Status <br /></td></tr>
|
|
<tr class="separator:ad1addd60a3af0c1b7539120885968ebb"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af389afcb635a3731c4ea2520aba05a29"><td class="memItemLeft" align="right" valign="top"><a id="af389afcb635a3731c4ea2520aba05a29"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af389afcb635a3731c4ea2520aba05a29">REG_DMAC_CHCTRLA3</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A070UL)</td></tr>
|
|
<tr class="memdesc:af389afcb635a3731c4ea2520aba05a29"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 3 Control A <br /></td></tr>
|
|
<tr class="separator:af389afcb635a3731c4ea2520aba05a29"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a40246f2e07d0355ecf064f94525d942e"><td class="memItemLeft" align="right" valign="top"><a id="a40246f2e07d0355ecf064f94525d942e"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a40246f2e07d0355ecf064f94525d942e">REG_DMAC_CHCTRLB3</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A074UL)</td></tr>
|
|
<tr class="memdesc:a40246f2e07d0355ecf064f94525d942e"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 3 Control B <br /></td></tr>
|
|
<tr class="separator:a40246f2e07d0355ecf064f94525d942e"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa0fa4b6fc090762fb518bd047778fe21"><td class="memItemLeft" align="right" valign="top"><a id="aa0fa4b6fc090762fb518bd047778fe21"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aa0fa4b6fc090762fb518bd047778fe21">REG_DMAC_CHPRILVL3</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A075UL)</td></tr>
|
|
<tr class="memdesc:aa0fa4b6fc090762fb518bd047778fe21"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 3 Priority Level <br /></td></tr>
|
|
<tr class="separator:aa0fa4b6fc090762fb518bd047778fe21"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1be1b308a5c34c61c34a0e3d4f12e620"><td class="memItemLeft" align="right" valign="top"><a id="a1be1b308a5c34c61c34a0e3d4f12e620"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1be1b308a5c34c61c34a0e3d4f12e620">REG_DMAC_CHEVCTRL3</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A076UL)</td></tr>
|
|
<tr class="memdesc:a1be1b308a5c34c61c34a0e3d4f12e620"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 3 Event Control <br /></td></tr>
|
|
<tr class="separator:a1be1b308a5c34c61c34a0e3d4f12e620"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a9b139073c64c297e11b8694c604b994c"><td class="memItemLeft" align="right" valign="top"><a id="a9b139073c64c297e11b8694c604b994c"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a9b139073c64c297e11b8694c604b994c">REG_DMAC_CHINTENCLR3</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A07CUL)</td></tr>
|
|
<tr class="memdesc:a9b139073c64c297e11b8694c604b994c"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 3 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a9b139073c64c297e11b8694c604b994c"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a7ff385057d58da18df73430438656255"><td class="memItemLeft" align="right" valign="top"><a id="a7ff385057d58da18df73430438656255"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a7ff385057d58da18df73430438656255">REG_DMAC_CHINTENSET3</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A07DUL)</td></tr>
|
|
<tr class="memdesc:a7ff385057d58da18df73430438656255"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 3 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a7ff385057d58da18df73430438656255"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a5c16cc04fc4f4fe9072b6da7feb74972"><td class="memItemLeft" align="right" valign="top"><a id="a5c16cc04fc4f4fe9072b6da7feb74972"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a5c16cc04fc4f4fe9072b6da7feb74972">REG_DMAC_CHINTFLAG3</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A07EUL)</td></tr>
|
|
<tr class="memdesc:a5c16cc04fc4f4fe9072b6da7feb74972"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 3 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a5c16cc04fc4f4fe9072b6da7feb74972"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af0c319f097661f26de845b1b20a70e2a"><td class="memItemLeft" align="right" valign="top"><a id="af0c319f097661f26de845b1b20a70e2a"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af0c319f097661f26de845b1b20a70e2a">REG_DMAC_CHSTATUS3</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A07FUL)</td></tr>
|
|
<tr class="memdesc:af0c319f097661f26de845b1b20a70e2a"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 3 Status <br /></td></tr>
|
|
<tr class="separator:af0c319f097661f26de845b1b20a70e2a"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3ad25032f8b5cbccfff8fc15fca85a65"><td class="memItemLeft" align="right" valign="top"><a id="a3ad25032f8b5cbccfff8fc15fca85a65"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3ad25032f8b5cbccfff8fc15fca85a65">REG_DMAC_CHCTRLA4</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A080UL)</td></tr>
|
|
<tr class="memdesc:a3ad25032f8b5cbccfff8fc15fca85a65"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 4 Control A <br /></td></tr>
|
|
<tr class="separator:a3ad25032f8b5cbccfff8fc15fca85a65"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3e649c82a4427b68099955806c08668f"><td class="memItemLeft" align="right" valign="top"><a id="a3e649c82a4427b68099955806c08668f"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3e649c82a4427b68099955806c08668f">REG_DMAC_CHCTRLB4</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A084UL)</td></tr>
|
|
<tr class="memdesc:a3e649c82a4427b68099955806c08668f"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 4 Control B <br /></td></tr>
|
|
<tr class="separator:a3e649c82a4427b68099955806c08668f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a4d71f4280994ca31f1372b6d8f7876ac"><td class="memItemLeft" align="right" valign="top"><a id="a4d71f4280994ca31f1372b6d8f7876ac"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a4d71f4280994ca31f1372b6d8f7876ac">REG_DMAC_CHPRILVL4</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A085UL)</td></tr>
|
|
<tr class="memdesc:a4d71f4280994ca31f1372b6d8f7876ac"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 4 Priority Level <br /></td></tr>
|
|
<tr class="separator:a4d71f4280994ca31f1372b6d8f7876ac"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:acf3a22eae3c3c83e4945b7abb432abc9"><td class="memItemLeft" align="right" valign="top"><a id="acf3a22eae3c3c83e4945b7abb432abc9"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#acf3a22eae3c3c83e4945b7abb432abc9">REG_DMAC_CHEVCTRL4</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A086UL)</td></tr>
|
|
<tr class="memdesc:acf3a22eae3c3c83e4945b7abb432abc9"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 4 Event Control <br /></td></tr>
|
|
<tr class="separator:acf3a22eae3c3c83e4945b7abb432abc9"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a553ab846e32d3289f2e99cccaf0f4343"><td class="memItemLeft" align="right" valign="top"><a id="a553ab846e32d3289f2e99cccaf0f4343"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a553ab846e32d3289f2e99cccaf0f4343">REG_DMAC_CHINTENCLR4</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A08CUL)</td></tr>
|
|
<tr class="memdesc:a553ab846e32d3289f2e99cccaf0f4343"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 4 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a553ab846e32d3289f2e99cccaf0f4343"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad5760ff6dfc1d6fd5db5d3fa6ec1a906"><td class="memItemLeft" align="right" valign="top"><a id="ad5760ff6dfc1d6fd5db5d3fa6ec1a906"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad5760ff6dfc1d6fd5db5d3fa6ec1a906">REG_DMAC_CHINTENSET4</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A08DUL)</td></tr>
|
|
<tr class="memdesc:ad5760ff6dfc1d6fd5db5d3fa6ec1a906"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 4 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:ad5760ff6dfc1d6fd5db5d3fa6ec1a906"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad2ea871837847497a9f4bcb83cc86e58"><td class="memItemLeft" align="right" valign="top"><a id="ad2ea871837847497a9f4bcb83cc86e58"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad2ea871837847497a9f4bcb83cc86e58">REG_DMAC_CHINTFLAG4</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A08EUL)</td></tr>
|
|
<tr class="memdesc:ad2ea871837847497a9f4bcb83cc86e58"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 4 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:ad2ea871837847497a9f4bcb83cc86e58"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a9b212791da5d967a526cdc2c8dda3418"><td class="memItemLeft" align="right" valign="top"><a id="a9b212791da5d967a526cdc2c8dda3418"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a9b212791da5d967a526cdc2c8dda3418">REG_DMAC_CHSTATUS4</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A08FUL)</td></tr>
|
|
<tr class="memdesc:a9b212791da5d967a526cdc2c8dda3418"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 4 Status <br /></td></tr>
|
|
<tr class="separator:a9b212791da5d967a526cdc2c8dda3418"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a719457a874d3f8971b3f16869cc99741"><td class="memItemLeft" align="right" valign="top"><a id="a719457a874d3f8971b3f16869cc99741"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a719457a874d3f8971b3f16869cc99741">REG_DMAC_CHCTRLA5</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A090UL)</td></tr>
|
|
<tr class="memdesc:a719457a874d3f8971b3f16869cc99741"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 5 Control A <br /></td></tr>
|
|
<tr class="separator:a719457a874d3f8971b3f16869cc99741"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a91d71977e3b2ac83c13251996cf50ab1"><td class="memItemLeft" align="right" valign="top"><a id="a91d71977e3b2ac83c13251996cf50ab1"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a91d71977e3b2ac83c13251996cf50ab1">REG_DMAC_CHCTRLB5</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A094UL)</td></tr>
|
|
<tr class="memdesc:a91d71977e3b2ac83c13251996cf50ab1"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 5 Control B <br /></td></tr>
|
|
<tr class="separator:a91d71977e3b2ac83c13251996cf50ab1"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a8d2a1d6d334261303713fb0f5bb52d6b"><td class="memItemLeft" align="right" valign="top"><a id="a8d2a1d6d334261303713fb0f5bb52d6b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a8d2a1d6d334261303713fb0f5bb52d6b">REG_DMAC_CHPRILVL5</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A095UL)</td></tr>
|
|
<tr class="memdesc:a8d2a1d6d334261303713fb0f5bb52d6b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 5 Priority Level <br /></td></tr>
|
|
<tr class="separator:a8d2a1d6d334261303713fb0f5bb52d6b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa03c6226812bac16a7f15613a7ee4354"><td class="memItemLeft" align="right" valign="top"><a id="aa03c6226812bac16a7f15613a7ee4354"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aa03c6226812bac16a7f15613a7ee4354">REG_DMAC_CHEVCTRL5</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A096UL)</td></tr>
|
|
<tr class="memdesc:aa03c6226812bac16a7f15613a7ee4354"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 5 Event Control <br /></td></tr>
|
|
<tr class="separator:aa03c6226812bac16a7f15613a7ee4354"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ab363c51a83f426e3df1e5313f8a2df11"><td class="memItemLeft" align="right" valign="top"><a id="ab363c51a83f426e3df1e5313f8a2df11"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ab363c51a83f426e3df1e5313f8a2df11">REG_DMAC_CHINTENCLR5</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A09CUL)</td></tr>
|
|
<tr class="memdesc:ab363c51a83f426e3df1e5313f8a2df11"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 5 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:ab363c51a83f426e3df1e5313f8a2df11"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa9f9a8ed660dd41329191e18c2a12a9a"><td class="memItemLeft" align="right" valign="top"><a id="aa9f9a8ed660dd41329191e18c2a12a9a"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aa9f9a8ed660dd41329191e18c2a12a9a">REG_DMAC_CHINTENSET5</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A09DUL)</td></tr>
|
|
<tr class="memdesc:aa9f9a8ed660dd41329191e18c2a12a9a"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 5 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:aa9f9a8ed660dd41329191e18c2a12a9a"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ab526d101b640054e90f59b445d77cd4e"><td class="memItemLeft" align="right" valign="top"><a id="ab526d101b640054e90f59b445d77cd4e"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ab526d101b640054e90f59b445d77cd4e">REG_DMAC_CHINTFLAG5</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A09EUL)</td></tr>
|
|
<tr class="memdesc:ab526d101b640054e90f59b445d77cd4e"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 5 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:ab526d101b640054e90f59b445d77cd4e"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1776c9e3ac60ced70d0dfdfdee805633"><td class="memItemLeft" align="right" valign="top"><a id="a1776c9e3ac60ced70d0dfdfdee805633"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1776c9e3ac60ced70d0dfdfdee805633">REG_DMAC_CHSTATUS5</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A09FUL)</td></tr>
|
|
<tr class="memdesc:a1776c9e3ac60ced70d0dfdfdee805633"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 5 Status <br /></td></tr>
|
|
<tr class="separator:a1776c9e3ac60ced70d0dfdfdee805633"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:affec6e2ab9718e070fcd9f6d69d87586"><td class="memItemLeft" align="right" valign="top"><a id="affec6e2ab9718e070fcd9f6d69d87586"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#affec6e2ab9718e070fcd9f6d69d87586">REG_DMAC_CHCTRLA6</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A0A0UL)</td></tr>
|
|
<tr class="memdesc:affec6e2ab9718e070fcd9f6d69d87586"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 6 Control A <br /></td></tr>
|
|
<tr class="separator:affec6e2ab9718e070fcd9f6d69d87586"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a835c839f56ec54e430a8648fb119d309"><td class="memItemLeft" align="right" valign="top"><a id="a835c839f56ec54e430a8648fb119d309"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a835c839f56ec54e430a8648fb119d309">REG_DMAC_CHCTRLB6</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0A4UL)</td></tr>
|
|
<tr class="memdesc:a835c839f56ec54e430a8648fb119d309"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 6 Control B <br /></td></tr>
|
|
<tr class="separator:a835c839f56ec54e430a8648fb119d309"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1227959d7366079835678dd63cf3b731"><td class="memItemLeft" align="right" valign="top"><a id="a1227959d7366079835678dd63cf3b731"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1227959d7366079835678dd63cf3b731">REG_DMAC_CHPRILVL6</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0A5UL)</td></tr>
|
|
<tr class="memdesc:a1227959d7366079835678dd63cf3b731"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 6 Priority Level <br /></td></tr>
|
|
<tr class="separator:a1227959d7366079835678dd63cf3b731"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3f6449038e3f2f9c5dff9bba33c7c1e3"><td class="memItemLeft" align="right" valign="top"><a id="a3f6449038e3f2f9c5dff9bba33c7c1e3"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3f6449038e3f2f9c5dff9bba33c7c1e3">REG_DMAC_CHEVCTRL6</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0A6UL)</td></tr>
|
|
<tr class="memdesc:a3f6449038e3f2f9c5dff9bba33c7c1e3"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 6 Event Control <br /></td></tr>
|
|
<tr class="separator:a3f6449038e3f2f9c5dff9bba33c7c1e3"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a60814da36a29acf713d9a34869e2b6a7"><td class="memItemLeft" align="right" valign="top"><a id="a60814da36a29acf713d9a34869e2b6a7"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a60814da36a29acf713d9a34869e2b6a7">REG_DMAC_CHINTENCLR6</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0ACUL)</td></tr>
|
|
<tr class="memdesc:a60814da36a29acf713d9a34869e2b6a7"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 6 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a60814da36a29acf713d9a34869e2b6a7"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a8ddb1d347e26885d76340de2a216c970"><td class="memItemLeft" align="right" valign="top"><a id="a8ddb1d347e26885d76340de2a216c970"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a8ddb1d347e26885d76340de2a216c970">REG_DMAC_CHINTENSET6</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0ADUL)</td></tr>
|
|
<tr class="memdesc:a8ddb1d347e26885d76340de2a216c970"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 6 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a8ddb1d347e26885d76340de2a216c970"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa209a86ab51bdd5dbcc4c6d9d830b414"><td class="memItemLeft" align="right" valign="top"><a id="aa209a86ab51bdd5dbcc4c6d9d830b414"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aa209a86ab51bdd5dbcc4c6d9d830b414">REG_DMAC_CHINTFLAG6</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0AEUL)</td></tr>
|
|
<tr class="memdesc:aa209a86ab51bdd5dbcc4c6d9d830b414"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 6 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:aa209a86ab51bdd5dbcc4c6d9d830b414"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a867e9bf2e6391f2993768c7e11bb7046"><td class="memItemLeft" align="right" valign="top"><a id="a867e9bf2e6391f2993768c7e11bb7046"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a867e9bf2e6391f2993768c7e11bb7046">REG_DMAC_CHSTATUS6</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0AFUL)</td></tr>
|
|
<tr class="memdesc:a867e9bf2e6391f2993768c7e11bb7046"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 6 Status <br /></td></tr>
|
|
<tr class="separator:a867e9bf2e6391f2993768c7e11bb7046"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:adfe420f4fec2070e59049601e385952b"><td class="memItemLeft" align="right" valign="top"><a id="adfe420f4fec2070e59049601e385952b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#adfe420f4fec2070e59049601e385952b">REG_DMAC_CHCTRLA7</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A0B0UL)</td></tr>
|
|
<tr class="memdesc:adfe420f4fec2070e59049601e385952b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 7 Control A <br /></td></tr>
|
|
<tr class="separator:adfe420f4fec2070e59049601e385952b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3684dae12e0ba9e6fcc63c5412687ab5"><td class="memItemLeft" align="right" valign="top"><a id="a3684dae12e0ba9e6fcc63c5412687ab5"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3684dae12e0ba9e6fcc63c5412687ab5">REG_DMAC_CHCTRLB7</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0B4UL)</td></tr>
|
|
<tr class="memdesc:a3684dae12e0ba9e6fcc63c5412687ab5"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 7 Control B <br /></td></tr>
|
|
<tr class="separator:a3684dae12e0ba9e6fcc63c5412687ab5"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aff6f137ed6f6a18115c2aec61bc84051"><td class="memItemLeft" align="right" valign="top"><a id="aff6f137ed6f6a18115c2aec61bc84051"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aff6f137ed6f6a18115c2aec61bc84051">REG_DMAC_CHPRILVL7</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0B5UL)</td></tr>
|
|
<tr class="memdesc:aff6f137ed6f6a18115c2aec61bc84051"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 7 Priority Level <br /></td></tr>
|
|
<tr class="separator:aff6f137ed6f6a18115c2aec61bc84051"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad1a2ee60ae56b2bcc0fb027736674a09"><td class="memItemLeft" align="right" valign="top"><a id="ad1a2ee60ae56b2bcc0fb027736674a09"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad1a2ee60ae56b2bcc0fb027736674a09">REG_DMAC_CHEVCTRL7</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0B6UL)</td></tr>
|
|
<tr class="memdesc:ad1a2ee60ae56b2bcc0fb027736674a09"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 7 Event Control <br /></td></tr>
|
|
<tr class="separator:ad1a2ee60ae56b2bcc0fb027736674a09"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a7bb0915bd84a248da646b3f0fd8f77d9"><td class="memItemLeft" align="right" valign="top"><a id="a7bb0915bd84a248da646b3f0fd8f77d9"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a7bb0915bd84a248da646b3f0fd8f77d9">REG_DMAC_CHINTENCLR7</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0BCUL)</td></tr>
|
|
<tr class="memdesc:a7bb0915bd84a248da646b3f0fd8f77d9"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 7 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a7bb0915bd84a248da646b3f0fd8f77d9"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aba71a28c6c5444940701f32833b077fd"><td class="memItemLeft" align="right" valign="top"><a id="aba71a28c6c5444940701f32833b077fd"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aba71a28c6c5444940701f32833b077fd">REG_DMAC_CHINTENSET7</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0BDUL)</td></tr>
|
|
<tr class="memdesc:aba71a28c6c5444940701f32833b077fd"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 7 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:aba71a28c6c5444940701f32833b077fd"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a6774b74bc1ad152fc97efe4abefebd7b"><td class="memItemLeft" align="right" valign="top"><a id="a6774b74bc1ad152fc97efe4abefebd7b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a6774b74bc1ad152fc97efe4abefebd7b">REG_DMAC_CHINTFLAG7</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0BEUL)</td></tr>
|
|
<tr class="memdesc:a6774b74bc1ad152fc97efe4abefebd7b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 7 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a6774b74bc1ad152fc97efe4abefebd7b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a04c0f45364ba3fa6723cfb70b0e86c4e"><td class="memItemLeft" align="right" valign="top"><a id="a04c0f45364ba3fa6723cfb70b0e86c4e"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a04c0f45364ba3fa6723cfb70b0e86c4e">REG_DMAC_CHSTATUS7</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0BFUL)</td></tr>
|
|
<tr class="memdesc:a04c0f45364ba3fa6723cfb70b0e86c4e"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 7 Status <br /></td></tr>
|
|
<tr class="separator:a04c0f45364ba3fa6723cfb70b0e86c4e"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ae96268d0c7f83e29c9b8348783305aa2"><td class="memItemLeft" align="right" valign="top"><a id="ae96268d0c7f83e29c9b8348783305aa2"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ae96268d0c7f83e29c9b8348783305aa2">REG_DMAC_CHCTRLA8</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A0C0UL)</td></tr>
|
|
<tr class="memdesc:ae96268d0c7f83e29c9b8348783305aa2"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 8 Control A <br /></td></tr>
|
|
<tr class="separator:ae96268d0c7f83e29c9b8348783305aa2"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3068a687d3f3c63c617225ec380f4b5e"><td class="memItemLeft" align="right" valign="top"><a id="a3068a687d3f3c63c617225ec380f4b5e"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3068a687d3f3c63c617225ec380f4b5e">REG_DMAC_CHCTRLB8</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0C4UL)</td></tr>
|
|
<tr class="memdesc:a3068a687d3f3c63c617225ec380f4b5e"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 8 Control B <br /></td></tr>
|
|
<tr class="separator:a3068a687d3f3c63c617225ec380f4b5e"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a177351f4a13ec629e20c5e3d4a6ac1dc"><td class="memItemLeft" align="right" valign="top"><a id="a177351f4a13ec629e20c5e3d4a6ac1dc"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a177351f4a13ec629e20c5e3d4a6ac1dc">REG_DMAC_CHPRILVL8</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0C5UL)</td></tr>
|
|
<tr class="memdesc:a177351f4a13ec629e20c5e3d4a6ac1dc"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 8 Priority Level <br /></td></tr>
|
|
<tr class="separator:a177351f4a13ec629e20c5e3d4a6ac1dc"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1306b37e2776334c396288651648df31"><td class="memItemLeft" align="right" valign="top"><a id="a1306b37e2776334c396288651648df31"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1306b37e2776334c396288651648df31">REG_DMAC_CHEVCTRL8</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0C6UL)</td></tr>
|
|
<tr class="memdesc:a1306b37e2776334c396288651648df31"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 8 Event Control <br /></td></tr>
|
|
<tr class="separator:a1306b37e2776334c396288651648df31"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a6dd358fbe1070d62c05fe2350c0c332f"><td class="memItemLeft" align="right" valign="top"><a id="a6dd358fbe1070d62c05fe2350c0c332f"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a6dd358fbe1070d62c05fe2350c0c332f">REG_DMAC_CHINTENCLR8</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0CCUL)</td></tr>
|
|
<tr class="memdesc:a6dd358fbe1070d62c05fe2350c0c332f"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 8 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a6dd358fbe1070d62c05fe2350c0c332f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:adb5c2243e1706096dba42a2adb9b4f96"><td class="memItemLeft" align="right" valign="top"><a id="adb5c2243e1706096dba42a2adb9b4f96"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#adb5c2243e1706096dba42a2adb9b4f96">REG_DMAC_CHINTENSET8</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0CDUL)</td></tr>
|
|
<tr class="memdesc:adb5c2243e1706096dba42a2adb9b4f96"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 8 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:adb5c2243e1706096dba42a2adb9b4f96"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a105f01d63550e4ee5f0fd575665ea2d3"><td class="memItemLeft" align="right" valign="top"><a id="a105f01d63550e4ee5f0fd575665ea2d3"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a105f01d63550e4ee5f0fd575665ea2d3">REG_DMAC_CHINTFLAG8</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0CEUL)</td></tr>
|
|
<tr class="memdesc:a105f01d63550e4ee5f0fd575665ea2d3"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 8 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a105f01d63550e4ee5f0fd575665ea2d3"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1e0675e84eece8edd6c51856747426ba"><td class="memItemLeft" align="right" valign="top"><a id="a1e0675e84eece8edd6c51856747426ba"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1e0675e84eece8edd6c51856747426ba">REG_DMAC_CHSTATUS8</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0CFUL)</td></tr>
|
|
<tr class="memdesc:a1e0675e84eece8edd6c51856747426ba"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 8 Status <br /></td></tr>
|
|
<tr class="separator:a1e0675e84eece8edd6c51856747426ba"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a5c64d172e64190e392a29bdf64caff19"><td class="memItemLeft" align="right" valign="top"><a id="a5c64d172e64190e392a29bdf64caff19"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a5c64d172e64190e392a29bdf64caff19">REG_DMAC_CHCTRLA9</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A0D0UL)</td></tr>
|
|
<tr class="memdesc:a5c64d172e64190e392a29bdf64caff19"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 9 Control A <br /></td></tr>
|
|
<tr class="separator:a5c64d172e64190e392a29bdf64caff19"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a8adfcb00eb6c51169da7e1e3fb37d0ed"><td class="memItemLeft" align="right" valign="top"><a id="a8adfcb00eb6c51169da7e1e3fb37d0ed"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a8adfcb00eb6c51169da7e1e3fb37d0ed">REG_DMAC_CHCTRLB9</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0D4UL)</td></tr>
|
|
<tr class="memdesc:a8adfcb00eb6c51169da7e1e3fb37d0ed"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 9 Control B <br /></td></tr>
|
|
<tr class="separator:a8adfcb00eb6c51169da7e1e3fb37d0ed"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a4aba532fd4ef0ce46ff5a6606ca602b6"><td class="memItemLeft" align="right" valign="top"><a id="a4aba532fd4ef0ce46ff5a6606ca602b6"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a4aba532fd4ef0ce46ff5a6606ca602b6">REG_DMAC_CHPRILVL9</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0D5UL)</td></tr>
|
|
<tr class="memdesc:a4aba532fd4ef0ce46ff5a6606ca602b6"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 9 Priority Level <br /></td></tr>
|
|
<tr class="separator:a4aba532fd4ef0ce46ff5a6606ca602b6"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af0053d00f488a9c7a3623d7da1faba93"><td class="memItemLeft" align="right" valign="top"><a id="af0053d00f488a9c7a3623d7da1faba93"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af0053d00f488a9c7a3623d7da1faba93">REG_DMAC_CHEVCTRL9</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0D6UL)</td></tr>
|
|
<tr class="memdesc:af0053d00f488a9c7a3623d7da1faba93"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 9 Event Control <br /></td></tr>
|
|
<tr class="separator:af0053d00f488a9c7a3623d7da1faba93"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3f413d99cdbd73a9c88c821dda27174b"><td class="memItemLeft" align="right" valign="top"><a id="a3f413d99cdbd73a9c88c821dda27174b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3f413d99cdbd73a9c88c821dda27174b">REG_DMAC_CHINTENCLR9</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0DCUL)</td></tr>
|
|
<tr class="memdesc:a3f413d99cdbd73a9c88c821dda27174b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 9 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a3f413d99cdbd73a9c88c821dda27174b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a7f9578baa8c9d879f529b66a6566ec25"><td class="memItemLeft" align="right" valign="top"><a id="a7f9578baa8c9d879f529b66a6566ec25"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a7f9578baa8c9d879f529b66a6566ec25">REG_DMAC_CHINTENSET9</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0DDUL)</td></tr>
|
|
<tr class="memdesc:a7f9578baa8c9d879f529b66a6566ec25"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 9 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a7f9578baa8c9d879f529b66a6566ec25"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a9eeb773b20f42a281fccfce34f9d9c86"><td class="memItemLeft" align="right" valign="top"><a id="a9eeb773b20f42a281fccfce34f9d9c86"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a9eeb773b20f42a281fccfce34f9d9c86">REG_DMAC_CHINTFLAG9</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0DEUL)</td></tr>
|
|
<tr class="memdesc:a9eeb773b20f42a281fccfce34f9d9c86"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 9 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a9eeb773b20f42a281fccfce34f9d9c86"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a7c507cbdb0ee7e28c37873bdc81a52be"><td class="memItemLeft" align="right" valign="top"><a id="a7c507cbdb0ee7e28c37873bdc81a52be"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a7c507cbdb0ee7e28c37873bdc81a52be">REG_DMAC_CHSTATUS9</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0DFUL)</td></tr>
|
|
<tr class="memdesc:a7c507cbdb0ee7e28c37873bdc81a52be"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 9 Status <br /></td></tr>
|
|
<tr class="separator:a7c507cbdb0ee7e28c37873bdc81a52be"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a6d4e4264e48788dfa410344b94b8b180"><td class="memItemLeft" align="right" valign="top"><a id="a6d4e4264e48788dfa410344b94b8b180"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a6d4e4264e48788dfa410344b94b8b180">REG_DMAC_CHCTRLA10</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A0E0UL)</td></tr>
|
|
<tr class="memdesc:a6d4e4264e48788dfa410344b94b8b180"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 10 Control A <br /></td></tr>
|
|
<tr class="separator:a6d4e4264e48788dfa410344b94b8b180"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a381abba6f00dec72af48c548bac4596e"><td class="memItemLeft" align="right" valign="top"><a id="a381abba6f00dec72af48c548bac4596e"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a381abba6f00dec72af48c548bac4596e">REG_DMAC_CHCTRLB10</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0E4UL)</td></tr>
|
|
<tr class="memdesc:a381abba6f00dec72af48c548bac4596e"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 10 Control B <br /></td></tr>
|
|
<tr class="separator:a381abba6f00dec72af48c548bac4596e"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a73672c693e8d1e55619bb452c3049a73"><td class="memItemLeft" align="right" valign="top"><a id="a73672c693e8d1e55619bb452c3049a73"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a73672c693e8d1e55619bb452c3049a73">REG_DMAC_CHPRILVL10</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0E5UL)</td></tr>
|
|
<tr class="memdesc:a73672c693e8d1e55619bb452c3049a73"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 10 Priority Level <br /></td></tr>
|
|
<tr class="separator:a73672c693e8d1e55619bb452c3049a73"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a7e7dd3dfbf0a12d5cb6a77f65fe8bcc3"><td class="memItemLeft" align="right" valign="top"><a id="a7e7dd3dfbf0a12d5cb6a77f65fe8bcc3"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a7e7dd3dfbf0a12d5cb6a77f65fe8bcc3">REG_DMAC_CHEVCTRL10</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0E6UL)</td></tr>
|
|
<tr class="memdesc:a7e7dd3dfbf0a12d5cb6a77f65fe8bcc3"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 10 Event Control <br /></td></tr>
|
|
<tr class="separator:a7e7dd3dfbf0a12d5cb6a77f65fe8bcc3"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a77aa20fdb27303ea4830de228f0f778f"><td class="memItemLeft" align="right" valign="top"><a id="a77aa20fdb27303ea4830de228f0f778f"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a77aa20fdb27303ea4830de228f0f778f">REG_DMAC_CHINTENCLR10</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0ECUL)</td></tr>
|
|
<tr class="memdesc:a77aa20fdb27303ea4830de228f0f778f"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 10 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a77aa20fdb27303ea4830de228f0f778f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a2e85b158b5a9afcaec38fcecd5c8a92d"><td class="memItemLeft" align="right" valign="top"><a id="a2e85b158b5a9afcaec38fcecd5c8a92d"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a2e85b158b5a9afcaec38fcecd5c8a92d">REG_DMAC_CHINTENSET10</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0EDUL)</td></tr>
|
|
<tr class="memdesc:a2e85b158b5a9afcaec38fcecd5c8a92d"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 10 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a2e85b158b5a9afcaec38fcecd5c8a92d"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a6769300cb46df86c53363b96503ad0df"><td class="memItemLeft" align="right" valign="top"><a id="a6769300cb46df86c53363b96503ad0df"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a6769300cb46df86c53363b96503ad0df">REG_DMAC_CHINTFLAG10</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0EEUL)</td></tr>
|
|
<tr class="memdesc:a6769300cb46df86c53363b96503ad0df"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 10 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a6769300cb46df86c53363b96503ad0df"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a0b332042ebe3a4e0279554ecf9d29d51"><td class="memItemLeft" align="right" valign="top"><a id="a0b332042ebe3a4e0279554ecf9d29d51"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a0b332042ebe3a4e0279554ecf9d29d51">REG_DMAC_CHSTATUS10</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0EFUL)</td></tr>
|
|
<tr class="memdesc:a0b332042ebe3a4e0279554ecf9d29d51"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 10 Status <br /></td></tr>
|
|
<tr class="separator:a0b332042ebe3a4e0279554ecf9d29d51"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af21be2650920dd28f8ef88a54b016dce"><td class="memItemLeft" align="right" valign="top"><a id="af21be2650920dd28f8ef88a54b016dce"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af21be2650920dd28f8ef88a54b016dce">REG_DMAC_CHCTRLA11</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A0F0UL)</td></tr>
|
|
<tr class="memdesc:af21be2650920dd28f8ef88a54b016dce"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 11 Control A <br /></td></tr>
|
|
<tr class="separator:af21be2650920dd28f8ef88a54b016dce"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a84dc88eaab63759e70e96c3a727b58d3"><td class="memItemLeft" align="right" valign="top"><a id="a84dc88eaab63759e70e96c3a727b58d3"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a84dc88eaab63759e70e96c3a727b58d3">REG_DMAC_CHCTRLB11</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0F4UL)</td></tr>
|
|
<tr class="memdesc:a84dc88eaab63759e70e96c3a727b58d3"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 11 Control B <br /></td></tr>
|
|
<tr class="separator:a84dc88eaab63759e70e96c3a727b58d3"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aaf93be17a7be5f26ad1be9edbc09a569"><td class="memItemLeft" align="right" valign="top"><a id="aaf93be17a7be5f26ad1be9edbc09a569"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aaf93be17a7be5f26ad1be9edbc09a569">REG_DMAC_CHPRILVL11</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0F5UL)</td></tr>
|
|
<tr class="memdesc:aaf93be17a7be5f26ad1be9edbc09a569"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 11 Priority Level <br /></td></tr>
|
|
<tr class="separator:aaf93be17a7be5f26ad1be9edbc09a569"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ac90f99e37a5cc1466fdf51ccdd8d7f60"><td class="memItemLeft" align="right" valign="top"><a id="ac90f99e37a5cc1466fdf51ccdd8d7f60"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ac90f99e37a5cc1466fdf51ccdd8d7f60">REG_DMAC_CHEVCTRL11</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0F6UL)</td></tr>
|
|
<tr class="memdesc:ac90f99e37a5cc1466fdf51ccdd8d7f60"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 11 Event Control <br /></td></tr>
|
|
<tr class="separator:ac90f99e37a5cc1466fdf51ccdd8d7f60"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a571befb2f946e576078acd29a2718660"><td class="memItemLeft" align="right" valign="top"><a id="a571befb2f946e576078acd29a2718660"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a571befb2f946e576078acd29a2718660">REG_DMAC_CHINTENCLR11</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0FCUL)</td></tr>
|
|
<tr class="memdesc:a571befb2f946e576078acd29a2718660"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 11 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a571befb2f946e576078acd29a2718660"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a26f9402f3ff7a82324af9c36abe6b945"><td class="memItemLeft" align="right" valign="top"><a id="a26f9402f3ff7a82324af9c36abe6b945"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a26f9402f3ff7a82324af9c36abe6b945">REG_DMAC_CHINTENSET11</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0FDUL)</td></tr>
|
|
<tr class="memdesc:a26f9402f3ff7a82324af9c36abe6b945"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 11 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a26f9402f3ff7a82324af9c36abe6b945"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aefc421c693a5e0ac34b6ee007f1b8157"><td class="memItemLeft" align="right" valign="top"><a id="aefc421c693a5e0ac34b6ee007f1b8157"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aefc421c693a5e0ac34b6ee007f1b8157">REG_DMAC_CHINTFLAG11</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0FEUL)</td></tr>
|
|
<tr class="memdesc:aefc421c693a5e0ac34b6ee007f1b8157"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 11 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:aefc421c693a5e0ac34b6ee007f1b8157"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a4980dc5f5a23c7e36ee979c172c3d832"><td class="memItemLeft" align="right" valign="top"><a id="a4980dc5f5a23c7e36ee979c172c3d832"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a4980dc5f5a23c7e36ee979c172c3d832">REG_DMAC_CHSTATUS11</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A0FFUL)</td></tr>
|
|
<tr class="memdesc:a4980dc5f5a23c7e36ee979c172c3d832"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 11 Status <br /></td></tr>
|
|
<tr class="separator:a4980dc5f5a23c7e36ee979c172c3d832"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a40272582f200ff6e7529768b41e85120"><td class="memItemLeft" align="right" valign="top"><a id="a40272582f200ff6e7529768b41e85120"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a40272582f200ff6e7529768b41e85120">REG_DMAC_CHCTRLA12</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A100UL)</td></tr>
|
|
<tr class="memdesc:a40272582f200ff6e7529768b41e85120"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 12 Control A <br /></td></tr>
|
|
<tr class="separator:a40272582f200ff6e7529768b41e85120"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a21af3e0db1134cfc49752dc84b2bbf84"><td class="memItemLeft" align="right" valign="top"><a id="a21af3e0db1134cfc49752dc84b2bbf84"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a21af3e0db1134cfc49752dc84b2bbf84">REG_DMAC_CHCTRLB12</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A104UL)</td></tr>
|
|
<tr class="memdesc:a21af3e0db1134cfc49752dc84b2bbf84"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 12 Control B <br /></td></tr>
|
|
<tr class="separator:a21af3e0db1134cfc49752dc84b2bbf84"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a7f25c3dd7a2a9723dd6b970dfe520a2a"><td class="memItemLeft" align="right" valign="top"><a id="a7f25c3dd7a2a9723dd6b970dfe520a2a"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a7f25c3dd7a2a9723dd6b970dfe520a2a">REG_DMAC_CHPRILVL12</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A105UL)</td></tr>
|
|
<tr class="memdesc:a7f25c3dd7a2a9723dd6b970dfe520a2a"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 12 Priority Level <br /></td></tr>
|
|
<tr class="separator:a7f25c3dd7a2a9723dd6b970dfe520a2a"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:abbd92512e555c75b2babb58b240eb016"><td class="memItemLeft" align="right" valign="top"><a id="abbd92512e555c75b2babb58b240eb016"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#abbd92512e555c75b2babb58b240eb016">REG_DMAC_CHEVCTRL12</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A106UL)</td></tr>
|
|
<tr class="memdesc:abbd92512e555c75b2babb58b240eb016"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 12 Event Control <br /></td></tr>
|
|
<tr class="separator:abbd92512e555c75b2babb58b240eb016"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a5c5e05be568bb21b9cf4dbca9bb7a86f"><td class="memItemLeft" align="right" valign="top"><a id="a5c5e05be568bb21b9cf4dbca9bb7a86f"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a5c5e05be568bb21b9cf4dbca9bb7a86f">REG_DMAC_CHINTENCLR12</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A10CUL)</td></tr>
|
|
<tr class="memdesc:a5c5e05be568bb21b9cf4dbca9bb7a86f"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 12 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a5c5e05be568bb21b9cf4dbca9bb7a86f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a0e107bcc14f8c4e2f78a1935db6d9b8c"><td class="memItemLeft" align="right" valign="top"><a id="a0e107bcc14f8c4e2f78a1935db6d9b8c"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a0e107bcc14f8c4e2f78a1935db6d9b8c">REG_DMAC_CHINTENSET12</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A10DUL)</td></tr>
|
|
<tr class="memdesc:a0e107bcc14f8c4e2f78a1935db6d9b8c"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 12 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a0e107bcc14f8c4e2f78a1935db6d9b8c"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a008a1777535a9a6198be4a4ed5e796cd"><td class="memItemLeft" align="right" valign="top"><a id="a008a1777535a9a6198be4a4ed5e796cd"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a008a1777535a9a6198be4a4ed5e796cd">REG_DMAC_CHINTFLAG12</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A10EUL)</td></tr>
|
|
<tr class="memdesc:a008a1777535a9a6198be4a4ed5e796cd"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 12 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a008a1777535a9a6198be4a4ed5e796cd"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad98a8fc6235fb4c14fc36cee32ce235b"><td class="memItemLeft" align="right" valign="top"><a id="ad98a8fc6235fb4c14fc36cee32ce235b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad98a8fc6235fb4c14fc36cee32ce235b">REG_DMAC_CHSTATUS12</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A10FUL)</td></tr>
|
|
<tr class="memdesc:ad98a8fc6235fb4c14fc36cee32ce235b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 12 Status <br /></td></tr>
|
|
<tr class="separator:ad98a8fc6235fb4c14fc36cee32ce235b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a947773da07c7914173911133c5f67692"><td class="memItemLeft" align="right" valign="top"><a id="a947773da07c7914173911133c5f67692"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a947773da07c7914173911133c5f67692">REG_DMAC_CHCTRLA13</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A110UL)</td></tr>
|
|
<tr class="memdesc:a947773da07c7914173911133c5f67692"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 13 Control A <br /></td></tr>
|
|
<tr class="separator:a947773da07c7914173911133c5f67692"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a59d51276e22be2fe22a2bbd4a49920c6"><td class="memItemLeft" align="right" valign="top"><a id="a59d51276e22be2fe22a2bbd4a49920c6"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a59d51276e22be2fe22a2bbd4a49920c6">REG_DMAC_CHCTRLB13</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A114UL)</td></tr>
|
|
<tr class="memdesc:a59d51276e22be2fe22a2bbd4a49920c6"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 13 Control B <br /></td></tr>
|
|
<tr class="separator:a59d51276e22be2fe22a2bbd4a49920c6"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:adc29f7c32efc460bd67aaf042362ba86"><td class="memItemLeft" align="right" valign="top"><a id="adc29f7c32efc460bd67aaf042362ba86"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#adc29f7c32efc460bd67aaf042362ba86">REG_DMAC_CHPRILVL13</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A115UL)</td></tr>
|
|
<tr class="memdesc:adc29f7c32efc460bd67aaf042362ba86"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 13 Priority Level <br /></td></tr>
|
|
<tr class="separator:adc29f7c32efc460bd67aaf042362ba86"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ae4d1ab9a5a1e9755fa6245da3da03e39"><td class="memItemLeft" align="right" valign="top"><a id="ae4d1ab9a5a1e9755fa6245da3da03e39"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ae4d1ab9a5a1e9755fa6245da3da03e39">REG_DMAC_CHEVCTRL13</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A116UL)</td></tr>
|
|
<tr class="memdesc:ae4d1ab9a5a1e9755fa6245da3da03e39"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 13 Event Control <br /></td></tr>
|
|
<tr class="separator:ae4d1ab9a5a1e9755fa6245da3da03e39"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a462b8b89b62c8b4b45dc49a481a66d4b"><td class="memItemLeft" align="right" valign="top"><a id="a462b8b89b62c8b4b45dc49a481a66d4b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a462b8b89b62c8b4b45dc49a481a66d4b">REG_DMAC_CHINTENCLR13</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A11CUL)</td></tr>
|
|
<tr class="memdesc:a462b8b89b62c8b4b45dc49a481a66d4b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 13 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a462b8b89b62c8b4b45dc49a481a66d4b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a5ba5521d7896485e5a2ed7fc549b3462"><td class="memItemLeft" align="right" valign="top"><a id="a5ba5521d7896485e5a2ed7fc549b3462"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a5ba5521d7896485e5a2ed7fc549b3462">REG_DMAC_CHINTENSET13</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A11DUL)</td></tr>
|
|
<tr class="memdesc:a5ba5521d7896485e5a2ed7fc549b3462"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 13 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a5ba5521d7896485e5a2ed7fc549b3462"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a2e04cf425581a811f4454621390fe14c"><td class="memItemLeft" align="right" valign="top"><a id="a2e04cf425581a811f4454621390fe14c"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a2e04cf425581a811f4454621390fe14c">REG_DMAC_CHINTFLAG13</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A11EUL)</td></tr>
|
|
<tr class="memdesc:a2e04cf425581a811f4454621390fe14c"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 13 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a2e04cf425581a811f4454621390fe14c"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a29c733577fa8d2055e4bd948b0451bbe"><td class="memItemLeft" align="right" valign="top"><a id="a29c733577fa8d2055e4bd948b0451bbe"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a29c733577fa8d2055e4bd948b0451bbe">REG_DMAC_CHSTATUS13</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A11FUL)</td></tr>
|
|
<tr class="memdesc:a29c733577fa8d2055e4bd948b0451bbe"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 13 Status <br /></td></tr>
|
|
<tr class="separator:a29c733577fa8d2055e4bd948b0451bbe"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:afa9c372900cded50a93737f82a6a9980"><td class="memItemLeft" align="right" valign="top"><a id="afa9c372900cded50a93737f82a6a9980"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#afa9c372900cded50a93737f82a6a9980">REG_DMAC_CHCTRLA14</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A120UL)</td></tr>
|
|
<tr class="memdesc:afa9c372900cded50a93737f82a6a9980"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 14 Control A <br /></td></tr>
|
|
<tr class="separator:afa9c372900cded50a93737f82a6a9980"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a768152a86e1cf7b3e86b6ffe6801d4f6"><td class="memItemLeft" align="right" valign="top"><a id="a768152a86e1cf7b3e86b6ffe6801d4f6"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a768152a86e1cf7b3e86b6ffe6801d4f6">REG_DMAC_CHCTRLB14</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A124UL)</td></tr>
|
|
<tr class="memdesc:a768152a86e1cf7b3e86b6ffe6801d4f6"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 14 Control B <br /></td></tr>
|
|
<tr class="separator:a768152a86e1cf7b3e86b6ffe6801d4f6"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa661a47e44a19b1e76c6a5278ce9903e"><td class="memItemLeft" align="right" valign="top"><a id="aa661a47e44a19b1e76c6a5278ce9903e"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aa661a47e44a19b1e76c6a5278ce9903e">REG_DMAC_CHPRILVL14</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A125UL)</td></tr>
|
|
<tr class="memdesc:aa661a47e44a19b1e76c6a5278ce9903e"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 14 Priority Level <br /></td></tr>
|
|
<tr class="separator:aa661a47e44a19b1e76c6a5278ce9903e"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a5e8d74b37a52f1e19bd0ddcc2ba4c25c"><td class="memItemLeft" align="right" valign="top"><a id="a5e8d74b37a52f1e19bd0ddcc2ba4c25c"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a5e8d74b37a52f1e19bd0ddcc2ba4c25c">REG_DMAC_CHEVCTRL14</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A126UL)</td></tr>
|
|
<tr class="memdesc:a5e8d74b37a52f1e19bd0ddcc2ba4c25c"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 14 Event Control <br /></td></tr>
|
|
<tr class="separator:a5e8d74b37a52f1e19bd0ddcc2ba4c25c"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:abac369119281573cf5a2609453988fa5"><td class="memItemLeft" align="right" valign="top"><a id="abac369119281573cf5a2609453988fa5"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#abac369119281573cf5a2609453988fa5">REG_DMAC_CHINTENCLR14</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A12CUL)</td></tr>
|
|
<tr class="memdesc:abac369119281573cf5a2609453988fa5"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 14 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:abac369119281573cf5a2609453988fa5"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a477e12b41d1edb03043b06cb07c23f46"><td class="memItemLeft" align="right" valign="top"><a id="a477e12b41d1edb03043b06cb07c23f46"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a477e12b41d1edb03043b06cb07c23f46">REG_DMAC_CHINTENSET14</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A12DUL)</td></tr>
|
|
<tr class="memdesc:a477e12b41d1edb03043b06cb07c23f46"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 14 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a477e12b41d1edb03043b06cb07c23f46"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a237d9b9a0e62ff4c6b46df361ff2fb94"><td class="memItemLeft" align="right" valign="top"><a id="a237d9b9a0e62ff4c6b46df361ff2fb94"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a237d9b9a0e62ff4c6b46df361ff2fb94">REG_DMAC_CHINTFLAG14</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A12EUL)</td></tr>
|
|
<tr class="memdesc:a237d9b9a0e62ff4c6b46df361ff2fb94"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 14 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a237d9b9a0e62ff4c6b46df361ff2fb94"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1db5415eea95c54f4ec98ddf1f0f2e62"><td class="memItemLeft" align="right" valign="top"><a id="a1db5415eea95c54f4ec98ddf1f0f2e62"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1db5415eea95c54f4ec98ddf1f0f2e62">REG_DMAC_CHSTATUS14</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A12FUL)</td></tr>
|
|
<tr class="memdesc:a1db5415eea95c54f4ec98ddf1f0f2e62"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 14 Status <br /></td></tr>
|
|
<tr class="separator:a1db5415eea95c54f4ec98ddf1f0f2e62"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a31e033962dd8f1b798ed209044e5df73"><td class="memItemLeft" align="right" valign="top"><a id="a31e033962dd8f1b798ed209044e5df73"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a31e033962dd8f1b798ed209044e5df73">REG_DMAC_CHCTRLA15</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A130UL)</td></tr>
|
|
<tr class="memdesc:a31e033962dd8f1b798ed209044e5df73"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 15 Control A <br /></td></tr>
|
|
<tr class="separator:a31e033962dd8f1b798ed209044e5df73"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:abe162a198e90390dfd51618f7c3186f5"><td class="memItemLeft" align="right" valign="top"><a id="abe162a198e90390dfd51618f7c3186f5"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#abe162a198e90390dfd51618f7c3186f5">REG_DMAC_CHCTRLB15</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A134UL)</td></tr>
|
|
<tr class="memdesc:abe162a198e90390dfd51618f7c3186f5"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 15 Control B <br /></td></tr>
|
|
<tr class="separator:abe162a198e90390dfd51618f7c3186f5"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a4a44e52ce066379ff9b80fd9e6e70cd9"><td class="memItemLeft" align="right" valign="top"><a id="a4a44e52ce066379ff9b80fd9e6e70cd9"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a4a44e52ce066379ff9b80fd9e6e70cd9">REG_DMAC_CHPRILVL15</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A135UL)</td></tr>
|
|
<tr class="memdesc:a4a44e52ce066379ff9b80fd9e6e70cd9"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 15 Priority Level <br /></td></tr>
|
|
<tr class="separator:a4a44e52ce066379ff9b80fd9e6e70cd9"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a106a5cf11bbe86602b87600dd399f680"><td class="memItemLeft" align="right" valign="top"><a id="a106a5cf11bbe86602b87600dd399f680"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a106a5cf11bbe86602b87600dd399f680">REG_DMAC_CHEVCTRL15</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A136UL)</td></tr>
|
|
<tr class="memdesc:a106a5cf11bbe86602b87600dd399f680"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 15 Event Control <br /></td></tr>
|
|
<tr class="separator:a106a5cf11bbe86602b87600dd399f680"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3e82541cb5a10b5c75b2fc8f116cf492"><td class="memItemLeft" align="right" valign="top"><a id="a3e82541cb5a10b5c75b2fc8f116cf492"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3e82541cb5a10b5c75b2fc8f116cf492">REG_DMAC_CHINTENCLR15</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A13CUL)</td></tr>
|
|
<tr class="memdesc:a3e82541cb5a10b5c75b2fc8f116cf492"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 15 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a3e82541cb5a10b5c75b2fc8f116cf492"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a8efc8eff29921011e8b2d35ba5882bfd"><td class="memItemLeft" align="right" valign="top"><a id="a8efc8eff29921011e8b2d35ba5882bfd"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a8efc8eff29921011e8b2d35ba5882bfd">REG_DMAC_CHINTENSET15</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A13DUL)</td></tr>
|
|
<tr class="memdesc:a8efc8eff29921011e8b2d35ba5882bfd"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 15 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a8efc8eff29921011e8b2d35ba5882bfd"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aba074178325793f24e3fa7f0b692fdd4"><td class="memItemLeft" align="right" valign="top"><a id="aba074178325793f24e3fa7f0b692fdd4"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aba074178325793f24e3fa7f0b692fdd4">REG_DMAC_CHINTFLAG15</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A13EUL)</td></tr>
|
|
<tr class="memdesc:aba074178325793f24e3fa7f0b692fdd4"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 15 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:aba074178325793f24e3fa7f0b692fdd4"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ac2fe1d63d81b765994612c3b41b605c4"><td class="memItemLeft" align="right" valign="top"><a id="ac2fe1d63d81b765994612c3b41b605c4"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ac2fe1d63d81b765994612c3b41b605c4">REG_DMAC_CHSTATUS15</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A13FUL)</td></tr>
|
|
<tr class="memdesc:ac2fe1d63d81b765994612c3b41b605c4"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 15 Status <br /></td></tr>
|
|
<tr class="separator:ac2fe1d63d81b765994612c3b41b605c4"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a18b4c204ef35e4f99793e6beb24890c2"><td class="memItemLeft" align="right" valign="top"><a id="a18b4c204ef35e4f99793e6beb24890c2"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a18b4c204ef35e4f99793e6beb24890c2">REG_DMAC_CHCTRLA16</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A140UL)</td></tr>
|
|
<tr class="memdesc:a18b4c204ef35e4f99793e6beb24890c2"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 16 Control A <br /></td></tr>
|
|
<tr class="separator:a18b4c204ef35e4f99793e6beb24890c2"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a25aad210bc6d9d57f8e1dbf4a0aa7df6"><td class="memItemLeft" align="right" valign="top"><a id="a25aad210bc6d9d57f8e1dbf4a0aa7df6"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a25aad210bc6d9d57f8e1dbf4a0aa7df6">REG_DMAC_CHCTRLB16</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A144UL)</td></tr>
|
|
<tr class="memdesc:a25aad210bc6d9d57f8e1dbf4a0aa7df6"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 16 Control B <br /></td></tr>
|
|
<tr class="separator:a25aad210bc6d9d57f8e1dbf4a0aa7df6"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a9a1eb99190b77bbd70b4931ef7b904a6"><td class="memItemLeft" align="right" valign="top"><a id="a9a1eb99190b77bbd70b4931ef7b904a6"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a9a1eb99190b77bbd70b4931ef7b904a6">REG_DMAC_CHPRILVL16</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A145UL)</td></tr>
|
|
<tr class="memdesc:a9a1eb99190b77bbd70b4931ef7b904a6"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 16 Priority Level <br /></td></tr>
|
|
<tr class="separator:a9a1eb99190b77bbd70b4931ef7b904a6"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a0cfce420389cd01b7349946ac39bc012"><td class="memItemLeft" align="right" valign="top"><a id="a0cfce420389cd01b7349946ac39bc012"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a0cfce420389cd01b7349946ac39bc012">REG_DMAC_CHEVCTRL16</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A146UL)</td></tr>
|
|
<tr class="memdesc:a0cfce420389cd01b7349946ac39bc012"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 16 Event Control <br /></td></tr>
|
|
<tr class="separator:a0cfce420389cd01b7349946ac39bc012"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af22ff924fa7f7d9b4e4ea7fc9d067779"><td class="memItemLeft" align="right" valign="top"><a id="af22ff924fa7f7d9b4e4ea7fc9d067779"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af22ff924fa7f7d9b4e4ea7fc9d067779">REG_DMAC_CHINTENCLR16</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A14CUL)</td></tr>
|
|
<tr class="memdesc:af22ff924fa7f7d9b4e4ea7fc9d067779"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 16 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:af22ff924fa7f7d9b4e4ea7fc9d067779"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3032d1605b4df5a5211e9076fbc283bf"><td class="memItemLeft" align="right" valign="top"><a id="a3032d1605b4df5a5211e9076fbc283bf"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3032d1605b4df5a5211e9076fbc283bf">REG_DMAC_CHINTENSET16</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A14DUL)</td></tr>
|
|
<tr class="memdesc:a3032d1605b4df5a5211e9076fbc283bf"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 16 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a3032d1605b4df5a5211e9076fbc283bf"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3be397ced6360a9c862909b2e99d9979"><td class="memItemLeft" align="right" valign="top"><a id="a3be397ced6360a9c862909b2e99d9979"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3be397ced6360a9c862909b2e99d9979">REG_DMAC_CHINTFLAG16</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A14EUL)</td></tr>
|
|
<tr class="memdesc:a3be397ced6360a9c862909b2e99d9979"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 16 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a3be397ced6360a9c862909b2e99d9979"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aade36cf5ed9160aca02fe12b6ff9d9fd"><td class="memItemLeft" align="right" valign="top"><a id="aade36cf5ed9160aca02fe12b6ff9d9fd"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aade36cf5ed9160aca02fe12b6ff9d9fd">REG_DMAC_CHSTATUS16</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A14FUL)</td></tr>
|
|
<tr class="memdesc:aade36cf5ed9160aca02fe12b6ff9d9fd"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 16 Status <br /></td></tr>
|
|
<tr class="separator:aade36cf5ed9160aca02fe12b6ff9d9fd"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a79146cf18bde4c8ab31b9f0243faedd1"><td class="memItemLeft" align="right" valign="top"><a id="a79146cf18bde4c8ab31b9f0243faedd1"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a79146cf18bde4c8ab31b9f0243faedd1">REG_DMAC_CHCTRLA17</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A150UL)</td></tr>
|
|
<tr class="memdesc:a79146cf18bde4c8ab31b9f0243faedd1"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 17 Control A <br /></td></tr>
|
|
<tr class="separator:a79146cf18bde4c8ab31b9f0243faedd1"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad8a4f393bab19e67d6e49fde267d6bc5"><td class="memItemLeft" align="right" valign="top"><a id="ad8a4f393bab19e67d6e49fde267d6bc5"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad8a4f393bab19e67d6e49fde267d6bc5">REG_DMAC_CHCTRLB17</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A154UL)</td></tr>
|
|
<tr class="memdesc:ad8a4f393bab19e67d6e49fde267d6bc5"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 17 Control B <br /></td></tr>
|
|
<tr class="separator:ad8a4f393bab19e67d6e49fde267d6bc5"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ab0eafc548bb251e98f426e192947d6b9"><td class="memItemLeft" align="right" valign="top"><a id="ab0eafc548bb251e98f426e192947d6b9"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ab0eafc548bb251e98f426e192947d6b9">REG_DMAC_CHPRILVL17</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A155UL)</td></tr>
|
|
<tr class="memdesc:ab0eafc548bb251e98f426e192947d6b9"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 17 Priority Level <br /></td></tr>
|
|
<tr class="separator:ab0eafc548bb251e98f426e192947d6b9"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af95104b69db5974a683e3f6f1c104759"><td class="memItemLeft" align="right" valign="top"><a id="af95104b69db5974a683e3f6f1c104759"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af95104b69db5974a683e3f6f1c104759">REG_DMAC_CHEVCTRL17</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A156UL)</td></tr>
|
|
<tr class="memdesc:af95104b69db5974a683e3f6f1c104759"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 17 Event Control <br /></td></tr>
|
|
<tr class="separator:af95104b69db5974a683e3f6f1c104759"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a0b3f107ec528f048573ba557023d3ac4"><td class="memItemLeft" align="right" valign="top"><a id="a0b3f107ec528f048573ba557023d3ac4"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a0b3f107ec528f048573ba557023d3ac4">REG_DMAC_CHINTENCLR17</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A15CUL)</td></tr>
|
|
<tr class="memdesc:a0b3f107ec528f048573ba557023d3ac4"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 17 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a0b3f107ec528f048573ba557023d3ac4"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aef3f7a8233af3b29629bf5c6af5e34cd"><td class="memItemLeft" align="right" valign="top"><a id="aef3f7a8233af3b29629bf5c6af5e34cd"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aef3f7a8233af3b29629bf5c6af5e34cd">REG_DMAC_CHINTENSET17</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A15DUL)</td></tr>
|
|
<tr class="memdesc:aef3f7a8233af3b29629bf5c6af5e34cd"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 17 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:aef3f7a8233af3b29629bf5c6af5e34cd"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a6ad266c2e58b24362371034ca221bf50"><td class="memItemLeft" align="right" valign="top"><a id="a6ad266c2e58b24362371034ca221bf50"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a6ad266c2e58b24362371034ca221bf50">REG_DMAC_CHINTFLAG17</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A15EUL)</td></tr>
|
|
<tr class="memdesc:a6ad266c2e58b24362371034ca221bf50"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 17 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a6ad266c2e58b24362371034ca221bf50"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a09b526515a03d347cd44c3f8184c4639"><td class="memItemLeft" align="right" valign="top"><a id="a09b526515a03d347cd44c3f8184c4639"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a09b526515a03d347cd44c3f8184c4639">REG_DMAC_CHSTATUS17</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A15FUL)</td></tr>
|
|
<tr class="memdesc:a09b526515a03d347cd44c3f8184c4639"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 17 Status <br /></td></tr>
|
|
<tr class="separator:a09b526515a03d347cd44c3f8184c4639"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ae518c5aff937b73dc635b24a616873a5"><td class="memItemLeft" align="right" valign="top"><a id="ae518c5aff937b73dc635b24a616873a5"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ae518c5aff937b73dc635b24a616873a5">REG_DMAC_CHCTRLA18</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A160UL)</td></tr>
|
|
<tr class="memdesc:ae518c5aff937b73dc635b24a616873a5"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 18 Control A <br /></td></tr>
|
|
<tr class="separator:ae518c5aff937b73dc635b24a616873a5"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a00ffb05ba10d275ff8809a31f13c54f1"><td class="memItemLeft" align="right" valign="top"><a id="a00ffb05ba10d275ff8809a31f13c54f1"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a00ffb05ba10d275ff8809a31f13c54f1">REG_DMAC_CHCTRLB18</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A164UL)</td></tr>
|
|
<tr class="memdesc:a00ffb05ba10d275ff8809a31f13c54f1"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 18 Control B <br /></td></tr>
|
|
<tr class="separator:a00ffb05ba10d275ff8809a31f13c54f1"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a7ba42dd27f3540fa8b0ff40a4c950c43"><td class="memItemLeft" align="right" valign="top"><a id="a7ba42dd27f3540fa8b0ff40a4c950c43"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a7ba42dd27f3540fa8b0ff40a4c950c43">REG_DMAC_CHPRILVL18</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A165UL)</td></tr>
|
|
<tr class="memdesc:a7ba42dd27f3540fa8b0ff40a4c950c43"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 18 Priority Level <br /></td></tr>
|
|
<tr class="separator:a7ba42dd27f3540fa8b0ff40a4c950c43"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a19b47ae015f9568c03be248d6ee2f7ee"><td class="memItemLeft" align="right" valign="top"><a id="a19b47ae015f9568c03be248d6ee2f7ee"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a19b47ae015f9568c03be248d6ee2f7ee">REG_DMAC_CHEVCTRL18</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A166UL)</td></tr>
|
|
<tr class="memdesc:a19b47ae015f9568c03be248d6ee2f7ee"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 18 Event Control <br /></td></tr>
|
|
<tr class="separator:a19b47ae015f9568c03be248d6ee2f7ee"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad6f34b230adf4fd8e2e32843ce22b572"><td class="memItemLeft" align="right" valign="top"><a id="ad6f34b230adf4fd8e2e32843ce22b572"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad6f34b230adf4fd8e2e32843ce22b572">REG_DMAC_CHINTENCLR18</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A16CUL)</td></tr>
|
|
<tr class="memdesc:ad6f34b230adf4fd8e2e32843ce22b572"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 18 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:ad6f34b230adf4fd8e2e32843ce22b572"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af6895a67d31bdebb0fccf2f52098903b"><td class="memItemLeft" align="right" valign="top"><a id="af6895a67d31bdebb0fccf2f52098903b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af6895a67d31bdebb0fccf2f52098903b">REG_DMAC_CHINTENSET18</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A16DUL)</td></tr>
|
|
<tr class="memdesc:af6895a67d31bdebb0fccf2f52098903b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 18 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:af6895a67d31bdebb0fccf2f52098903b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3be3d11681a6e940a162c5177e2c861a"><td class="memItemLeft" align="right" valign="top"><a id="a3be3d11681a6e940a162c5177e2c861a"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3be3d11681a6e940a162c5177e2c861a">REG_DMAC_CHINTFLAG18</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A16EUL)</td></tr>
|
|
<tr class="memdesc:a3be3d11681a6e940a162c5177e2c861a"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 18 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a3be3d11681a6e940a162c5177e2c861a"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a32ccc75ab1262ec5a771d927d7589f1f"><td class="memItemLeft" align="right" valign="top"><a id="a32ccc75ab1262ec5a771d927d7589f1f"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a32ccc75ab1262ec5a771d927d7589f1f">REG_DMAC_CHSTATUS18</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A16FUL)</td></tr>
|
|
<tr class="memdesc:a32ccc75ab1262ec5a771d927d7589f1f"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 18 Status <br /></td></tr>
|
|
<tr class="separator:a32ccc75ab1262ec5a771d927d7589f1f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ac4493e95b31712b5ce5a44c9b5463121"><td class="memItemLeft" align="right" valign="top"><a id="ac4493e95b31712b5ce5a44c9b5463121"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ac4493e95b31712b5ce5a44c9b5463121">REG_DMAC_CHCTRLA19</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A170UL)</td></tr>
|
|
<tr class="memdesc:ac4493e95b31712b5ce5a44c9b5463121"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 19 Control A <br /></td></tr>
|
|
<tr class="separator:ac4493e95b31712b5ce5a44c9b5463121"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a8961eb5ac88d2ed6c6c700527baea83a"><td class="memItemLeft" align="right" valign="top"><a id="a8961eb5ac88d2ed6c6c700527baea83a"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a8961eb5ac88d2ed6c6c700527baea83a">REG_DMAC_CHCTRLB19</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A174UL)</td></tr>
|
|
<tr class="memdesc:a8961eb5ac88d2ed6c6c700527baea83a"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 19 Control B <br /></td></tr>
|
|
<tr class="separator:a8961eb5ac88d2ed6c6c700527baea83a"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a8aa412423e2194c34f4cb3909b5bc92d"><td class="memItemLeft" align="right" valign="top"><a id="a8aa412423e2194c34f4cb3909b5bc92d"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a8aa412423e2194c34f4cb3909b5bc92d">REG_DMAC_CHPRILVL19</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A175UL)</td></tr>
|
|
<tr class="memdesc:a8aa412423e2194c34f4cb3909b5bc92d"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 19 Priority Level <br /></td></tr>
|
|
<tr class="separator:a8aa412423e2194c34f4cb3909b5bc92d"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:adb06222ff877b35f7f89626e6004d47f"><td class="memItemLeft" align="right" valign="top"><a id="adb06222ff877b35f7f89626e6004d47f"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#adb06222ff877b35f7f89626e6004d47f">REG_DMAC_CHEVCTRL19</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A176UL)</td></tr>
|
|
<tr class="memdesc:adb06222ff877b35f7f89626e6004d47f"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 19 Event Control <br /></td></tr>
|
|
<tr class="separator:adb06222ff877b35f7f89626e6004d47f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:afdfb8b7aabeebd2915d719b35a1a115d"><td class="memItemLeft" align="right" valign="top"><a id="afdfb8b7aabeebd2915d719b35a1a115d"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#afdfb8b7aabeebd2915d719b35a1a115d">REG_DMAC_CHINTENCLR19</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A17CUL)</td></tr>
|
|
<tr class="memdesc:afdfb8b7aabeebd2915d719b35a1a115d"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 19 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:afdfb8b7aabeebd2915d719b35a1a115d"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a5caa3be6247bc085c16e2903865d20ae"><td class="memItemLeft" align="right" valign="top"><a id="a5caa3be6247bc085c16e2903865d20ae"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a5caa3be6247bc085c16e2903865d20ae">REG_DMAC_CHINTENSET19</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A17DUL)</td></tr>
|
|
<tr class="memdesc:a5caa3be6247bc085c16e2903865d20ae"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 19 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a5caa3be6247bc085c16e2903865d20ae"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a0b42234b10129d905c19f51f95ae3884"><td class="memItemLeft" align="right" valign="top"><a id="a0b42234b10129d905c19f51f95ae3884"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a0b42234b10129d905c19f51f95ae3884">REG_DMAC_CHINTFLAG19</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A17EUL)</td></tr>
|
|
<tr class="memdesc:a0b42234b10129d905c19f51f95ae3884"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 19 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a0b42234b10129d905c19f51f95ae3884"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:adb224ad6c381e2b805b928e162bee08d"><td class="memItemLeft" align="right" valign="top"><a id="adb224ad6c381e2b805b928e162bee08d"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#adb224ad6c381e2b805b928e162bee08d">REG_DMAC_CHSTATUS19</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A17FUL)</td></tr>
|
|
<tr class="memdesc:adb224ad6c381e2b805b928e162bee08d"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 19 Status <br /></td></tr>
|
|
<tr class="separator:adb224ad6c381e2b805b928e162bee08d"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3910cfece05b491de07bbc9d98aeb5f1"><td class="memItemLeft" align="right" valign="top"><a id="a3910cfece05b491de07bbc9d98aeb5f1"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3910cfece05b491de07bbc9d98aeb5f1">REG_DMAC_CHCTRLA20</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A180UL)</td></tr>
|
|
<tr class="memdesc:a3910cfece05b491de07bbc9d98aeb5f1"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 20 Control A <br /></td></tr>
|
|
<tr class="separator:a3910cfece05b491de07bbc9d98aeb5f1"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a8e1c138bb7cc3cbd3e9a934ea96820e9"><td class="memItemLeft" align="right" valign="top"><a id="a8e1c138bb7cc3cbd3e9a934ea96820e9"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a8e1c138bb7cc3cbd3e9a934ea96820e9">REG_DMAC_CHCTRLB20</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A184UL)</td></tr>
|
|
<tr class="memdesc:a8e1c138bb7cc3cbd3e9a934ea96820e9"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 20 Control B <br /></td></tr>
|
|
<tr class="separator:a8e1c138bb7cc3cbd3e9a934ea96820e9"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad3add1369fe02d5615e10d7dfcf966e1"><td class="memItemLeft" align="right" valign="top"><a id="ad3add1369fe02d5615e10d7dfcf966e1"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad3add1369fe02d5615e10d7dfcf966e1">REG_DMAC_CHPRILVL20</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A185UL)</td></tr>
|
|
<tr class="memdesc:ad3add1369fe02d5615e10d7dfcf966e1"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 20 Priority Level <br /></td></tr>
|
|
<tr class="separator:ad3add1369fe02d5615e10d7dfcf966e1"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a71aa86cdb3cee80a364cccdada3f4b26"><td class="memItemLeft" align="right" valign="top"><a id="a71aa86cdb3cee80a364cccdada3f4b26"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a71aa86cdb3cee80a364cccdada3f4b26">REG_DMAC_CHEVCTRL20</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A186UL)</td></tr>
|
|
<tr class="memdesc:a71aa86cdb3cee80a364cccdada3f4b26"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 20 Event Control <br /></td></tr>
|
|
<tr class="separator:a71aa86cdb3cee80a364cccdada3f4b26"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a5dae6496654006b5df22036de157578b"><td class="memItemLeft" align="right" valign="top"><a id="a5dae6496654006b5df22036de157578b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a5dae6496654006b5df22036de157578b">REG_DMAC_CHINTENCLR20</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A18CUL)</td></tr>
|
|
<tr class="memdesc:a5dae6496654006b5df22036de157578b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 20 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a5dae6496654006b5df22036de157578b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:abc2b9c70d7502ed82307bf9230932bac"><td class="memItemLeft" align="right" valign="top"><a id="abc2b9c70d7502ed82307bf9230932bac"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#abc2b9c70d7502ed82307bf9230932bac">REG_DMAC_CHINTENSET20</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A18DUL)</td></tr>
|
|
<tr class="memdesc:abc2b9c70d7502ed82307bf9230932bac"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 20 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:abc2b9c70d7502ed82307bf9230932bac"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af09e5f304d4f6fc491b898a11a6068c3"><td class="memItemLeft" align="right" valign="top"><a id="af09e5f304d4f6fc491b898a11a6068c3"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af09e5f304d4f6fc491b898a11a6068c3">REG_DMAC_CHINTFLAG20</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A18EUL)</td></tr>
|
|
<tr class="memdesc:af09e5f304d4f6fc491b898a11a6068c3"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 20 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:af09e5f304d4f6fc491b898a11a6068c3"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1063b716016505d8644c4d4445b6b8dd"><td class="memItemLeft" align="right" valign="top"><a id="a1063b716016505d8644c4d4445b6b8dd"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1063b716016505d8644c4d4445b6b8dd">REG_DMAC_CHSTATUS20</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A18FUL)</td></tr>
|
|
<tr class="memdesc:a1063b716016505d8644c4d4445b6b8dd"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 20 Status <br /></td></tr>
|
|
<tr class="separator:a1063b716016505d8644c4d4445b6b8dd"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a4e0cfe0296c19611396b4e3f144ba48b"><td class="memItemLeft" align="right" valign="top"><a id="a4e0cfe0296c19611396b4e3f144ba48b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a4e0cfe0296c19611396b4e3f144ba48b">REG_DMAC_CHCTRLA21</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A190UL)</td></tr>
|
|
<tr class="memdesc:a4e0cfe0296c19611396b4e3f144ba48b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 21 Control A <br /></td></tr>
|
|
<tr class="separator:a4e0cfe0296c19611396b4e3f144ba48b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a8f1fd7fa8069696ef674249525492d3f"><td class="memItemLeft" align="right" valign="top"><a id="a8f1fd7fa8069696ef674249525492d3f"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a8f1fd7fa8069696ef674249525492d3f">REG_DMAC_CHCTRLB21</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A194UL)</td></tr>
|
|
<tr class="memdesc:a8f1fd7fa8069696ef674249525492d3f"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 21 Control B <br /></td></tr>
|
|
<tr class="separator:a8f1fd7fa8069696ef674249525492d3f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a26a3ff08520d4f527938aa126c7a82da"><td class="memItemLeft" align="right" valign="top"><a id="a26a3ff08520d4f527938aa126c7a82da"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a26a3ff08520d4f527938aa126c7a82da">REG_DMAC_CHPRILVL21</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A195UL)</td></tr>
|
|
<tr class="memdesc:a26a3ff08520d4f527938aa126c7a82da"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 21 Priority Level <br /></td></tr>
|
|
<tr class="separator:a26a3ff08520d4f527938aa126c7a82da"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a8325fc5027206fe3c5495cb15006d518"><td class="memItemLeft" align="right" valign="top"><a id="a8325fc5027206fe3c5495cb15006d518"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a8325fc5027206fe3c5495cb15006d518">REG_DMAC_CHEVCTRL21</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A196UL)</td></tr>
|
|
<tr class="memdesc:a8325fc5027206fe3c5495cb15006d518"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 21 Event Control <br /></td></tr>
|
|
<tr class="separator:a8325fc5027206fe3c5495cb15006d518"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aaea58f5d75db78215da1591d264d4e8b"><td class="memItemLeft" align="right" valign="top"><a id="aaea58f5d75db78215da1591d264d4e8b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aaea58f5d75db78215da1591d264d4e8b">REG_DMAC_CHINTENCLR21</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A19CUL)</td></tr>
|
|
<tr class="memdesc:aaea58f5d75db78215da1591d264d4e8b"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 21 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:aaea58f5d75db78215da1591d264d4e8b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a07722d35fb7019fb1363a55988f83d0d"><td class="memItemLeft" align="right" valign="top"><a id="a07722d35fb7019fb1363a55988f83d0d"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a07722d35fb7019fb1363a55988f83d0d">REG_DMAC_CHINTENSET21</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A19DUL)</td></tr>
|
|
<tr class="memdesc:a07722d35fb7019fb1363a55988f83d0d"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 21 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a07722d35fb7019fb1363a55988f83d0d"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a14a78605d45793141984e0e7076a112d"><td class="memItemLeft" align="right" valign="top"><a id="a14a78605d45793141984e0e7076a112d"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a14a78605d45793141984e0e7076a112d">REG_DMAC_CHINTFLAG21</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A19EUL)</td></tr>
|
|
<tr class="memdesc:a14a78605d45793141984e0e7076a112d"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 21 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a14a78605d45793141984e0e7076a112d"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a2d6007d99ff29c6567749a255e2edfa8"><td class="memItemLeft" align="right" valign="top"><a id="a2d6007d99ff29c6567749a255e2edfa8"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a2d6007d99ff29c6567749a255e2edfa8">REG_DMAC_CHSTATUS21</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A19FUL)</td></tr>
|
|
<tr class="memdesc:a2d6007d99ff29c6567749a255e2edfa8"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 21 Status <br /></td></tr>
|
|
<tr class="separator:a2d6007d99ff29c6567749a255e2edfa8"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa0b72fed5a36b0960a7373578505b662"><td class="memItemLeft" align="right" valign="top"><a id="aa0b72fed5a36b0960a7373578505b662"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aa0b72fed5a36b0960a7373578505b662">REG_DMAC_CHCTRLA22</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A1A0UL)</td></tr>
|
|
<tr class="memdesc:aa0b72fed5a36b0960a7373578505b662"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 22 Control A <br /></td></tr>
|
|
<tr class="separator:aa0b72fed5a36b0960a7373578505b662"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a064f68afa05de8c07e555afe26bdb915"><td class="memItemLeft" align="right" valign="top"><a id="a064f68afa05de8c07e555afe26bdb915"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a064f68afa05de8c07e555afe26bdb915">REG_DMAC_CHCTRLB22</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1A4UL)</td></tr>
|
|
<tr class="memdesc:a064f68afa05de8c07e555afe26bdb915"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 22 Control B <br /></td></tr>
|
|
<tr class="separator:a064f68afa05de8c07e555afe26bdb915"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad4a6841bbfb3acc9c2a1f9bfd9a402a2"><td class="memItemLeft" align="right" valign="top"><a id="ad4a6841bbfb3acc9c2a1f9bfd9a402a2"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad4a6841bbfb3acc9c2a1f9bfd9a402a2">REG_DMAC_CHPRILVL22</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1A5UL)</td></tr>
|
|
<tr class="memdesc:ad4a6841bbfb3acc9c2a1f9bfd9a402a2"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 22 Priority Level <br /></td></tr>
|
|
<tr class="separator:ad4a6841bbfb3acc9c2a1f9bfd9a402a2"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a87a9ec83ad9538e8f8723abda7ccce62"><td class="memItemLeft" align="right" valign="top"><a id="a87a9ec83ad9538e8f8723abda7ccce62"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a87a9ec83ad9538e8f8723abda7ccce62">REG_DMAC_CHEVCTRL22</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1A6UL)</td></tr>
|
|
<tr class="memdesc:a87a9ec83ad9538e8f8723abda7ccce62"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 22 Event Control <br /></td></tr>
|
|
<tr class="separator:a87a9ec83ad9538e8f8723abda7ccce62"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ae973ae375dfbeac6dfb3c3ca626a322a"><td class="memItemLeft" align="right" valign="top"><a id="ae973ae375dfbeac6dfb3c3ca626a322a"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ae973ae375dfbeac6dfb3c3ca626a322a">REG_DMAC_CHINTENCLR22</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1ACUL)</td></tr>
|
|
<tr class="memdesc:ae973ae375dfbeac6dfb3c3ca626a322a"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 22 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:ae973ae375dfbeac6dfb3c3ca626a322a"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aae1625c31b0b75fbd439aeb24376709d"><td class="memItemLeft" align="right" valign="top"><a id="aae1625c31b0b75fbd439aeb24376709d"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aae1625c31b0b75fbd439aeb24376709d">REG_DMAC_CHINTENSET22</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1ADUL)</td></tr>
|
|
<tr class="memdesc:aae1625c31b0b75fbd439aeb24376709d"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 22 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:aae1625c31b0b75fbd439aeb24376709d"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a17ffc932ddcc7f2a8109b4aeb65f1ccc"><td class="memItemLeft" align="right" valign="top"><a id="a17ffc932ddcc7f2a8109b4aeb65f1ccc"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a17ffc932ddcc7f2a8109b4aeb65f1ccc">REG_DMAC_CHINTFLAG22</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1AEUL)</td></tr>
|
|
<tr class="memdesc:a17ffc932ddcc7f2a8109b4aeb65f1ccc"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 22 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a17ffc932ddcc7f2a8109b4aeb65f1ccc"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a5bf4a712e733f8f651fd75dbdd8e2ea0"><td class="memItemLeft" align="right" valign="top"><a id="a5bf4a712e733f8f651fd75dbdd8e2ea0"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a5bf4a712e733f8f651fd75dbdd8e2ea0">REG_DMAC_CHSTATUS22</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1AFUL)</td></tr>
|
|
<tr class="memdesc:a5bf4a712e733f8f651fd75dbdd8e2ea0"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 22 Status <br /></td></tr>
|
|
<tr class="separator:a5bf4a712e733f8f651fd75dbdd8e2ea0"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a0aaff99ddc6a232f8be7fcf6d94a379d"><td class="memItemLeft" align="right" valign="top"><a id="a0aaff99ddc6a232f8be7fcf6d94a379d"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a0aaff99ddc6a232f8be7fcf6d94a379d">REG_DMAC_CHCTRLA23</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A1B0UL)</td></tr>
|
|
<tr class="memdesc:a0aaff99ddc6a232f8be7fcf6d94a379d"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 23 Control A <br /></td></tr>
|
|
<tr class="separator:a0aaff99ddc6a232f8be7fcf6d94a379d"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad28603af4d7b50f36c1c5a475d0d9c29"><td class="memItemLeft" align="right" valign="top"><a id="ad28603af4d7b50f36c1c5a475d0d9c29"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad28603af4d7b50f36c1c5a475d0d9c29">REG_DMAC_CHCTRLB23</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1B4UL)</td></tr>
|
|
<tr class="memdesc:ad28603af4d7b50f36c1c5a475d0d9c29"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 23 Control B <br /></td></tr>
|
|
<tr class="separator:ad28603af4d7b50f36c1c5a475d0d9c29"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a8c33c357c145b11eb0d2ef648f480d23"><td class="memItemLeft" align="right" valign="top"><a id="a8c33c357c145b11eb0d2ef648f480d23"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a8c33c357c145b11eb0d2ef648f480d23">REG_DMAC_CHPRILVL23</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1B5UL)</td></tr>
|
|
<tr class="memdesc:a8c33c357c145b11eb0d2ef648f480d23"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 23 Priority Level <br /></td></tr>
|
|
<tr class="separator:a8c33c357c145b11eb0d2ef648f480d23"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a36af1abc9b3ad5d14d17c63fedb51466"><td class="memItemLeft" align="right" valign="top"><a id="a36af1abc9b3ad5d14d17c63fedb51466"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a36af1abc9b3ad5d14d17c63fedb51466">REG_DMAC_CHEVCTRL23</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1B6UL)</td></tr>
|
|
<tr class="memdesc:a36af1abc9b3ad5d14d17c63fedb51466"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 23 Event Control <br /></td></tr>
|
|
<tr class="separator:a36af1abc9b3ad5d14d17c63fedb51466"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a979daab958c28c15de8e513aec669bd3"><td class="memItemLeft" align="right" valign="top"><a id="a979daab958c28c15de8e513aec669bd3"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a979daab958c28c15de8e513aec669bd3">REG_DMAC_CHINTENCLR23</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1BCUL)</td></tr>
|
|
<tr class="memdesc:a979daab958c28c15de8e513aec669bd3"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 23 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a979daab958c28c15de8e513aec669bd3"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a599aaaffff56a79126e5673aeb70fe59"><td class="memItemLeft" align="right" valign="top"><a id="a599aaaffff56a79126e5673aeb70fe59"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a599aaaffff56a79126e5673aeb70fe59">REG_DMAC_CHINTENSET23</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1BDUL)</td></tr>
|
|
<tr class="memdesc:a599aaaffff56a79126e5673aeb70fe59"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 23 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a599aaaffff56a79126e5673aeb70fe59"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa6c3af080e0ad6e639fcaaa6e74a91e6"><td class="memItemLeft" align="right" valign="top"><a id="aa6c3af080e0ad6e639fcaaa6e74a91e6"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aa6c3af080e0ad6e639fcaaa6e74a91e6">REG_DMAC_CHINTFLAG23</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1BEUL)</td></tr>
|
|
<tr class="memdesc:aa6c3af080e0ad6e639fcaaa6e74a91e6"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 23 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:aa6c3af080e0ad6e639fcaaa6e74a91e6"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a44095fcbc05b5180d071d5a716fa5953"><td class="memItemLeft" align="right" valign="top"><a id="a44095fcbc05b5180d071d5a716fa5953"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a44095fcbc05b5180d071d5a716fa5953">REG_DMAC_CHSTATUS23</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1BFUL)</td></tr>
|
|
<tr class="memdesc:a44095fcbc05b5180d071d5a716fa5953"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 23 Status <br /></td></tr>
|
|
<tr class="separator:a44095fcbc05b5180d071d5a716fa5953"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3956abc6255dd8af328cba749eaad1ae"><td class="memItemLeft" align="right" valign="top"><a id="a3956abc6255dd8af328cba749eaad1ae"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3956abc6255dd8af328cba749eaad1ae">REG_DMAC_CHCTRLA24</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A1C0UL)</td></tr>
|
|
<tr class="memdesc:a3956abc6255dd8af328cba749eaad1ae"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 24 Control A <br /></td></tr>
|
|
<tr class="separator:a3956abc6255dd8af328cba749eaad1ae"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a5aea4b92029d6b723cc7ff0ffdf0d2ea"><td class="memItemLeft" align="right" valign="top"><a id="a5aea4b92029d6b723cc7ff0ffdf0d2ea"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a5aea4b92029d6b723cc7ff0ffdf0d2ea">REG_DMAC_CHCTRLB24</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1C4UL)</td></tr>
|
|
<tr class="memdesc:a5aea4b92029d6b723cc7ff0ffdf0d2ea"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 24 Control B <br /></td></tr>
|
|
<tr class="separator:a5aea4b92029d6b723cc7ff0ffdf0d2ea"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a07cfa37891f36bee8e7ae1afa15ecdb2"><td class="memItemLeft" align="right" valign="top"><a id="a07cfa37891f36bee8e7ae1afa15ecdb2"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a07cfa37891f36bee8e7ae1afa15ecdb2">REG_DMAC_CHPRILVL24</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1C5UL)</td></tr>
|
|
<tr class="memdesc:a07cfa37891f36bee8e7ae1afa15ecdb2"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 24 Priority Level <br /></td></tr>
|
|
<tr class="separator:a07cfa37891f36bee8e7ae1afa15ecdb2"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a53b8fbeca09f4ae7297b5e497c4d5dfa"><td class="memItemLeft" align="right" valign="top"><a id="a53b8fbeca09f4ae7297b5e497c4d5dfa"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a53b8fbeca09f4ae7297b5e497c4d5dfa">REG_DMAC_CHEVCTRL24</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1C6UL)</td></tr>
|
|
<tr class="memdesc:a53b8fbeca09f4ae7297b5e497c4d5dfa"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 24 Event Control <br /></td></tr>
|
|
<tr class="separator:a53b8fbeca09f4ae7297b5e497c4d5dfa"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a5ff36e37b244c07fee84efb5396b9b75"><td class="memItemLeft" align="right" valign="top"><a id="a5ff36e37b244c07fee84efb5396b9b75"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a5ff36e37b244c07fee84efb5396b9b75">REG_DMAC_CHINTENCLR24</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1CCUL)</td></tr>
|
|
<tr class="memdesc:a5ff36e37b244c07fee84efb5396b9b75"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 24 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a5ff36e37b244c07fee84efb5396b9b75"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a79a4ea62f5dd0a3f0a03889a060371de"><td class="memItemLeft" align="right" valign="top"><a id="a79a4ea62f5dd0a3f0a03889a060371de"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a79a4ea62f5dd0a3f0a03889a060371de">REG_DMAC_CHINTENSET24</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1CDUL)</td></tr>
|
|
<tr class="memdesc:a79a4ea62f5dd0a3f0a03889a060371de"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 24 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a79a4ea62f5dd0a3f0a03889a060371de"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a362a60b691a0d19987d0d2169454623f"><td class="memItemLeft" align="right" valign="top"><a id="a362a60b691a0d19987d0d2169454623f"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a362a60b691a0d19987d0d2169454623f">REG_DMAC_CHINTFLAG24</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1CEUL)</td></tr>
|
|
<tr class="memdesc:a362a60b691a0d19987d0d2169454623f"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 24 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a362a60b691a0d19987d0d2169454623f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a53cb1d6ff7261311224b2f2de99e09ea"><td class="memItemLeft" align="right" valign="top"><a id="a53cb1d6ff7261311224b2f2de99e09ea"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a53cb1d6ff7261311224b2f2de99e09ea">REG_DMAC_CHSTATUS24</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1CFUL)</td></tr>
|
|
<tr class="memdesc:a53cb1d6ff7261311224b2f2de99e09ea"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 24 Status <br /></td></tr>
|
|
<tr class="separator:a53cb1d6ff7261311224b2f2de99e09ea"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ac7bc20455dccf975b159aac9f53523a6"><td class="memItemLeft" align="right" valign="top"><a id="ac7bc20455dccf975b159aac9f53523a6"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ac7bc20455dccf975b159aac9f53523a6">REG_DMAC_CHCTRLA25</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A1D0UL)</td></tr>
|
|
<tr class="memdesc:ac7bc20455dccf975b159aac9f53523a6"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 25 Control A <br /></td></tr>
|
|
<tr class="separator:ac7bc20455dccf975b159aac9f53523a6"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a39b6b09c9e3e9b1efdbf6764904fe917"><td class="memItemLeft" align="right" valign="top"><a id="a39b6b09c9e3e9b1efdbf6764904fe917"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a39b6b09c9e3e9b1efdbf6764904fe917">REG_DMAC_CHCTRLB25</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1D4UL)</td></tr>
|
|
<tr class="memdesc:a39b6b09c9e3e9b1efdbf6764904fe917"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 25 Control B <br /></td></tr>
|
|
<tr class="separator:a39b6b09c9e3e9b1efdbf6764904fe917"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:adb367c636782b6bb87c1277c5b301332"><td class="memItemLeft" align="right" valign="top"><a id="adb367c636782b6bb87c1277c5b301332"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#adb367c636782b6bb87c1277c5b301332">REG_DMAC_CHPRILVL25</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1D5UL)</td></tr>
|
|
<tr class="memdesc:adb367c636782b6bb87c1277c5b301332"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 25 Priority Level <br /></td></tr>
|
|
<tr class="separator:adb367c636782b6bb87c1277c5b301332"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1dd0ca81e4184ed844bedd7519cb69ee"><td class="memItemLeft" align="right" valign="top"><a id="a1dd0ca81e4184ed844bedd7519cb69ee"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1dd0ca81e4184ed844bedd7519cb69ee">REG_DMAC_CHEVCTRL25</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1D6UL)</td></tr>
|
|
<tr class="memdesc:a1dd0ca81e4184ed844bedd7519cb69ee"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 25 Event Control <br /></td></tr>
|
|
<tr class="separator:a1dd0ca81e4184ed844bedd7519cb69ee"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a4d7287032bab19fef362cd983f15dc6a"><td class="memItemLeft" align="right" valign="top"><a id="a4d7287032bab19fef362cd983f15dc6a"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a4d7287032bab19fef362cd983f15dc6a">REG_DMAC_CHINTENCLR25</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1DCUL)</td></tr>
|
|
<tr class="memdesc:a4d7287032bab19fef362cd983f15dc6a"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 25 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a4d7287032bab19fef362cd983f15dc6a"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ae47c8e3bcfa549c3a58aa5d6d75995dd"><td class="memItemLeft" align="right" valign="top"><a id="ae47c8e3bcfa549c3a58aa5d6d75995dd"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ae47c8e3bcfa549c3a58aa5d6d75995dd">REG_DMAC_CHINTENSET25</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1DDUL)</td></tr>
|
|
<tr class="memdesc:ae47c8e3bcfa549c3a58aa5d6d75995dd"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 25 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:ae47c8e3bcfa549c3a58aa5d6d75995dd"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a5e96236b38280aad12cd4f70f4911032"><td class="memItemLeft" align="right" valign="top"><a id="a5e96236b38280aad12cd4f70f4911032"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a5e96236b38280aad12cd4f70f4911032">REG_DMAC_CHINTFLAG25</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1DEUL)</td></tr>
|
|
<tr class="memdesc:a5e96236b38280aad12cd4f70f4911032"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 25 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a5e96236b38280aad12cd4f70f4911032"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a0e8b23d371c31e89771172d04ef78ef5"><td class="memItemLeft" align="right" valign="top"><a id="a0e8b23d371c31e89771172d04ef78ef5"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a0e8b23d371c31e89771172d04ef78ef5">REG_DMAC_CHSTATUS25</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1DFUL)</td></tr>
|
|
<tr class="memdesc:a0e8b23d371c31e89771172d04ef78ef5"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 25 Status <br /></td></tr>
|
|
<tr class="separator:a0e8b23d371c31e89771172d04ef78ef5"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a160e7f1d7884212bbf8a685fb132f280"><td class="memItemLeft" align="right" valign="top"><a id="a160e7f1d7884212bbf8a685fb132f280"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a160e7f1d7884212bbf8a685fb132f280">REG_DMAC_CHCTRLA26</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A1E0UL)</td></tr>
|
|
<tr class="memdesc:a160e7f1d7884212bbf8a685fb132f280"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 26 Control A <br /></td></tr>
|
|
<tr class="separator:a160e7f1d7884212bbf8a685fb132f280"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a2c1243e83a63c92a6e5aa8272fcd7aaa"><td class="memItemLeft" align="right" valign="top"><a id="a2c1243e83a63c92a6e5aa8272fcd7aaa"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a2c1243e83a63c92a6e5aa8272fcd7aaa">REG_DMAC_CHCTRLB26</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1E4UL)</td></tr>
|
|
<tr class="memdesc:a2c1243e83a63c92a6e5aa8272fcd7aaa"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 26 Control B <br /></td></tr>
|
|
<tr class="separator:a2c1243e83a63c92a6e5aa8272fcd7aaa"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af48cb88f1eda30a4ae12393eff5d37d1"><td class="memItemLeft" align="right" valign="top"><a id="af48cb88f1eda30a4ae12393eff5d37d1"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af48cb88f1eda30a4ae12393eff5d37d1">REG_DMAC_CHPRILVL26</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1E5UL)</td></tr>
|
|
<tr class="memdesc:af48cb88f1eda30a4ae12393eff5d37d1"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 26 Priority Level <br /></td></tr>
|
|
<tr class="separator:af48cb88f1eda30a4ae12393eff5d37d1"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ac95264cf9a83da59560e57c5f001eb3c"><td class="memItemLeft" align="right" valign="top"><a id="ac95264cf9a83da59560e57c5f001eb3c"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ac95264cf9a83da59560e57c5f001eb3c">REG_DMAC_CHEVCTRL26</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1E6UL)</td></tr>
|
|
<tr class="memdesc:ac95264cf9a83da59560e57c5f001eb3c"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 26 Event Control <br /></td></tr>
|
|
<tr class="separator:ac95264cf9a83da59560e57c5f001eb3c"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ab2173120b5e25b46a8e7291ff40fe1a1"><td class="memItemLeft" align="right" valign="top"><a id="ab2173120b5e25b46a8e7291ff40fe1a1"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ab2173120b5e25b46a8e7291ff40fe1a1">REG_DMAC_CHINTENCLR26</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1ECUL)</td></tr>
|
|
<tr class="memdesc:ab2173120b5e25b46a8e7291ff40fe1a1"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 26 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:ab2173120b5e25b46a8e7291ff40fe1a1"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:acd901800f442acfef5ba890fc7936639"><td class="memItemLeft" align="right" valign="top"><a id="acd901800f442acfef5ba890fc7936639"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#acd901800f442acfef5ba890fc7936639">REG_DMAC_CHINTENSET26</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1EDUL)</td></tr>
|
|
<tr class="memdesc:acd901800f442acfef5ba890fc7936639"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 26 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:acd901800f442acfef5ba890fc7936639"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a4a5726926d993c9a79abc458e690de00"><td class="memItemLeft" align="right" valign="top"><a id="a4a5726926d993c9a79abc458e690de00"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a4a5726926d993c9a79abc458e690de00">REG_DMAC_CHINTFLAG26</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1EEUL)</td></tr>
|
|
<tr class="memdesc:a4a5726926d993c9a79abc458e690de00"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 26 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a4a5726926d993c9a79abc458e690de00"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ae8eca0e230020e3cb2c46ebcfea1f9a8"><td class="memItemLeft" align="right" valign="top"><a id="ae8eca0e230020e3cb2c46ebcfea1f9a8"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ae8eca0e230020e3cb2c46ebcfea1f9a8">REG_DMAC_CHSTATUS26</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1EFUL)</td></tr>
|
|
<tr class="memdesc:ae8eca0e230020e3cb2c46ebcfea1f9a8"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 26 Status <br /></td></tr>
|
|
<tr class="separator:ae8eca0e230020e3cb2c46ebcfea1f9a8"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a185fed21a7f490181e138e70c50489dc"><td class="memItemLeft" align="right" valign="top"><a id="a185fed21a7f490181e138e70c50489dc"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a185fed21a7f490181e138e70c50489dc">REG_DMAC_CHCTRLA27</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A1F0UL)</td></tr>
|
|
<tr class="memdesc:a185fed21a7f490181e138e70c50489dc"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 27 Control A <br /></td></tr>
|
|
<tr class="separator:a185fed21a7f490181e138e70c50489dc"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3b86bd9c17148a96977359c3bcf71fea"><td class="memItemLeft" align="right" valign="top"><a id="a3b86bd9c17148a96977359c3bcf71fea"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3b86bd9c17148a96977359c3bcf71fea">REG_DMAC_CHCTRLB27</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1F4UL)</td></tr>
|
|
<tr class="memdesc:a3b86bd9c17148a96977359c3bcf71fea"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 27 Control B <br /></td></tr>
|
|
<tr class="separator:a3b86bd9c17148a96977359c3bcf71fea"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:afe5c0fa2a7ad932f8078f4f28a44bd92"><td class="memItemLeft" align="right" valign="top"><a id="afe5c0fa2a7ad932f8078f4f28a44bd92"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#afe5c0fa2a7ad932f8078f4f28a44bd92">REG_DMAC_CHPRILVL27</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1F5UL)</td></tr>
|
|
<tr class="memdesc:afe5c0fa2a7ad932f8078f4f28a44bd92"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 27 Priority Level <br /></td></tr>
|
|
<tr class="separator:afe5c0fa2a7ad932f8078f4f28a44bd92"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aeb14867c10f89f0faa10f3ea1b8732e0"><td class="memItemLeft" align="right" valign="top"><a id="aeb14867c10f89f0faa10f3ea1b8732e0"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aeb14867c10f89f0faa10f3ea1b8732e0">REG_DMAC_CHEVCTRL27</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1F6UL)</td></tr>
|
|
<tr class="memdesc:aeb14867c10f89f0faa10f3ea1b8732e0"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 27 Event Control <br /></td></tr>
|
|
<tr class="separator:aeb14867c10f89f0faa10f3ea1b8732e0"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1587fc1949a46afcf6b4aa5bd803c28d"><td class="memItemLeft" align="right" valign="top"><a id="a1587fc1949a46afcf6b4aa5bd803c28d"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1587fc1949a46afcf6b4aa5bd803c28d">REG_DMAC_CHINTENCLR27</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1FCUL)</td></tr>
|
|
<tr class="memdesc:a1587fc1949a46afcf6b4aa5bd803c28d"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 27 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a1587fc1949a46afcf6b4aa5bd803c28d"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ac03a9f66acedef77626f9d6f31123920"><td class="memItemLeft" align="right" valign="top"><a id="ac03a9f66acedef77626f9d6f31123920"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ac03a9f66acedef77626f9d6f31123920">REG_DMAC_CHINTENSET27</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1FDUL)</td></tr>
|
|
<tr class="memdesc:ac03a9f66acedef77626f9d6f31123920"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 27 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:ac03a9f66acedef77626f9d6f31123920"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a201e37dd65ef3dd87507397cbd4ed134"><td class="memItemLeft" align="right" valign="top"><a id="a201e37dd65ef3dd87507397cbd4ed134"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a201e37dd65ef3dd87507397cbd4ed134">REG_DMAC_CHINTFLAG27</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1FEUL)</td></tr>
|
|
<tr class="memdesc:a201e37dd65ef3dd87507397cbd4ed134"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 27 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:a201e37dd65ef3dd87507397cbd4ed134"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3d77785b18847bba9388fd4db284f888"><td class="memItemLeft" align="right" valign="top"><a id="a3d77785b18847bba9388fd4db284f888"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a3d77785b18847bba9388fd4db284f888">REG_DMAC_CHSTATUS27</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A1FFUL)</td></tr>
|
|
<tr class="memdesc:a3d77785b18847bba9388fd4db284f888"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 27 Status <br /></td></tr>
|
|
<tr class="separator:a3d77785b18847bba9388fd4db284f888"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1255508cbdcb8345dd4aaef74e719115"><td class="memItemLeft" align="right" valign="top"><a id="a1255508cbdcb8345dd4aaef74e719115"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1255508cbdcb8345dd4aaef74e719115">REG_DMAC_CHCTRLA28</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A200UL)</td></tr>
|
|
<tr class="memdesc:a1255508cbdcb8345dd4aaef74e719115"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 28 Control A <br /></td></tr>
|
|
<tr class="separator:a1255508cbdcb8345dd4aaef74e719115"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a2b5b012ba6cc1158dd15ddecef20a6d9"><td class="memItemLeft" align="right" valign="top"><a id="a2b5b012ba6cc1158dd15ddecef20a6d9"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a2b5b012ba6cc1158dd15ddecef20a6d9">REG_DMAC_CHCTRLB28</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A204UL)</td></tr>
|
|
<tr class="memdesc:a2b5b012ba6cc1158dd15ddecef20a6d9"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 28 Control B <br /></td></tr>
|
|
<tr class="separator:a2b5b012ba6cc1158dd15ddecef20a6d9"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a5106e1e5e8c52b4fe0d28ac8a8da16f5"><td class="memItemLeft" align="right" valign="top"><a id="a5106e1e5e8c52b4fe0d28ac8a8da16f5"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a5106e1e5e8c52b4fe0d28ac8a8da16f5">REG_DMAC_CHPRILVL28</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A205UL)</td></tr>
|
|
<tr class="memdesc:a5106e1e5e8c52b4fe0d28ac8a8da16f5"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 28 Priority Level <br /></td></tr>
|
|
<tr class="separator:a5106e1e5e8c52b4fe0d28ac8a8da16f5"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a4bbe4aa2d30e257a6c10f09e49247385"><td class="memItemLeft" align="right" valign="top"><a id="a4bbe4aa2d30e257a6c10f09e49247385"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a4bbe4aa2d30e257a6c10f09e49247385">REG_DMAC_CHEVCTRL28</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A206UL)</td></tr>
|
|
<tr class="memdesc:a4bbe4aa2d30e257a6c10f09e49247385"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 28 Event Control <br /></td></tr>
|
|
<tr class="separator:a4bbe4aa2d30e257a6c10f09e49247385"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1a02dbbb358de39e7ac7f993745b3f23"><td class="memItemLeft" align="right" valign="top"><a id="a1a02dbbb358de39e7ac7f993745b3f23"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a1a02dbbb358de39e7ac7f993745b3f23">REG_DMAC_CHINTENCLR28</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A20CUL)</td></tr>
|
|
<tr class="memdesc:a1a02dbbb358de39e7ac7f993745b3f23"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 28 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a1a02dbbb358de39e7ac7f993745b3f23"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:acec08e14c3d0d10d277eb5e44b87f266"><td class="memItemLeft" align="right" valign="top"><a id="acec08e14c3d0d10d277eb5e44b87f266"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#acec08e14c3d0d10d277eb5e44b87f266">REG_DMAC_CHINTENSET28</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A20DUL)</td></tr>
|
|
<tr class="memdesc:acec08e14c3d0d10d277eb5e44b87f266"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 28 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:acec08e14c3d0d10d277eb5e44b87f266"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ae98c7946545af2b333e25a72cda827ef"><td class="memItemLeft" align="right" valign="top"><a id="ae98c7946545af2b333e25a72cda827ef"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ae98c7946545af2b333e25a72cda827ef">REG_DMAC_CHINTFLAG28</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A20EUL)</td></tr>
|
|
<tr class="memdesc:ae98c7946545af2b333e25a72cda827ef"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 28 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:ae98c7946545af2b333e25a72cda827ef"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a09bb6991dbcf5f896656bb804315d97e"><td class="memItemLeft" align="right" valign="top"><a id="a09bb6991dbcf5f896656bb804315d97e"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a09bb6991dbcf5f896656bb804315d97e">REG_DMAC_CHSTATUS28</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A20FUL)</td></tr>
|
|
<tr class="memdesc:a09bb6991dbcf5f896656bb804315d97e"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 28 Status <br /></td></tr>
|
|
<tr class="separator:a09bb6991dbcf5f896656bb804315d97e"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a044d6b97b91cd8fe4ad5dcb5b28f2b75"><td class="memItemLeft" align="right" valign="top"><a id="a044d6b97b91cd8fe4ad5dcb5b28f2b75"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a044d6b97b91cd8fe4ad5dcb5b28f2b75">REG_DMAC_CHCTRLA29</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A210UL)</td></tr>
|
|
<tr class="memdesc:a044d6b97b91cd8fe4ad5dcb5b28f2b75"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 29 Control A <br /></td></tr>
|
|
<tr class="separator:a044d6b97b91cd8fe4ad5dcb5b28f2b75"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a2ca341ea0d1c368ac081f754d8c30a33"><td class="memItemLeft" align="right" valign="top"><a id="a2ca341ea0d1c368ac081f754d8c30a33"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a2ca341ea0d1c368ac081f754d8c30a33">REG_DMAC_CHCTRLB29</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A214UL)</td></tr>
|
|
<tr class="memdesc:a2ca341ea0d1c368ac081f754d8c30a33"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 29 Control B <br /></td></tr>
|
|
<tr class="separator:a2ca341ea0d1c368ac081f754d8c30a33"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a28a3d118ba7378b218918d4c7fe6a8e8"><td class="memItemLeft" align="right" valign="top"><a id="a28a3d118ba7378b218918d4c7fe6a8e8"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a28a3d118ba7378b218918d4c7fe6a8e8">REG_DMAC_CHPRILVL29</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A215UL)</td></tr>
|
|
<tr class="memdesc:a28a3d118ba7378b218918d4c7fe6a8e8"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 29 Priority Level <br /></td></tr>
|
|
<tr class="separator:a28a3d118ba7378b218918d4c7fe6a8e8"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a92a86fe6512c13f51bfc55bed445e8f9"><td class="memItemLeft" align="right" valign="top"><a id="a92a86fe6512c13f51bfc55bed445e8f9"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a92a86fe6512c13f51bfc55bed445e8f9">REG_DMAC_CHEVCTRL29</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A216UL)</td></tr>
|
|
<tr class="memdesc:a92a86fe6512c13f51bfc55bed445e8f9"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 29 Event Control <br /></td></tr>
|
|
<tr class="separator:a92a86fe6512c13f51bfc55bed445e8f9"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a0956546c6dde5404ed34ff8f765ec4c8"><td class="memItemLeft" align="right" valign="top"><a id="a0956546c6dde5404ed34ff8f765ec4c8"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a0956546c6dde5404ed34ff8f765ec4c8">REG_DMAC_CHINTENCLR29</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A21CUL)</td></tr>
|
|
<tr class="memdesc:a0956546c6dde5404ed34ff8f765ec4c8"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 29 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a0956546c6dde5404ed34ff8f765ec4c8"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a42891db63b874743d1dfec1011c3aad5"><td class="memItemLeft" align="right" valign="top"><a id="a42891db63b874743d1dfec1011c3aad5"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a42891db63b874743d1dfec1011c3aad5">REG_DMAC_CHINTENSET29</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A21DUL)</td></tr>
|
|
<tr class="memdesc:a42891db63b874743d1dfec1011c3aad5"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 29 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a42891db63b874743d1dfec1011c3aad5"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af9bb002706ccc6b7456651001f090214"><td class="memItemLeft" align="right" valign="top"><a id="af9bb002706ccc6b7456651001f090214"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af9bb002706ccc6b7456651001f090214">REG_DMAC_CHINTFLAG29</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A21EUL)</td></tr>
|
|
<tr class="memdesc:af9bb002706ccc6b7456651001f090214"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 29 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:af9bb002706ccc6b7456651001f090214"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:acd7147bbd8878b8ac3ef21d380746cae"><td class="memItemLeft" align="right" valign="top"><a id="acd7147bbd8878b8ac3ef21d380746cae"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#acd7147bbd8878b8ac3ef21d380746cae">REG_DMAC_CHSTATUS29</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A21FUL)</td></tr>
|
|
<tr class="memdesc:acd7147bbd8878b8ac3ef21d380746cae"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 29 Status <br /></td></tr>
|
|
<tr class="separator:acd7147bbd8878b8ac3ef21d380746cae"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad58b044333c585073d01821cc58541e0"><td class="memItemLeft" align="right" valign="top"><a id="ad58b044333c585073d01821cc58541e0"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad58b044333c585073d01821cc58541e0">REG_DMAC_CHCTRLA30</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A220UL)</td></tr>
|
|
<tr class="memdesc:ad58b044333c585073d01821cc58541e0"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 30 Control A <br /></td></tr>
|
|
<tr class="separator:ad58b044333c585073d01821cc58541e0"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a28269161846d3f3a7a25051e6277f310"><td class="memItemLeft" align="right" valign="top"><a id="a28269161846d3f3a7a25051e6277f310"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a28269161846d3f3a7a25051e6277f310">REG_DMAC_CHCTRLB30</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A224UL)</td></tr>
|
|
<tr class="memdesc:a28269161846d3f3a7a25051e6277f310"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 30 Control B <br /></td></tr>
|
|
<tr class="separator:a28269161846d3f3a7a25051e6277f310"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a826f585d6f630e02c698eb63462ded08"><td class="memItemLeft" align="right" valign="top"><a id="a826f585d6f630e02c698eb63462ded08"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a826f585d6f630e02c698eb63462ded08">REG_DMAC_CHPRILVL30</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A225UL)</td></tr>
|
|
<tr class="memdesc:a826f585d6f630e02c698eb63462ded08"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 30 Priority Level <br /></td></tr>
|
|
<tr class="separator:a826f585d6f630e02c698eb63462ded08"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa51fc0d01c0e3fb210f9291ecd231460"><td class="memItemLeft" align="right" valign="top"><a id="aa51fc0d01c0e3fb210f9291ecd231460"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aa51fc0d01c0e3fb210f9291ecd231460">REG_DMAC_CHEVCTRL30</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A226UL)</td></tr>
|
|
<tr class="memdesc:aa51fc0d01c0e3fb210f9291ecd231460"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 30 Event Control <br /></td></tr>
|
|
<tr class="separator:aa51fc0d01c0e3fb210f9291ecd231460"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af4947446eccedd9954b47cddb954f07a"><td class="memItemLeft" align="right" valign="top"><a id="af4947446eccedd9954b47cddb954f07a"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af4947446eccedd9954b47cddb954f07a">REG_DMAC_CHINTENCLR30</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A22CUL)</td></tr>
|
|
<tr class="memdesc:af4947446eccedd9954b47cddb954f07a"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 30 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:af4947446eccedd9954b47cddb954f07a"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a83104853ac9ee4ad8d02c205cd6276b3"><td class="memItemLeft" align="right" valign="top"><a id="a83104853ac9ee4ad8d02c205cd6276b3"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a83104853ac9ee4ad8d02c205cd6276b3">REG_DMAC_CHINTENSET30</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A22DUL)</td></tr>
|
|
<tr class="memdesc:a83104853ac9ee4ad8d02c205cd6276b3"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 30 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:a83104853ac9ee4ad8d02c205cd6276b3"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af8b10e0cc69f94619f519626e67e9e9e"><td class="memItemLeft" align="right" valign="top"><a id="af8b10e0cc69f94619f519626e67e9e9e"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af8b10e0cc69f94619f519626e67e9e9e">REG_DMAC_CHINTFLAG30</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A22EUL)</td></tr>
|
|
<tr class="memdesc:af8b10e0cc69f94619f519626e67e9e9e"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 30 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:af8b10e0cc69f94619f519626e67e9e9e"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:afcd7207a7507da28d044d24d0fbca427"><td class="memItemLeft" align="right" valign="top"><a id="afcd7207a7507da28d044d24d0fbca427"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#afcd7207a7507da28d044d24d0fbca427">REG_DMAC_CHSTATUS30</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A22FUL)</td></tr>
|
|
<tr class="memdesc:afcd7207a7507da28d044d24d0fbca427"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 30 Status <br /></td></tr>
|
|
<tr class="separator:afcd7207a7507da28d044d24d0fbca427"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a923cceb51d0516467dc1413a472ab695"><td class="memItemLeft" align="right" valign="top"><a id="a923cceb51d0516467dc1413a472ab695"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a923cceb51d0516467dc1413a472ab695">REG_DMAC_CHCTRLA31</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100A230UL)</td></tr>
|
|
<tr class="memdesc:a923cceb51d0516467dc1413a472ab695"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 31 Control A <br /></td></tr>
|
|
<tr class="separator:a923cceb51d0516467dc1413a472ab695"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a85e455dd2d58136e5d8f0c00220adca3"><td class="memItemLeft" align="right" valign="top"><a id="a85e455dd2d58136e5d8f0c00220adca3"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a85e455dd2d58136e5d8f0c00220adca3">REG_DMAC_CHCTRLB31</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A234UL)</td></tr>
|
|
<tr class="memdesc:a85e455dd2d58136e5d8f0c00220adca3"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 31 Control B <br /></td></tr>
|
|
<tr class="separator:a85e455dd2d58136e5d8f0c00220adca3"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af085cca270c00acc1f93a77f5c2c326f"><td class="memItemLeft" align="right" valign="top"><a id="af085cca270c00acc1f93a77f5c2c326f"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#af085cca270c00acc1f93a77f5c2c326f">REG_DMAC_CHPRILVL31</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A235UL)</td></tr>
|
|
<tr class="memdesc:af085cca270c00acc1f93a77f5c2c326f"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 31 Priority Level <br /></td></tr>
|
|
<tr class="separator:af085cca270c00acc1f93a77f5c2c326f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa13b886418aeef3ad1f7fc5ac44f9dac"><td class="memItemLeft" align="right" valign="top"><a id="aa13b886418aeef3ad1f7fc5ac44f9dac"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aa13b886418aeef3ad1f7fc5ac44f9dac">REG_DMAC_CHEVCTRL31</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A236UL)</td></tr>
|
|
<tr class="memdesc:aa13b886418aeef3ad1f7fc5ac44f9dac"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 31 Event Control <br /></td></tr>
|
|
<tr class="separator:aa13b886418aeef3ad1f7fc5ac44f9dac"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a14a835c32ed2ccbe860d16673c25fb31"><td class="memItemLeft" align="right" valign="top"><a id="a14a835c32ed2ccbe860d16673c25fb31"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#a14a835c32ed2ccbe860d16673c25fb31">REG_DMAC_CHINTENCLR31</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A23CUL)</td></tr>
|
|
<tr class="memdesc:a14a835c32ed2ccbe860d16673c25fb31"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 31 Interrupt Enable Clear <br /></td></tr>
|
|
<tr class="separator:a14a835c32ed2ccbe860d16673c25fb31"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ad25c2f0e5c0a1928cd801e49c3c9a307"><td class="memItemLeft" align="right" valign="top"><a id="ad25c2f0e5c0a1928cd801e49c3c9a307"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ad25c2f0e5c0a1928cd801e49c3c9a307">REG_DMAC_CHINTENSET31</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A23DUL)</td></tr>
|
|
<tr class="memdesc:ad25c2f0e5c0a1928cd801e49c3c9a307"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 31 Interrupt Enable Set <br /></td></tr>
|
|
<tr class="separator:ad25c2f0e5c0a1928cd801e49c3c9a307"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa1ea3320ad8ddf27371de000eb613ce7"><td class="memItemLeft" align="right" valign="top"><a id="aa1ea3320ad8ddf27371de000eb613ce7"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#aa1ea3320ad8ddf27371de000eb613ce7">REG_DMAC_CHINTFLAG31</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A23EUL)</td></tr>
|
|
<tr class="memdesc:aa1ea3320ad8ddf27371de000eb613ce7"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 31 Interrupt Flag Status and Clear <br /></td></tr>
|
|
<tr class="separator:aa1ea3320ad8ddf27371de000eb613ce7"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ac0e3a9d969b18fe320cfe819791d43ec"><td class="memItemLeft" align="right" valign="top"><a id="ac0e3a9d969b18fe320cfe819791d43ec"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2dmac_8h.html#ac0e3a9d969b18fe320cfe819791d43ec">REG_DMAC_CHSTATUS31</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4100A23FUL)</td></tr>
|
|
<tr class="memdesc:ac0e3a9d969b18fe320cfe819791d43ec"><td class="mdescLeft"> </td><td class="mdescRight">(DMAC) Channel 31 Status <br /></td></tr>
|
|
<tr class="separator:ac0e3a9d969b18fe320cfe819791d43ec"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a0af6bf6f5cd3bd1ac736b7293204b9a2"><td class="memItemLeft" align="right" valign="top"><a id="a0af6bf6f5cd3bd1ac736b7293204b9a2"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_BURST</b>   1</td></tr>
|
|
<tr class="separator:a0af6bf6f5cd3bd1ac736b7293204b9a2"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a0e93a207de1fa434f262783124252acb"><td class="memItemLeft" align="right" valign="top"><a id="a0e93a207de1fa434f262783124252acb"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_CH_BITS</b>   5</td></tr>
|
|
<tr class="separator:a0e93a207de1fa434f262783124252acb"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ade11822cddf9a0e802e0b682db3aa46c"><td class="memItemLeft" align="right" valign="top"><a id="ade11822cddf9a0e802e0b682db3aa46c"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_CH_NUM</b>   32</td></tr>
|
|
<tr class="separator:ade11822cddf9a0e802e0b682db3aa46c"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a444fdc03c0f28fb3bfb69b2ed08fc2ab"><td class="memItemLeft" align="right" valign="top"><a id="a444fdc03c0f28fb3bfb69b2ed08fc2ab"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_CLK_AHB_ID</b>   9</td></tr>
|
|
<tr class="separator:a444fdc03c0f28fb3bfb69b2ed08fc2ab"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ada99bcab97299ac1de783300eb5208f6"><td class="memItemLeft" align="right" valign="top"><a id="ada99bcab97299ac1de783300eb5208f6"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_EVIN_NUM</b>   8</td></tr>
|
|
<tr class="separator:ada99bcab97299ac1de783300eb5208f6"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa66315110f2acc89d9ba40c7993fab9f"><td class="memItemLeft" align="right" valign="top"><a id="aa66315110f2acc89d9ba40c7993fab9f"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_EVOUT_NUM</b>   4</td></tr>
|
|
<tr class="separator:aa66315110f2acc89d9ba40c7993fab9f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a94037eb9082071bca008b217af0f3709"><td class="memItemLeft" align="right" valign="top"><a id="a94037eb9082071bca008b217af0f3709"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_FIFO_SIZE</b>   16</td></tr>
|
|
<tr class="separator:a94037eb9082071bca008b217af0f3709"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a02dea64f357a290b2e1631050646c615"><td class="memItemLeft" align="right" valign="top"><a id="a02dea64f357a290b2e1631050646c615"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_LVL_BITS</b>   2</td></tr>
|
|
<tr class="separator:a02dea64f357a290b2e1631050646c615"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a7b9fc9815bb91dc84d0db567a7dd64cb"><td class="memItemLeft" align="right" valign="top"><a id="a7b9fc9815bb91dc84d0db567a7dd64cb"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_LVL_NUM</b>   4</td></tr>
|
|
<tr class="separator:a7b9fc9815bb91dc84d0db567a7dd64cb"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a4637e06c214b02ce1aeb03bb305fd386"><td class="memItemLeft" align="right" valign="top"><a id="a4637e06c214b02ce1aeb03bb305fd386"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_QOSCTRL_D_RESETVALUE</b>   2</td></tr>
|
|
<tr class="separator:a4637e06c214b02ce1aeb03bb305fd386"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a1bdcc4dfaac65aa9ea49721fddf69519"><td class="memItemLeft" align="right" valign="top"><a id="a1bdcc4dfaac65aa9ea49721fddf69519"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_QOSCTRL_F_RESETVALUE</b>   2</td></tr>
|
|
<tr class="separator:a1bdcc4dfaac65aa9ea49721fddf69519"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ae26d474e731d9bafb63bb73b3f7c119b"><td class="memItemLeft" align="right" valign="top"><a id="ae26d474e731d9bafb63bb73b3f7c119b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_QOSCTRL_WRB_RESETVALUE</b>   2</td></tr>
|
|
<tr class="separator:ae26d474e731d9bafb63bb73b3f7c119b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aece2afc0b93585d225d07db21716df1a"><td class="memItemLeft" align="right" valign="top"><a id="aece2afc0b93585d225d07db21716df1a"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_TRIG_BITS</b>   7</td></tr>
|
|
<tr class="separator:aece2afc0b93585d225d07db21716df1a"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a4970c3fcb0da9b536366734676c1925b"><td class="memItemLeft" align="right" valign="top"><a id="a4970c3fcb0da9b536366734676c1925b"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><b>DMAC_TRIG_NUM</b>   85</td></tr>
|
|
<tr class="separator:a4970c3fcb0da9b536366734676c1925b"><td class="memSeparator" colspan="2"> </td></tr>
|
|
</table>
|
|
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
|
|
<div class="textblock"><p>Instance description for DMAC. </p>
|
|
<p>Copyright (c) 2019 Microchip Technology Inc.</p>
|
|
<p>\asf_license_start </p>
|
|
|
|
<p class="definition">Definition in file <a class="el" href="instance_2dmac_8h_source.html">dmac.h</a>.</p>
|
|
</div></div><!-- contents -->
|
|
<!-- start footer part -->
|
|
<hr class="footer"/><address class="footer"><small>
|
|
Generated by <a href="http://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.8.20
|
|
</small></address>
|
|
</body>
|
|
</html>
|