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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/cmcc.h File Reference</title>
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<div id="projectname">SAME54P20A Test Project
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<a href="#define-members">Macros</a> </div>
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<div class="title">cmcc.h File Reference</div> </div>
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<div class="contents">
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<p>Instance description for CMCC.
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<a href="#details">More...</a></p>
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<p><a href="instance_2cmcc_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a6829522d87b10ee63febc5aac35b37c1"><td class="memItemLeft" align="right" valign="top"><a id="a6829522d87b10ee63febc5aac35b37c1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2cmcc_8h.html#a6829522d87b10ee63febc5aac35b37c1">REG_CMCC_TYPE</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41006000UL)</td></tr>
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<tr class="memdesc:a6829522d87b10ee63febc5aac35b37c1"><td class="mdescLeft"> </td><td class="mdescRight">(CMCC) Cache Type Register <br /></td></tr>
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<tr class="separator:a6829522d87b10ee63febc5aac35b37c1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4b323104c4623f6fe1d6df8f97648f5"><td class="memItemLeft" align="right" valign="top"><a id="ab4b323104c4623f6fe1d6df8f97648f5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2cmcc_8h.html#ab4b323104c4623f6fe1d6df8f97648f5">REG_CMCC_CFG</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41006004UL)</td></tr>
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<tr class="memdesc:ab4b323104c4623f6fe1d6df8f97648f5"><td class="mdescLeft"> </td><td class="mdescRight">(CMCC) Cache Configuration Register <br /></td></tr>
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<tr class="separator:ab4b323104c4623f6fe1d6df8f97648f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d8eaa69c8b42a85b9c65f6160a5b09e"><td class="memItemLeft" align="right" valign="top"><a id="a2d8eaa69c8b42a85b9c65f6160a5b09e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2cmcc_8h.html#a2d8eaa69c8b42a85b9c65f6160a5b09e">REG_CMCC_CTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ac0f96d4e8018367b38f527007cf0eafd">WoReg</a> *)0x41006008UL)</td></tr>
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<tr class="memdesc:a2d8eaa69c8b42a85b9c65f6160a5b09e"><td class="mdescLeft"> </td><td class="mdescRight">(CMCC) Cache Control Register <br /></td></tr>
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<tr class="separator:a2d8eaa69c8b42a85b9c65f6160a5b09e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad1cb993f76e36df88c27ed3d467b4446"><td class="memItemLeft" align="right" valign="top"><a id="ad1cb993f76e36df88c27ed3d467b4446"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2cmcc_8h.html#ad1cb993f76e36df88c27ed3d467b4446">REG_CMCC_SR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4100600CUL)</td></tr>
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<tr class="memdesc:ad1cb993f76e36df88c27ed3d467b4446"><td class="mdescLeft"> </td><td class="mdescRight">(CMCC) Cache Status Register <br /></td></tr>
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<tr class="separator:ad1cb993f76e36df88c27ed3d467b4446"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a63e0af529de55811896bbb1294009d68"><td class="memItemLeft" align="right" valign="top"><a id="a63e0af529de55811896bbb1294009d68"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2cmcc_8h.html#a63e0af529de55811896bbb1294009d68">REG_CMCC_LCKWAY</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41006010UL)</td></tr>
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<tr class="memdesc:a63e0af529de55811896bbb1294009d68"><td class="mdescLeft"> </td><td class="mdescRight">(CMCC) Cache Lock per Way Register <br /></td></tr>
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<tr class="separator:a63e0af529de55811896bbb1294009d68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adff2eaa36e509f365d9068c1482c782e"><td class="memItemLeft" align="right" valign="top"><a id="adff2eaa36e509f365d9068c1482c782e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2cmcc_8h.html#adff2eaa36e509f365d9068c1482c782e">REG_CMCC_MAINT0</a>   (*(<a class="el" href="same54n19a_8h.html#ac0f96d4e8018367b38f527007cf0eafd">WoReg</a> *)0x41006020UL)</td></tr>
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<tr class="memdesc:adff2eaa36e509f365d9068c1482c782e"><td class="mdescLeft"> </td><td class="mdescRight">(CMCC) Cache Maintenance Register 0 <br /></td></tr>
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<tr class="separator:adff2eaa36e509f365d9068c1482c782e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae83e89aeab0242be876eb6308f94a627"><td class="memItemLeft" align="right" valign="top"><a id="ae83e89aeab0242be876eb6308f94a627"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2cmcc_8h.html#ae83e89aeab0242be876eb6308f94a627">REG_CMCC_MAINT1</a>   (*(<a class="el" href="same54n19a_8h.html#ac0f96d4e8018367b38f527007cf0eafd">WoReg</a> *)0x41006024UL)</td></tr>
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<tr class="memdesc:ae83e89aeab0242be876eb6308f94a627"><td class="mdescLeft"> </td><td class="mdescRight">(CMCC) Cache Maintenance Register 1 <br /></td></tr>
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<tr class="separator:ae83e89aeab0242be876eb6308f94a627"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a61129c019241c5d18b8632760d18c96a"><td class="memItemLeft" align="right" valign="top"><a id="a61129c019241c5d18b8632760d18c96a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2cmcc_8h.html#a61129c019241c5d18b8632760d18c96a">REG_CMCC_MCFG</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41006028UL)</td></tr>
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<tr class="memdesc:a61129c019241c5d18b8632760d18c96a"><td class="mdescLeft"> </td><td class="mdescRight">(CMCC) Cache Monitor Configuration Register <br /></td></tr>
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<tr class="separator:a61129c019241c5d18b8632760d18c96a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9270e689f2f63e410ec1bb5700f3388b"><td class="memItemLeft" align="right" valign="top"><a id="a9270e689f2f63e410ec1bb5700f3388b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2cmcc_8h.html#a9270e689f2f63e410ec1bb5700f3388b">REG_CMCC_MEN</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4100602CUL)</td></tr>
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<tr class="memdesc:a9270e689f2f63e410ec1bb5700f3388b"><td class="mdescLeft"> </td><td class="mdescRight">(CMCC) Cache Monitor Enable Register <br /></td></tr>
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<tr class="separator:a9270e689f2f63e410ec1bb5700f3388b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7a96dd2192a0b517a2726c7c41c6705c"><td class="memItemLeft" align="right" valign="top"><a id="a7a96dd2192a0b517a2726c7c41c6705c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2cmcc_8h.html#a7a96dd2192a0b517a2726c7c41c6705c">REG_CMCC_MCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ac0f96d4e8018367b38f527007cf0eafd">WoReg</a> *)0x41006030UL)</td></tr>
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<tr class="memdesc:a7a96dd2192a0b517a2726c7c41c6705c"><td class="mdescLeft"> </td><td class="mdescRight">(CMCC) Cache Monitor Control Register <br /></td></tr>
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<tr class="separator:a7a96dd2192a0b517a2726c7c41c6705c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a83a44a1c2b4c996886722068ff359d8f"><td class="memItemLeft" align="right" valign="top"><a id="a83a44a1c2b4c996886722068ff359d8f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2cmcc_8h.html#a83a44a1c2b4c996886722068ff359d8f">REG_CMCC_MSR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x41006034UL)</td></tr>
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<tr class="memdesc:a83a44a1c2b4c996886722068ff359d8f"><td class="mdescLeft"> </td><td class="mdescRight">(CMCC) Cache Monitor Status Register <br /></td></tr>
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<tr class="separator:a83a44a1c2b4c996886722068ff359d8f"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for CMCC. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="instance_2cmcc_8h_source.html">cmcc.h</a>.</p>
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