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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/ramecc.h Source File</title>
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<div id="projectname">SAME54P20A Test Project
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<ul>
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_2bb2e10400507f879251f0324a0a8c7c.html">component</a></li> </ul>
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<div class="header">
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<div class="headertitle">
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<div class="title">ramecc.h</div> </div>
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</div><!--header-->
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<div class="contents">
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<a href="component_2ramecc_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_RAMECC_COMPONENT_</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_RAMECC_COMPONENT_</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========================================================================== */</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="comment">/* ========================================================================== */</span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span>  </div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define RAMECC_U2268</span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REV_RAMECC 0x100</span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span>  </div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="comment">/* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x0) (R/W 8) Interrupt Enable Clear -------- */</span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"><a class="line" href="unionRAMECC__INTENCLR__Type.html"> 44</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00046"></a><span class="lineno"><a class="line" href="unionRAMECC__INTENCLR__Type.html#a9d1cdd538022a6d946ddaa7a309adb3d"> 46</a></span>  uint8_t <a class="code" href="unionRAMECC__INTENCLR__Type.html#a9d1cdd538022a6d946ddaa7a309adb3d">SINGLEE</a>:1; </div>
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<div class="line"><a name="l00047"></a><span class="lineno"><a class="line" href="unionRAMECC__INTENCLR__Type.html#afab0e25b8ab8f40beb6235a0a6a2790b"> 47</a></span>  uint8_t <a class="code" href="unionRAMECC__INTENCLR__Type.html#afab0e25b8ab8f40beb6235a0a6a2790b">DUALE</a>:1; </div>
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<div class="line"><a name="l00048"></a><span class="lineno"><a class="line" href="unionRAMECC__INTENCLR__Type.html#a62e1cee1398f0a6b6330c578c5646fbb"> 48</a></span>  uint8_t :6; </div>
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<div class="line"><a name="l00049"></a><span class="lineno"><a class="line" href="unionRAMECC__INTENCLR__Type.html#acde9081a98614151f02e7cb1beedcb3d"> 49</a></span>  } bit; </div>
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<div class="line"><a name="l00050"></a><span class="lineno"><a class="line" href="unionRAMECC__INTENCLR__Type.html#a4ccb41c26ef2ddb58920d249cdb05ba2"> 50</a></span>  uint8_t <a class="code" href="unionRAMECC__INTENCLR__Type.html#a4ccb41c26ef2ddb58920d249cdb05ba2">reg</a>; </div>
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<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> } <a class="code" href="unionRAMECC__INTENCLR__Type.html">RAMECC_INTENCLR_Type</a>;</div>
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<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span>  </div>
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<div class="line"><a name="l00054"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a6ecdeaa86842a9b5a0a99abede67f384"> 54</a></span> <span class="preprocessor">#define RAMECC_INTENCLR_OFFSET 0x0 </span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#af905d7a6bc86a37d0e957904ae1c1847"> 55</a></span> <span class="preprocessor">#define RAMECC_INTENCLR_RESETVALUE _U_(0x00) </span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#ad78892cf766a2ceea0c07e82236954ea"> 57</a></span> <span class="preprocessor">#define RAMECC_INTENCLR_SINGLEE_Pos 0 </span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define RAMECC_INTENCLR_SINGLEE (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos)</span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#aa8f8f8016d8b11f20868660762d61636"> 59</a></span> <span class="preprocessor">#define RAMECC_INTENCLR_DUALE_Pos 1 </span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor">#define RAMECC_INTENCLR_DUALE (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos)</span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#ac2d16480713fd62c82cd54b94d894ea1"> 61</a></span> <span class="preprocessor">#define RAMECC_INTENCLR_MASK _U_(0x03) </span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor"></span><span class="comment">/* -------- RAMECC_INTENSET : (RAMECC Offset: 0x1) (R/W 8) Interrupt Enable Set -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="unionRAMECC__INTENSET__Type.html"> 65</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00066"></a><span class="lineno"> 66</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="unionRAMECC__INTENSET__Type.html#ac3bca61e09b406e033c6c11ad25424b1"> 67</a></span>  uint8_t <a class="code" href="unionRAMECC__INTENSET__Type.html#ac3bca61e09b406e033c6c11ad25424b1">SINGLEE</a>:1; </div>
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<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="unionRAMECC__INTENSET__Type.html#aa3bb1a4e499095a54ee97635de0474c7"> 68</a></span>  uint8_t <a class="code" href="unionRAMECC__INTENSET__Type.html#aa3bb1a4e499095a54ee97635de0474c7">DUALE</a>:1; </div>
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<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="unionRAMECC__INTENSET__Type.html#a6205d4c97f5b61b34cca56fd03ccad7b"> 69</a></span>  uint8_t :6; </div>
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<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="unionRAMECC__INTENSET__Type.html#a5a3c98fedeed73299d4e83ec8d9ec677"> 70</a></span>  } bit; </div>
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<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="unionRAMECC__INTENSET__Type.html#a7fd56076817b424b3800d2c63cb8c7d8"> 71</a></span>  uint8_t <a class="code" href="unionRAMECC__INTENSET__Type.html#a7fd56076817b424b3800d2c63cb8c7d8">reg</a>; </div>
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<div class="line"><a name="l00072"></a><span class="lineno"> 72</span> } <a class="code" href="unionRAMECC__INTENSET__Type.html">RAMECC_INTENSET_Type</a>;</div>
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<div class="line"><a name="l00073"></a><span class="lineno"> 73</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"> 74</span>  </div>
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<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#ac428cc201847ef38fdfccb09d43dfd05"> 75</a></span> <span class="preprocessor">#define RAMECC_INTENSET_OFFSET 0x1 </span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a1d0eda60a8a741fb277a5762c66f6664"> 76</a></span> <span class="preprocessor">#define RAMECC_INTENSET_RESETVALUE _U_(0x00) </span></div>
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<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a3f7d235551f4e8b801aa723b1dfd9d50"> 78</a></span> <span class="preprocessor">#define RAMECC_INTENSET_SINGLEE_Pos 0 </span></div>
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<div class="line"><a name="l00079"></a><span class="lineno"> 79</span> <span class="preprocessor">#define RAMECC_INTENSET_SINGLEE (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos)</span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a540bd256680ad5cc67e90d3d05ff3888"> 80</a></span> <span class="preprocessor">#define RAMECC_INTENSET_DUALE_Pos 1 </span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"> 81</span> <span class="preprocessor">#define RAMECC_INTENSET_DUALE (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos)</span></div>
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<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#afce3a73643801607c3b2953710448281"> 82</a></span> <span class="preprocessor">#define RAMECC_INTENSET_MASK _U_(0x03) </span></div>
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<div class="line"><a name="l00084"></a><span class="lineno"> 84</span> <span class="preprocessor"></span><span class="comment">/* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x2) (R/W 8) Interrupt Flag -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"> 85</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00086"></a><span class="lineno"><a class="line" href="unionRAMECC__INTFLAG__Type.html"> 86</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{ <span class="comment">// __I to avoid read-modify-write on write-to-clear register</span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"> 87</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="unionRAMECC__INTFLAG__Type.html#a6c86a13d1e675ad5534168693d1cd3b4"> 88</a></span>  __I uint8_t <a class="code" href="unionRAMECC__INTFLAG__Type.html#a6c86a13d1e675ad5534168693d1cd3b4">SINGLEE</a>:1; </div>
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<div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="unionRAMECC__INTFLAG__Type.html#a0e8e3d64b9b225a39bc8d5e24ca64c15"> 89</a></span>  __I uint8_t <a class="code" href="unionRAMECC__INTFLAG__Type.html#a0e8e3d64b9b225a39bc8d5e24ca64c15">DUALE</a>:1; </div>
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<div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="unionRAMECC__INTFLAG__Type.html#ae14a87cb17f6ed916491356b0c8f68d3"> 90</a></span>  __I <a class="code" href="unionRAMECC__INTFLAG__Type.html#ae14a87cb17f6ed916491356b0c8f68d3">uint8_t</a> :6; </div>
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<div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="unionRAMECC__INTFLAG__Type.html#adb8411891ad4f745661a0e3660fd7796"> 91</a></span>  } bit; </div>
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<div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="unionRAMECC__INTFLAG__Type.html#a81c09b15fe5c6f6d0091ac7c8445230e"> 92</a></span>  uint8_t <a class="code" href="unionRAMECC__INTFLAG__Type.html#a81c09b15fe5c6f6d0091ac7c8445230e">reg</a>; </div>
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<div class="line"><a name="l00093"></a><span class="lineno"> 93</span> } <a class="code" href="unionRAMECC__INTFLAG__Type.html">RAMECC_INTFLAG_Type</a>;</div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span>  </div>
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<div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a97ba817ff23664a405979a16c296adb5"> 96</a></span> <span class="preprocessor">#define RAMECC_INTFLAG_OFFSET 0x2 </span></div>
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<div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a75316aa5bf2764aef9342ab9e97102ce"> 97</a></span> <span class="preprocessor">#define RAMECC_INTFLAG_RESETVALUE _U_(0x00) </span></div>
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<div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a670716fa90c43dec438166271e62b842"> 99</a></span> <span class="preprocessor">#define RAMECC_INTFLAG_SINGLEE_Pos 0 </span></div>
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<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor">#define RAMECC_INTFLAG_SINGLEE (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos)</span></div>
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<div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#aa3e61ae09b527a9e0ab2a4621aa20959"> 101</a></span> <span class="preprocessor">#define RAMECC_INTFLAG_DUALE_Pos 1 </span></div>
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<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="preprocessor">#define RAMECC_INTFLAG_DUALE (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos)</span></div>
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<div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a53cbb484920b486324488c1e6e04fcba"> 103</a></span> <span class="preprocessor">#define RAMECC_INTFLAG_MASK _U_(0x03) </span></div>
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<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor"></span><span class="comment">/* -------- RAMECC_STATUS : (RAMECC Offset: 0x3) (R/ 8) Status -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="unionRAMECC__STATUS__Type.html"> 107</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00108"></a><span class="lineno"> 108</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="unionRAMECC__STATUS__Type.html#a1a3d492f6e8eb23ba582b4a99c564a61"> 109</a></span>  uint8_t <a class="code" href="unionRAMECC__STATUS__Type.html#a1a3d492f6e8eb23ba582b4a99c564a61">ECCDIS</a>:1; </div>
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<div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="unionRAMECC__STATUS__Type.html#ac8167f7e22ac2360bad48df69a246136"> 110</a></span>  uint8_t :7; </div>
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<div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="unionRAMECC__STATUS__Type.html#ac51d19fd2a23d1037b3719ad750db0d6"> 111</a></span>  } bit; </div>
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<div class="line"><a name="l00112"></a><span class="lineno"><a class="line" href="unionRAMECC__STATUS__Type.html#a71d7ad8cfea8ede09ddc6e544915841c"> 112</a></span>  uint8_t <a class="code" href="unionRAMECC__STATUS__Type.html#a71d7ad8cfea8ede09ddc6e544915841c">reg</a>; </div>
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<div class="line"><a name="l00113"></a><span class="lineno"> 113</span> } <a class="code" href="unionRAMECC__STATUS__Type.html">RAMECC_STATUS_Type</a>;</div>
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<div class="line"><a name="l00114"></a><span class="lineno"> 114</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00115"></a><span class="lineno"> 115</span>  </div>
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<div class="line"><a name="l00116"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a92482bf7dca87d60e43bff04febe1726"> 116</a></span> <span class="preprocessor">#define RAMECC_STATUS_OFFSET 0x3 </span></div>
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<div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#ade15049c636df2ad5882e1b6798b8799"> 117</a></span> <span class="preprocessor">#define RAMECC_STATUS_RESETVALUE _U_(0x00) </span></div>
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<div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#aad3526dd29623bdf0b6b017385ce8cee"> 119</a></span> <span class="preprocessor">#define RAMECC_STATUS_ECCDIS_Pos 0 </span></div>
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<div class="line"><a name="l00120"></a><span class="lineno"> 120</span> <span class="preprocessor">#define RAMECC_STATUS_ECCDIS (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos)</span></div>
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<div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a7744be01916c51171405466f2f5e77fa"> 121</a></span> <span class="preprocessor">#define RAMECC_STATUS_MASK _U_(0x01) </span></div>
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<div class="line"><a name="l00123"></a><span class="lineno"> 123</span> <span class="preprocessor"></span><span class="comment">/* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x4) (R/ 32) Error Address -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00124"></a><span class="lineno"> 124</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="unionRAMECC__ERRADDR__Type.html"> 125</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00126"></a><span class="lineno"> 126</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="unionRAMECC__ERRADDR__Type.html#a16378b1a0ad77b11b8da2246e0467c52"> 127</a></span>  uint32_t <a class="code" href="unionRAMECC__ERRADDR__Type.html#a16378b1a0ad77b11b8da2246e0467c52">ERRADDR</a>:17; </div>
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<div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="unionRAMECC__ERRADDR__Type.html#ad1a2d1241781fbb44c5358ff46749587"> 128</a></span>  uint32_t :15; </div>
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<div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="unionRAMECC__ERRADDR__Type.html#af9e671ba228327d47ee2edcd2a67f88a"> 129</a></span>  } bit; </div>
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<div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="unionRAMECC__ERRADDR__Type.html#a16e4a3edcb563711fbe80987b248cc4d"> 130</a></span>  uint32_t <a class="code" href="unionRAMECC__ERRADDR__Type.html#a16e4a3edcb563711fbe80987b248cc4d">reg</a>; </div>
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<div class="line"><a name="l00131"></a><span class="lineno"> 131</span> } <a class="code" href="unionRAMECC__ERRADDR__Type.html">RAMECC_ERRADDR_Type</a>;</div>
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<div class="line"><a name="l00132"></a><span class="lineno"> 132</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00133"></a><span class="lineno"> 133</span>  </div>
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<div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#ae1210dedbd55a1583bebd5ee8870d5dc"> 134</a></span> <span class="preprocessor">#define RAMECC_ERRADDR_OFFSET 0x4 </span></div>
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<div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a421c81f0ceb471869a0dad27520761bb"> 135</a></span> <span class="preprocessor">#define RAMECC_ERRADDR_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#aa78357b85c2bc9531d87c2a7ffb94490"> 137</a></span> <span class="preprocessor">#define RAMECC_ERRADDR_ERRADDR_Pos 0 </span></div>
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<div class="line"><a name="l00138"></a><span class="lineno"> 138</span> <span class="preprocessor">#define RAMECC_ERRADDR_ERRADDR_Msk (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos)</span></div>
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<div class="line"><a name="l00139"></a><span class="lineno"> 139</span> <span class="preprocessor">#define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))</span></div>
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<div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#abd318720c748f4880ae7db2f304f48ed"> 140</a></span> <span class="preprocessor">#define RAMECC_ERRADDR_MASK _U_(0x0001FFFF) </span></div>
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<div class="line"><a name="l00142"></a><span class="lineno"> 142</span> <span class="preprocessor"></span><span class="comment">/* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0xF) (R/W 8) Debug Control -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00143"></a><span class="lineno"> 143</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="unionRAMECC__DBGCTRL__Type.html"> 144</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00145"></a><span class="lineno"> 145</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="unionRAMECC__DBGCTRL__Type.html#ad3b3c5e771c441563133ff08403ba4ea"> 146</a></span>  uint8_t <a class="code" href="unionRAMECC__DBGCTRL__Type.html#ad3b3c5e771c441563133ff08403ba4ea">ECCDIS</a>:1; </div>
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<div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="unionRAMECC__DBGCTRL__Type.html#a8768634ba192fbd104244d5aa4bee6f9"> 147</a></span>  uint8_t <a class="code" href="unionRAMECC__DBGCTRL__Type.html#a8768634ba192fbd104244d5aa4bee6f9">ECCELOG</a>:1; </div>
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<div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="unionRAMECC__DBGCTRL__Type.html#ad81f91d9fa68abfcf53be98efbe4f8dc"> 148</a></span>  uint8_t :6; </div>
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<div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="unionRAMECC__DBGCTRL__Type.html#a7a0c35e637182ac8a7974ea883178b39"> 149</a></span>  } bit; </div>
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<div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="unionRAMECC__DBGCTRL__Type.html#a388bfce6dc7a139d9484ec8ff9bbbd03"> 150</a></span>  uint8_t <a class="code" href="unionRAMECC__DBGCTRL__Type.html#a388bfce6dc7a139d9484ec8ff9bbbd03">reg</a>; </div>
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<div class="line"><a name="l00151"></a><span class="lineno"> 151</span> } <a class="code" href="unionRAMECC__DBGCTRL__Type.html">RAMECC_DBGCTRL_Type</a>;</div>
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<div class="line"><a name="l00152"></a><span class="lineno"> 152</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00153"></a><span class="lineno"> 153</span>  </div>
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<div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a95f3d6ef123e45e0583164ae6ac03544"> 154</a></span> <span class="preprocessor">#define RAMECC_DBGCTRL_OFFSET 0xF </span></div>
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<div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#aed80d19f1724acee50967a8212ee2b1c"> 155</a></span> <span class="preprocessor">#define RAMECC_DBGCTRL_RESETVALUE _U_(0x00) </span></div>
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<div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#aa5972c5e97ddb80048f2a045f8789b96"> 157</a></span> <span class="preprocessor">#define RAMECC_DBGCTRL_ECCDIS_Pos 0 </span></div>
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<div class="line"><a name="l00158"></a><span class="lineno"> 158</span> <span class="preprocessor">#define RAMECC_DBGCTRL_ECCDIS (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos)</span></div>
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<div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#ad80a79467c2c1661d1a7dc3d03376fd8"> 159</a></span> <span class="preprocessor">#define RAMECC_DBGCTRL_ECCELOG_Pos 1 </span></div>
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<div class="line"><a name="l00160"></a><span class="lineno"> 160</span> <span class="preprocessor">#define RAMECC_DBGCTRL_ECCELOG (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos)</span></div>
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<div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="component_2ramecc_8h.html#a1b3536513c7d5d946dc77a753c0bf2fb"> 161</a></span> <span class="preprocessor">#define RAMECC_DBGCTRL_MASK _U_(0x03) </span></div>
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<div class="line"><a name="l00164"></a><span class="lineno"> 164</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="structRamecc.html"> 165</a></span> <span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="structRamecc.html#a0ab08cb00c7dbb1928723621a5c2e98b"> 166</a></span>  __IO <a class="code" href="unionRAMECC__INTENCLR__Type.html">RAMECC_INTENCLR_Type</a> <a class="code" href="structRamecc.html#a0ab08cb00c7dbb1928723621a5c2e98b">INTENCLR</a>; </div>
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<div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="structRamecc.html#ac8dad5ebd0322b3dea84ab8838109e3a"> 167</a></span>  __IO <a class="code" href="unionRAMECC__INTENSET__Type.html">RAMECC_INTENSET_Type</a> <a class="code" href="structRamecc.html#ac8dad5ebd0322b3dea84ab8838109e3a">INTENSET</a>; </div>
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<div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="structRamecc.html#aa8b70758e67cb15f134ef1a0ae8a3513"> 168</a></span>  __IO <a class="code" href="unionRAMECC__INTFLAG__Type.html">RAMECC_INTFLAG_Type</a> <a class="code" href="structRamecc.html#aa8b70758e67cb15f134ef1a0ae8a3513">INTFLAG</a>; </div>
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<div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="structRamecc.html#af5cf55200d059eff323c18a8d8636332"> 169</a></span>  __I <a class="code" href="unionRAMECC__STATUS__Type.html">RAMECC_STATUS_Type</a> <a class="code" href="structRamecc.html#af5cf55200d059eff323c18a8d8636332">STATUS</a>; </div>
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<div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="structRamecc.html#ae8ee769b2af7eb4f37263a301cd8e53b"> 170</a></span>  __I <a class="code" href="unionRAMECC__ERRADDR__Type.html">RAMECC_ERRADDR_Type</a> <a class="code" href="structRamecc.html#ae8ee769b2af7eb4f37263a301cd8e53b">ERRADDR</a>; </div>
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<div class="line"><a name="l00171"></a><span class="lineno"> 171</span>  <a class="code" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> Reserved1[0x7];</div>
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<div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="structRamecc.html#ac8796cbdb0b3d610174ba0e025a9fb56"> 172</a></span>  __IO <a class="code" href="unionRAMECC__DBGCTRL__Type.html">RAMECC_DBGCTRL_Type</a> <a class="code" href="structRamecc.html#ac8796cbdb0b3d610174ba0e025a9fb56">DBGCTRL</a>; </div>
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<div class="line"><a name="l00173"></a><span class="lineno"> 173</span> } <a class="code" href="structRamecc.html">Ramecc</a>;</div>
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<div class="line"><a name="l00174"></a><span class="lineno"> 174</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00175"></a><span class="lineno"> 175</span>  </div>
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<div class="line"><a name="l00178"></a><span class="lineno"> 178</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_RAMECC_COMPONENT_ */</span><span class="preprocessor"></span></div>
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</div><!-- fragment --></div><!-- contents -->
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<div class="ttc" id="aunionRAMECC__DBGCTRL__Type_html_ad3b3c5e771c441563133ff08403ba4ea"><div class="ttname"><a href="unionRAMECC__DBGCTRL__Type.html#ad3b3c5e771c441563133ff08403ba4ea">RAMECC_DBGCTRL_Type::ECCDIS</a></div><div class="ttdeci">uint8_t ECCDIS</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00146">ramecc.h:146</a></div></div>
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<div class="ttc" id="astructRamecc_html_af5cf55200d059eff323c18a8d8636332"><div class="ttname"><a href="structRamecc.html#af5cf55200d059eff323c18a8d8636332">Ramecc::STATUS</a></div><div class="ttdeci">__I RAMECC_STATUS_Type STATUS</div><div class="ttdoc">Offset: 0x3 (R/ 8) Status.</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00169">ramecc.h:169</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTFLAG__Type_html_a81c09b15fe5c6f6d0091ac7c8445230e"><div class="ttname"><a href="unionRAMECC__INTFLAG__Type.html#a81c09b15fe5c6f6d0091ac7c8445230e">RAMECC_INTFLAG_Type::reg</a></div><div class="ttdeci">uint8_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00092">ramecc.h:92</a></div></div>
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<div class="ttc" id="aunionRAMECC__STATUS__Type_html_a1a3d492f6e8eb23ba582b4a99c564a61"><div class="ttname"><a href="unionRAMECC__STATUS__Type.html#a1a3d492f6e8eb23ba582b4a99c564a61">RAMECC_STATUS_Type::ECCDIS</a></div><div class="ttdeci">uint8_t ECCDIS</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00109">ramecc.h:109</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTENSET__Type_html_a7fd56076817b424b3800d2c63cb8c7d8"><div class="ttname"><a href="unionRAMECC__INTENSET__Type.html#a7fd56076817b424b3800d2c63cb8c7d8">RAMECC_INTENSET_Type::reg</a></div><div class="ttdeci">uint8_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00071">ramecc.h:71</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTFLAG__Type_html_a6c86a13d1e675ad5534168693d1cd3b4"><div class="ttname"><a href="unionRAMECC__INTFLAG__Type.html#a6c86a13d1e675ad5534168693d1cd3b4">RAMECC_INTFLAG_Type::SINGLEE</a></div><div class="ttdeci">__I uint8_t SINGLEE</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00088">ramecc.h:88</a></div></div>
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<div class="ttc" id="astructRamecc_html"><div class="ttname"><a href="structRamecc.html">Ramecc</a></div><div class="ttdoc">RAMECC hardware registers.</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00165">ramecc.h:165</a></div></div>
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<div class="ttc" id="astructRamecc_html_ae8ee769b2af7eb4f37263a301cd8e53b"><div class="ttname"><a href="structRamecc.html#ae8ee769b2af7eb4f37263a301cd8e53b">Ramecc::ERRADDR</a></div><div class="ttdeci">__I RAMECC_ERRADDR_Type ERRADDR</div><div class="ttdoc">Offset: 0x4 (R/ 32) Error Address.</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00170">ramecc.h:170</a></div></div>
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<div class="ttc" id="aunionRAMECC__STATUS__Type_html_a71d7ad8cfea8ede09ddc6e544915841c"><div class="ttname"><a href="unionRAMECC__STATUS__Type.html#a71d7ad8cfea8ede09ddc6e544915841c">RAMECC_STATUS_Type::reg</a></div><div class="ttdeci">uint8_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00112">ramecc.h:112</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTENSET__Type_html_ac3bca61e09b406e033c6c11ad25424b1"><div class="ttname"><a href="unionRAMECC__INTENSET__Type.html#ac3bca61e09b406e033c6c11ad25424b1">RAMECC_INTENSET_Type::SINGLEE</a></div><div class="ttdeci">uint8_t SINGLEE</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00067">ramecc.h:67</a></div></div>
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<div class="ttc" id="aunionRAMECC__ERRADDR__Type_html_a16e4a3edcb563711fbe80987b248cc4d"><div class="ttname"><a href="unionRAMECC__ERRADDR__Type.html#a16e4a3edcb563711fbe80987b248cc4d">RAMECC_ERRADDR_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00130">ramecc.h:130</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTFLAG__Type_html_ae14a87cb17f6ed916491356b0c8f68d3"><div class="ttname"><a href="unionRAMECC__INTFLAG__Type.html#ae14a87cb17f6ed916491356b0c8f68d3">RAMECC_INTFLAG_Type::uint8_t</a></div><div class="ttdeci">__I uint8_t</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00090">ramecc.h:90</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTENCLR__Type_html_a9d1cdd538022a6d946ddaa7a309adb3d"><div class="ttname"><a href="unionRAMECC__INTENCLR__Type.html#a9d1cdd538022a6d946ddaa7a309adb3d">RAMECC_INTENCLR_Type::SINGLEE</a></div><div class="ttdeci">uint8_t SINGLEE</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00046">ramecc.h:46</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTENCLR__Type_html"><div class="ttname"><a href="unionRAMECC__INTENCLR__Type.html">RAMECC_INTENCLR_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00044">ramecc.h:44</a></div></div>
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<div class="ttc" id="aunionRAMECC__DBGCTRL__Type_html_a388bfce6dc7a139d9484ec8ff9bbbd03"><div class="ttname"><a href="unionRAMECC__DBGCTRL__Type.html#a388bfce6dc7a139d9484ec8ff9bbbd03">RAMECC_DBGCTRL_Type::reg</a></div><div class="ttdeci">uint8_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00150">ramecc.h:150</a></div></div>
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<div class="ttc" id="aunionRAMECC__ERRADDR__Type_html_a16378b1a0ad77b11b8da2246e0467c52"><div class="ttname"><a href="unionRAMECC__ERRADDR__Type.html#a16378b1a0ad77b11b8da2246e0467c52">RAMECC_ERRADDR_Type::ERRADDR</a></div><div class="ttdeci">uint32_t ERRADDR</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00127">ramecc.h:127</a></div></div>
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<div class="ttc" id="aunionRAMECC__DBGCTRL__Type_html"><div class="ttname"><a href="unionRAMECC__DBGCTRL__Type.html">RAMECC_DBGCTRL_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00144">ramecc.h:144</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTENSET__Type_html_aa3bb1a4e499095a54ee97635de0474c7"><div class="ttname"><a href="unionRAMECC__INTENSET__Type.html#aa3bb1a4e499095a54ee97635de0474c7">RAMECC_INTENSET_Type::DUALE</a></div><div class="ttdeci">uint8_t DUALE</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00068">ramecc.h:68</a></div></div>
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<div class="ttc" id="aunionRAMECC__STATUS__Type_html"><div class="ttname"><a href="unionRAMECC__STATUS__Type.html">RAMECC_STATUS_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00107">ramecc.h:107</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTENSET__Type_html"><div class="ttname"><a href="unionRAMECC__INTENSET__Type.html">RAMECC_INTENSET_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00065">ramecc.h:65</a></div></div>
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<div class="ttc" id="astructRamecc_html_ac8796cbdb0b3d610174ba0e025a9fb56"><div class="ttname"><a href="structRamecc.html#ac8796cbdb0b3d610174ba0e025a9fb56">Ramecc::DBGCTRL</a></div><div class="ttdeci">__IO RAMECC_DBGCTRL_Type DBGCTRL</div><div class="ttdoc">Offset: 0xF (R/W 8) Debug Control.</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00172">ramecc.h:172</a></div></div>
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<div class="ttc" id="astructRamecc_html_ac8dad5ebd0322b3dea84ab8838109e3a"><div class="ttname"><a href="structRamecc.html#ac8dad5ebd0322b3dea84ab8838109e3a">Ramecc::INTENSET</a></div><div class="ttdeci">__IO RAMECC_INTENSET_Type INTENSET</div><div class="ttdoc">Offset: 0x1 (R/W 8) Interrupt Enable Set.</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00167">ramecc.h:167</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTFLAG__Type_html_a0e8e3d64b9b225a39bc8d5e24ca64c15"><div class="ttname"><a href="unionRAMECC__INTFLAG__Type.html#a0e8e3d64b9b225a39bc8d5e24ca64c15">RAMECC_INTFLAG_Type::DUALE</a></div><div class="ttdeci">__I uint8_t DUALE</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00089">ramecc.h:89</a></div></div>
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<div class="ttc" id="astructRamecc_html_a0ab08cb00c7dbb1928723621a5c2e98b"><div class="ttname"><a href="structRamecc.html#a0ab08cb00c7dbb1928723621a5c2e98b">Ramecc::INTENCLR</a></div><div class="ttdeci">__IO RAMECC_INTENCLR_Type INTENCLR</div><div class="ttdoc">Offset: 0x0 (R/W 8) Interrupt Enable Clear.</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00166">ramecc.h:166</a></div></div>
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<div class="ttc" id="aunionRAMECC__DBGCTRL__Type_html_a8768634ba192fbd104244d5aa4bee6f9"><div class="ttname"><a href="unionRAMECC__DBGCTRL__Type.html#a8768634ba192fbd104244d5aa4bee6f9">RAMECC_DBGCTRL_Type::ECCELOG</a></div><div class="ttdeci">uint8_t ECCELOG</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00147">ramecc.h:147</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTENCLR__Type_html_afab0e25b8ab8f40beb6235a0a6a2790b"><div class="ttname"><a href="unionRAMECC__INTENCLR__Type.html#afab0e25b8ab8f40beb6235a0a6a2790b">RAMECC_INTENCLR_Type::DUALE</a></div><div class="ttdeci">uint8_t DUALE</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00047">ramecc.h:47</a></div></div>
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<div class="ttc" id="asame54n19a_8h_html_a0d957f1433aaf5d70e4dc2b68288442d"><div class="ttname"><a href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a></div><div class="ttdeci">volatile const uint8_t RoReg8</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00053">same54n19a.h:53</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTENCLR__Type_html_a4ccb41c26ef2ddb58920d249cdb05ba2"><div class="ttname"><a href="unionRAMECC__INTENCLR__Type.html#a4ccb41c26ef2ddb58920d249cdb05ba2">RAMECC_INTENCLR_Type::reg</a></div><div class="ttdeci">uint8_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00050">ramecc.h:50</a></div></div>
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<div class="ttc" id="aunionRAMECC__INTFLAG__Type_html"><div class="ttname"><a href="unionRAMECC__INTFLAG__Type.html">RAMECC_INTFLAG_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00086">ramecc.h:86</a></div></div>
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<div class="ttc" id="astructRamecc_html_aa8b70758e67cb15f134ef1a0ae8a3513"><div class="ttname"><a href="structRamecc.html#aa8b70758e67cb15f134ef1a0ae8a3513">Ramecc::INTFLAG</a></div><div class="ttdeci">__IO RAMECC_INTFLAG_Type INTFLAG</div><div class="ttdoc">Offset: 0x2 (R/W 8) Interrupt Flag.</div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00168">ramecc.h:168</a></div></div>
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<div class="ttc" id="aunionRAMECC__ERRADDR__Type_html"><div class="ttname"><a href="unionRAMECC__ERRADDR__Type.html">RAMECC_ERRADDR_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2ramecc_8h_source.html#l00125">ramecc.h:125</a></div></div>
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